Universal reset system applied to FPGA chip configuration circuit

Abstract

The invention provides a universal reset system applied to an FPGA chip configuration circuit, and relates to the technical field of universal reset, reset signals generated in the FPGA configuration process are classified through a reset request circuit, and preset signal processing is executed according to preset function scenes and priorities; selecting a plurality of reset requests through a reset selection circuit, and responding to the reset requests according to a preset priority sequence; a reset signal from a reset request circuit is synchronously processed through a reset synchronous processing circuit, and the control signal is transmitted between clock domains; after the reset operation is completed through the reset release circuit, the FPGA is converted from the reset state to the normal working state, the FPGA configuration reset circuit can meet the FPGA configuration reset requirements in various scenes, and the metastable state problem in the reset signal transmission process can be effectively solved.

Description

Technical Field

[0001] The present invention provides a general reset system applied to an FPGA chip configuration circuit, which relates to the technical field of general reset, and specifically relates to the technical field of general reset of an FPGA chip configuration circuit. Background Art

[0002] The purpose of reset is to force the system to be set to an initial and predictable state when the system starts up or when an internal circuit function goes wrong. Compared with traditional reset methods, this design can solve the metastability problem in the reset transmission process.

[0003] However, traditional reset methods often have some limitations, such as problems like transmission delay of the reset signal, signal jitter, and reset failure caused by power fluctuations. These problems may cause the system to fail to initialize correctly or to exhibit unstable states during initialization, thus affecting the stability and reliability of the entire system. In addition, with the development of integrated circuit technology, the scale and complexity of FPGAs are constantly increasing, and the performance requirements for the reset system are also getting higher and higher. Summary of the Invention

[0004] The present invention provides a general reset system that can adapt to complex circuit environments and has high stability and reliability to solve the above problems existing in the prior art:

[0005] A general reset system applied to an FPGA chip configuration circuit proposed by the present invention, the system includes a reset request circuit, a reset selection circuit, a reset synchronization processing circuit, and a reset release circuit;

[0006] The reset request circuit is used to classify the reset signals generated during the FPGA configuration process and perform corresponding signal processing according to preset functional scenarios and priorities; the signal processing includes filtering out glitches, widening, and synchronization;

[0007] The reset selection circuit is used to select among multiple reset requests and control the system to respond to the reset requests in the preset priority order;

[0008] The reset synchronization processing circuit is used to perform synchronization processing and transmission on the reset signals from the reset request circuit;

[0009] The reset release circuit is responsible for safely guiding the FPGA from the reset state to the normal working state after the reset operation is completed.

[0010] Furthermore, the reset request circuit is connected to a configuration reset module;

[0011] The configuration reset module includes USER, FALLBACK, PROGRAM, and PROGRAMSCUB;

[0012] USER is used to detect the user instantiated startup primitive in user mode and generate a USER reset request in encryption / decryption mode;

[0013] FALLBACK is used to generate a FALLBACK reset request when errors such as ID_ERR, CRC_ERR, or WTO_ERR are detected in configuration mode;

[0014] PROGRAM is used to perform a forced reset operation during the configuration process. It consists of PROGRAM_B, JPROGRAM, and ISC_PROGRAM_KEY_RESET, and resets all registers according to preset requirement information;

[0015] PROGRAMSCUB is used to reload the bitstream through self-refresh trigger and reset all registers according to preset requirement information.

[0016] Furthermore, the reset request circuit includes a glitch removal module and a widening module;

[0017] The glitch removal module is used to perform glitch processing on the initial reset signal after the reset initial signal arrives at the reset request module;

[0018] The widening module is used to widen a single clock cycle signal: tap the signal in its clock domain, perform an operation on the tapped signal and the signal before tapping, and obtain the corresponding widened signal.

[0019] Furthermore, the reset selection circuit includes an active control module and an inactive control module;

[0020] The reset sources are divided into user mode and configuration mode;

[0021] The active control module is used to, when pack_active is active, in user mode, when an error occurs, send a PREQ signal to the user through the STARTUP primitive and determine whether to send a response to the reset system through the STARTUP primitive;

[0022] The inactive control module is used to generate a reset request by default in configuration mode when pack_active is inactive.

[0023] Furthermore, the reset selection circuit further includes a reset control unit;

[0024] The reset control unit is used to receive reset request signals from different reset sources;

[0025] The reset control unit includes a triple modular redundancy circuit;

[0026] The triple modular redundancy circuit is used to receive each reset signal through the clock terminals of the triple modular redundancy. After the outputs of the three flip - flops are ANDed, only when all three flip - flops are valid, the final output will be valid, and then error correction is performed.

[0027] Further, the reset synchronization processing circuit includes an asynchronous reset module and a synchronization processing module;

[0028] The asynchronous reset module is used to control the reset signal not to be affected by the clock signal and perform a reset at a low level;

[0029] The synchronization processing module is used to synchronize the target signal RST_N with the clock CP when the reset is invalid.

[0030] Further, the reset release module includes a clock cycle monitoring module, a delay cycle monitoring module, and a high - level output module;

[0031] The clock cycle monitoring module is used to monitor a specific clock cycle;

[0032] The delay cycle monitoring module is used to obtain an additional delay cycle;

[0033] The high - level output module is used to output a high - level signal indicating the end of the reset state when a specific clock cycle and an additional delay cycle are obtained; the high - level signal passes through the logic gate circuit inside the FPGA to convert the entire system from the reset state to the normal working state.

[0034] Further, the general reset method includes:

[0035] Classify the reset signals generated during the FPGA configuration process through the reset request circuit, and perform preset signal processing according to the preset functional scenarios and priorities. The signal processing includes filtering out glitches, widening, and synchronization;

[0036] Select among multiple reset requests through the reset selection circuit and respond to the reset requests in the predetermined priority order;

[0037] Synchronize the reset signals from the reset request circuit through the reset synchronization processing circuit to control the signal transmission between clock domains;

[0038] After the reset operation is completed, convert the FPGA from the reset state to the normal working state through the reset release circuit.

[0039] Further, the configuration reset method of the reset request circuit includes:

[0040] Perform USER reset in user mode. When the user instantiates the startup primitive, in the encryption / decryption mode, generate a USER reset request;

[0041] Perform FALLBACK reset in configuration mode. When detecting ID_ERR, CRC_ERR, or WTO_ERR errors, generate a FALLBACK reset request;

[0042] Perform a forced reset operation during the configuration process through PROGRAM reset, which consists of PROGRAM_B and ISC_PROGRAM_KEY_RESET, and reset all registers;

[0043] Trigger PROGRAMSCUB reset through self-refresh, reload the bitstream, and reset all registers;

[0044] Debounce the USER, FALLBACK, PROGRAM, and PROGRAMSCUB signals, and then widen the single clock cycle signals:

[0045] Latch the corresponding signal in its clock domain, perform an operation on the latched signal and the signal before latching to obtain the corresponding widened signal;

[0046] After widening, perform two-clock-cycle synchronization processing on the signal in the corresponding clock domain. The signal after processing is the qualified reset request signal.

[0047] Furthermore, the debouncing of the USER, FALLBACK, PROGRAM, and PROGRAMSCUB signals includes:

[0048] When the glitch is active high, latch the signal generating the glitch twice with the target clock, and perform an AND operation on the signal after the second latch and the signal after the first latch to obtain glitch removal information;

[0049] When the glitch is active low, perform an OR operation on the signal after the second latch and the signal after the first latch.

[0050] Advantages of the present invention: The purpose of the present invention is to forcibly set the system to an initial and predictable state when the system starts up or when an error occurs in the internal module function. Compared with traditional reset methods, this design can solve the metastability problem in the reset transmission process.

[0051] Traditional reset methods often have some limitations, such as transmission delay of reset signals, signal jitter, and reset failure caused by power fluctuations. These problems may cause the system to fail to initialize correctly or exhibit unstable states during initialization, thus affecting the stability and reliability of the entire system. In addition, with the development of integrated circuit technology, the scale and complexity of FPGAs have been increasing, and the performance requirements for the reset system have also become higher and higher.

[0052] The present invention aims to provide a general reset system that can adapt to complex circuit environments and has high stability and reliability to solve the above problems existing in the prior art. This system is applicable to the FPGA configuration reset requirements in various scenarios and can effectively solve the metastability problem during the transmission of reset signals. By filtering out mis-triggered signals and signals that do not meet the conditions, the circuit can accurately identify and process correct reset signals; according to different working modes and system states, dynamically adjust the priority of reset requests, perform delay processing on reset signals to meet specific timing requirements, and ensure the accuracy and reliability of reset operations; control the duration of reset signals and release the reset signals at appropriate times to ensure that the FPGA can complete initialization correctly. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 Schematic diagram of a general reset system applied to an FPGA chip configuration circuit;

[0054] Figure 2 Circuit diagram for removing glitches effective for high level;

[0055] Figure 3 Timing diagram for removing glitches effective for high level;

[0056] Figure 4 Circuit diagram for removing glitches effective for low level;

[0057] Figure 5 Timing diagram for removing glitches effective for low level;

[0058] Figure 6 Schematic diagram of a reset selection circuit;

[0059] Figure 7 Schematic diagram of a triple modular redundancy circuit;

[0060] Figure 8 Schematic diagram of an asynchronous reset synchronous processing circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] The following describes the preferred embodiments of the present invention with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for the purpose of illustrating and explaining the present invention and are not intended to limit the present invention.

[0062] One embodiment of the present invention provides a universal reset system for an FPGA chip configuration circuit, the system comprising a reset request circuit, a reset selection circuit, a reset synchronization processing circuit and a reset release circuit;

[0063] The reset request circuit is used to classify the reset signals generated during the FPGA configuration process and perform corresponding signal processing according to preset functional scenarios and priorities; the signal processing includes filtering burrs, widening and synchronization;

[0064] The reset selection circuit is used to select among multiple reset requests, and the control system responds to the reset requests in a preset priority order;

[0065] The reset synchronization processing circuit is used to synchronously process and transmit the reset signal from the reset request circuit;

[0066] The reset release circuit is used to safely guide the FPGA from a reset state to a normal working state after the reset operation is completed.

[0067] The working principle of the above technical solution is as follows: This design has four modules, namely: reset request circuit, reset selection circuit, reset synchronization processing circuit, reset release circuit;

[0068] Reset request circuit: The reset request circuit is responsible for classifying the reset signals generated during the FPGA configuration process, based on factors such as functional scenarios and priorities, and performing corresponding signal processing: filtering burrs, widening and synchronization. This circuit is designed to improve signal stability, avoid false triggering, and ensure that the signal duration is sufficient to meet the trigger condition. By filtering out false trigger signals and signals that do not meet the conditions, the circuit can accurately identify and process the correct reset signal.

[0069] Reset selection circuit: The reset selection circuit is responsible for selecting among multiple reset requests to ensure that the system responds to reset requests in a predetermined priority order. This circuit uses an intelligent arbitration mechanism to effectively avoid conflicts when multiple reset requests occur simultaneously, ensuring that the system can enter the reset state stably. In addition, it can also dynamically adjust the priority of the reset request according to different working modes and system states to adapt to different operating environments.

[0070] Reset Synchronization Processing Circuit: The main function of the reset synchronization processing circuit is to synchronize the reset signals from the reset request circuit, ensuring that these signals are transmitted correctly between clock domains. By using synchronizers and clock domain crossing techniques, this circuit can effectively prevent signal distortion and data corruption caused by asynchronous clock domains. It can also delay the reset signals to meet specific timing requirements, ensuring the accuracy and reliability of the reset operation.

[0071] Reset Release Circuit: The reset release circuit is responsible for safely guiding the FPGA from the reset state to the normal operating state after the reset operation is completed. By precisely controlling the duration of the reset signal and releasing the reset signal at the appropriate time, this circuit ensures that the FPGA can correctly complete the initialization process. In addition, it can detect the system state after the reset is released to confirm whether the FPGA has stably entered the normal operating mode, thereby further improving the stability and reliability of the system.

[0072] The technical effects of the above technical solutions are as follows: The purpose of reset is to forcibly set the system to an initial and predictable state when starting up or when internal module functions encounter errors. Compared with traditional reset methods, this design can solve the metastability problem in the reset transmission process.

[0073] Traditional reset methods often have some limitations, such as transmission delays of reset signals, signal jitter, and reset failures caused by power fluctuations. These problems may prevent the system from being correctly initialized or cause unstable states during the initialization process, thereby affecting the stability and reliability of the entire system. In addition, with the development of integrated circuit technology, the scale and complexity of FPGAs are increasing, and the performance requirements for the reset system are also getting higher and higher.

[0074] The present invention aims to provide a general reset system that can adapt to complex circuit environments and has high stability and reliability to solve the above problems existing in the prior art. This system is applicable to the FPGA configuration reset requirements in various scenarios and can effectively solve the metastability problem in the reset signal transmission process. By filtering out mis-triggered signals and signals that do not meet the conditions, the circuit can accurately identify and process correct reset signals; according to different working modes and system states, dynamically adjust the priority of reset requests, delay the reset signals to meet specific timing requirements, and ensure the accuracy and reliability of the reset operation; control the duration of the reset signal and release the reset signal at the appropriate time to ensure that the FPGA can correctly complete the initialization.

[0075] In an embodiment of the present invention, the reset request circuit is connected to a configuration reset module;

[0076] The configuration reset module includes USER, FALLBACK, PROGRAM, and PROGRAMSCUB;

[0077] USER is used to detect the user instantiation of the startup primitive in user mode and generate a USER reset request in the encryption and decryption mode;

[0078] FALLBACK is used to generate a FALLBACK reset request when errors such as ID_ERR, CRC_ERR, or WTO_ERR are detected in configuration mode;

[0079] PROGRAM is used to perform a forced reset operation during the configuration process. It consists of PROGRAM_B, JPROGRAM, and ISC_PROGRAM_KEY_RESET, and resets all registers according to the preset requirement information;

[0080] PROGRAMSCUB is used to reload the bitstream through self-refresh triggering and reset all registers according to the preset requirement information.

[0081] The working principle of the above technical solution is as follows: Configuration reset is divided into four main categories: USER, FALLBACK, PROGRAM, and PROGRAMSCUB. Each category has its specific triggering conditions and functions. The reset request circuit generates different reset requests under different triggering conditions.

[0082] USER reset occurs in user mode when the user instantiation of the startup primitive is detected and generates a USER reset request in the encryption and decryption mode. In this scenario, in the subsequent reset selection circuit part, a request can be sent to the user. The user can agree to the reset or determine that it is a mis-trigger and intercept the reset for remedy, thus realizing the reset interception function.

[0083] FALLBACK reset is generated when errors such as ID_ERR, CRC_ERR, or WTO_ERR are detected in configuration mode. After passing through the reset synchronization processing circuit, other modules are ordered to perform a fallback operation and trigger a reset for initialization and reconfiguration. Also, when in the main bpi or main spi mode (two of the loading modes of the FPGA), when a multiboot operation is detected, the FPGA sends an uper address to the flash (flash memory) to update the bitstream. At the same time, the FPGA parses the iprog instruction from the bitstream, triggers a reset initialization, and then reloads the updated bitstream of the flash for reconfiguration.

[0084] The PROGRAM reset involves a forced reset operation during the configuration process and consists of PROGRAM_B (a fixed pin of the FPGA for forced reset initialization), JPROGRAM (one of the JTAG-related instructions with the same meaning as PROGRAM_B), and ISC_PROGRAM_KEY_RESET (the reset generated by the storage key module in non-secure mode). It can reset all registers and has the highest priority.

[0085] The PROGRAMSCUB reset (this reset means that during the readback process, when an error greater than 2 bits is detected, it is suspected that there is a problem with the FPGA configuration bits, and then the flash is reloaded to refresh the FPGA configuration bits) is triggered by self-refresh. The bitstream will be reloaded, and it can also reset all registers with the highest priority.

[0086] Among them, the FALLBACK reset can only reset the configuration registers except those related to multiboot. However, registers related to multiboot such as the timer register, BSPI register, and WBSTAR register cannot be reset by FALLBACK; the MULTIBOOT reset can reset all registers.

[0087] Term Explanation:

[0088] USER:

[0089] The user mode of the FPGA refers to the user working mode that the FPGA enters after the configuration loading is completed. At this time, the I / O ports of the FPGA work according to the user's designed functions. The configuration stage includes power-on, reset, initialization, and startup. After startup is completed, the FPGA enters the user mode.

[0090] MULTIBOOT:

[0091] MultiBoot is a way for the FPGA to remotely update the configuration file. To ensure security, we usually need to arrange a Golden Image. After the upgrade fails, the FPGA can fallback to this configuration so that the FPGA is always in a detectable working state.

[0092] FALLBACK:

[0093] MultiBoot and Fallback can support the realization of remote online FPGA upgrade. When there is an error in the upgraded bit, Fallback can be triggered to return to the Golden Image for normal operation. If an error occurs during the configuration stage or user stage of the FPGA, the FPGA will perform a fallback operation, reset and initialize again, load the Golden Image, block the iprog instruction, and when the fallback is completed, that is, the Golden Image is successfully loaded.

[0094] PROGRAM_SCUB:

[0095] When reading back and checking the CRC, if an error occurs, bitstream self-refresh can be triggered to perform self-refresh operation, which will trigger a reset to reset all registers, initialize, and reload the bitstream.

[0096] ID ERR:

[0097] Each FPGA has a specific model and a specific identity. This indication is written into the bitstream of the FPGA through the configuration register. When it is detected during the configuration process that the ID CODE does not match the internal setting of the FPGA, IDCODEERR will be generated.

[0098] CRC ERR:

[0099] The CRC_ERR error refers to a cyclic redundancy check error. CRC (Cyclic Redundancy Check) is a technology used to detect possible errors during data transmission or storage. When the CRC check sequence of the received data packet does not match the CRC result calculated by the sender, a CRC error occurs.

[0100] WTO_ERR:

[0101] The watchdog, also known as the watchdog timer, is essentially a timer circuit. When the program starts to execute, the timer starts to count down. When the program has not finished executing but the timer has reached zero, WTO_ERR will be triggered at this time. The function of the watchdog is to periodically check the internal situation of the chip and send a restart signal to the chip once an error occurs to prevent the system from falling into an infinite loop.

[0102] STARTUP primitive:

[0103] The primitive is a small module used to implement specific functions, usually used in FPGA designs. These primitives provide direct control over the hardware behavior, enabling designers to efficiently implement complex logic functions. The STARTUP primitive can be used on interface device ports and logic, and will output corresponding global reset, global tri-state signals, and also includes reset interception logic and clears the key management module.

[0104] Asynchronous reset synchronous processing:

[0105] A commonly used method to handle asynchronous reset can avoid the metastability caused by asynchronous reset.

[0106] PACK:

[0107] When users use the FPGA chip, they can use the built-in IP of the chip, the function module STARTUP primitive, which allows users to directly control the hardware behavior. If a reset request is generated, the user will obtain the reset request through the input signal PREQ of the STARTUP primitive. Then the user decides whether to perform a reset according to their own needs. If a reset occurs, the PACK signal is set to 1 through the STARTUP primitive, otherwise it is set to 0.

[0108] PREQ:

[0109] The input signal of the STARTUP primitive corresponding to PACK, which conveys the reset request signal to the user

[0110] PROGRAM_B:

[0111] The global reset pin, which can clear all configuration information inside the FPGA, return the FPGA to the configuration state, and reconfigure it. It is active low and valid at any time.

[0112] JPROGRAM:

[0113] The JTAG instruction, this signal is equivalent to the PROGRAM_B signal, but is only valid in specific modes.

[0114] ISC_PROGRAM_KEY_RESET:

[0115] When the key management module clears the status when jumping from the full mode to the non-secure mode or in the non-secure mode state, this signal is valid and will be high for three consecutive beats. After entering the non-secure mode, configuration and readback are performed again

[0116] Instantiation:

[0117] Instantiation in Verilog is to instantiate a defined module into another module, thus achieving modular design and reuse of circuits. Through instantiation, we can decompose a complex circuit into multiple simple modules, improving the readability and maintainability of the code while reducing code redundancy.

[0118] Glitch:

[0119] Glitches are caused by race and hazard:

[0120] Race: In combinational circuits, when signals reach a meeting point through different paths at different times, this phenomenon is called race.

[0121] Hazard: The phenomenon that the circuit output has an instantaneous error due to race is called hazard. It is manifested as a narrow pulse that does not exist in the original design at the output terminal, often called a glitch.

[0122] The technical effects of the above technical solutions are as follows: The USER function allows the generation of a USER reset request according to the encryption / decryption mode when a user-instantiated startup primitive is detected in user mode. This design increases the flexibility of the system, enabling users to manually or automatically trigger reset operations when needed to adapt to different application requirements or handle abnormal situations. The FALLBACK function can generate a FALLBACK reset request when errors such as ID_ERR (identifier error), CRC_ERR (cyclic redundancy check error), or WTO_ERR (wait timeout error) are detected in configuration mode. This enhances the error recovery ability of the system, ensuring that when errors are encountered during the configuration process, the system can automatically recover to a safe or default state, avoiding potential running errors or system crashes.

[0123] The PROGRAM function resets all registers according to the preset demand information through the PROGRAM_B, JPROGRAM, and ISC_PROGRAM_KEY_RESET components. This provides a powerful means to manage and control the reset operation during the configuration process, ensuring that the system can operate in the expected configuration state. Especially when a forced reset is needed to correct configuration errors or update the configuration, this function is particularly important. The PROGRAMSCUB function reloads the bitstream through self-refresh and resets all registers according to the preset demand information. This design enables the system to automatically recover or reload configuration data when necessary, thus ensuring the stability and reliability of the system. Self-refresh can be used to detect errors found during the readback process and reload the bitstream.

[0124] The entire configuration reset module integrates multiple reset functions and mechanisms, forming a comprehensive reset management system. This not only improves the reliability and stability of the system but also enables the system to more flexibly handle various abnormal situations and configuration requirements. By reasonably configuring and using these reset functions, the performance and user experience of the system can be significantly improved. The above-mentioned configuration reset module provides flexible user-mode reset, powerful error recovery capabilities, effective forced reset and configuration management, as well as convenient bitstream reloading and register reset functions, providing strong support for the stable operation and configuration management of the system.

[0125] In one embodiment of the present invention, the reset request circuit includes a glitch removal module and a pulse-width expansion module;

[0126] The glitch removal module is used to perform glitch processing on the initial reset signal after the reset initial signal arrives at the reset request module;

[0127] The pulse-width expansion module is used to expand a single clock cycle signal: the signal is pipelined in its clock domain, and the pipelined signal and the signal before pipelining are operated on to obtain the corresponding expanded signal.

[0128] The electrical signal output terminal of the glitch removal module is connected to the electrical signal input terminal of the pulse-width expansion module;

[0129] The glitch removal module includes a high-level active glitch processing circuit and a low-level active glitch processing circuit.

[0130] The working principle of the above technical solution is as follows: Glitch processing is performed on the signal, and then a single clock cycle signal is expanded: the signal is pipelined in its clock domain, and the pipelined signal and the signal before pipelining are OR-operated to obtain the corresponding expanded signal. After expansion, two-pipeline synchronization processing is performed on the signal in the corresponding clock domain. The signal after processing is the qualified reset request signal.

[0131] After the reset initial signal arrives at the reset request module, glitch processing is first performed on the initial reset signal. Glitch processing is as Figure 2-5 shown. Generally, the glitches are less than one cycle.

[0132] If the glitch is high-level active, the filtering method is to pipeline the signal generating the glitch twice using the target clock, and AND the signal after the second pipelining and the signal after the first pipelining. It can be seen that the glitch disappears. If the glitch is low-level, the signal after the second pipelining and the signal after the first pipelining should be ORed. The specific timing is as Figure 2 shown;

[0133] Among them, CP represents the clock terminal of the flip-flop, RST_N represents the reset terminal of the flip-flop, D is the input signal of the flip-flop, that is, the glitch signal to be filtered. Q output by the first-stage flip-flop is the signal after the first beat, and Q output by the second-stage flip-flop is the signal after the second beat.

[0134] The technical effects of the above technical solution are as follows: The USER reset request function in the user mode allows users to flexibly trigger the reset operation in the encryption and decryption modes according to actual needs or abnormal situations, thereby improving the adaptability and response speed of the system. The FALLBACK reset mechanism can quickly generate a reset request when an error is detected during the configuration process, enabling the system to automatically return to a safe or default state, effectively shortening the error recovery time, and improving the stability and reliability of the system. The PROGRAM function resets all registers through preset demand information, achieving precise control and management of the configuration process. This can ensure that the system operates in the expected configuration state and avoid system anomalies caused by configuration errors. The PROGRAMSCUB function reloads the bitstream by self-refreshing the trigger and resets all registers according to the preset demand information, achieving automatic recovery and update of the system configuration. This can keep the system in the latest state and improve the availability and performance of the system. The entire configuration reset module integrates multiple reset functions and mechanisms, forming a comprehensive reset management system. This allows the system to more flexibly respond to various abnormal situations and configuration requirements, improving the overall performance and user experience of the system.

[0135] In an embodiment of the present invention, the reset selection circuit includes an active control module and an inactive control module;

[0136] The reset source is divided into a user mode and a configuration mode;

[0137] The active control module is used to send a PREQ signal to the user through the STARTUP primitive in the user mode when an error occurs when pack_active is active, and determine whether to send a response to the reset system through the STARTUP primitive;

[0138] The inactive control module is used to generate a reset request by default in the configuration mode when pack_active is inactive.

[0139] The working principle of the above technical solution is as follows: It is mainly divided into two directions, namely the validity of pack_active. According to the validity of this signal, the reset sources are divided into user mode and configuration mode. In user mode, once an error occurs, the reset system sends a PREQ signal to the user through the STARTUP primitive. After receiving this signal, the user realizes that a reset request has been generated and decides whether to send a response to the reset system through the STARTUP primitive. If the signal is invalid, it is defaulted that the reset request is generated in the configuration mode, and the reset requests in the configuration mode are divided into three paths. The reset selection circuit, such as Figure 6 shown

[0140] The technical effects of the above technical solution are as follows: By dividing the reset sources into user mode and configuration mode, the reset selection circuit can provide refined reset control according to different operation scenarios and error types. This can reduce unnecessary reset operations and improve the stability and efficiency of the system. In user mode, when pack_active is valid and an error occurs, the valid control module sends a PREQ signal to the user through the STARTUP primitive and determines whether to send a response to the reset system. This design enables the user to promptly understand the error situation and take appropriate countermeasures as needed, thus enhancing the interactivity and user-friendliness of the system. When pack_active is invalid, the invalid control module defaults to generating a reset request in the configuration mode. This ensures that when an error or abnormality occurs during the configuration process of the system, the reset operation can be automatically triggered to restore to a safe or default state. This design improves the self-recovery ability and fault tolerance of the system. Through the collaborative work of the valid and invalid control modules, the reset selection circuit can ensure that when the system encounters an error or abnormality, the reset operation can be triggered quickly and accurately. This can reduce system crashes or data losses caused by errors or abnormalities and improve the reliability and stability of the system. Through refined reset control and a flexible reset selection mechanism, the reset selection circuit can reduce unnecessary reset operations and reduce the overhead and delay caused by system resets. This can optimize the overall performance of the system and improve the response speed and operation efficiency of the system.

[0141] In an embodiment of the present invention, the reset selection circuit further includes a reset control unit;

[0142] The reset control unit is used to receive reset request signals from different reset sources;

[0143] The reset control unit includes a triple modular redundancy circuit;

[0144] The triple modular redundancy circuit is used to receive each reset signal through the triple modular redundant clock terminals, and the outputs of the three path flip-flops are ANDed. Only when all three path flip-flops are valid, the final output will be valid, and then error correction is performed.

[0145] The working principle of the above technical solution is as follows: To ensure the correct execution of the reset operation, the present invention also designs a dedicated reset control unit of the present invention. This unit is responsible for receiving request signals from different reset sources. No matter which of the above reset signals is generated first, a corresponding request signal will be generated. In this way, it is not necessary to consider the sequence of generation of these reset signals, ensuring that only one reset operation is executed at any time.

[0146] The main part of this reset control unit is a triple modular redundancy circuit. Each reset signal (generally, a reset is a period of pos signal) will be sent to the clock terminal of the triple modular redundancy, which is equivalent to edge detection. After the outputs of the three flip-flops are ANDed, this ensures that only when all three flip-flops are valid, the final output will be valid, enabling error correction and improving system reliability.

[0147] After the output of the triple modular redundancy circuit, a selection is made through a mux according to the validity of pack_active to select the reset in the configuration or user mode. The triple modular redundancy circuit is as Figure 7 shown.

[0148] The technical effects of the above technical solution are as follows: The triple modular redundancy circuit receives each reset signal through three independent clock terminals, and after being output by three-way flip-flops, an AND operation is performed. Only when all three-way flip-flops are valid, the final output will be valid. This design greatly improves the reliability of the reset signal. Because even if one or two of the reset signals are interfered with or malfunction, as long as there is one valid reset signal, the system can still perform the reset operation correctly. The triple modular redundancy technology is a widely used fault-tolerant technology, which can effectively cope with soft faults such as single event upsets (SEUs). Introducing the triple modular redundancy circuit into the reset selection circuit can significantly enhance the fault-tolerant ability of the system, enabling the system to maintain a stable operating state when facing various abnormal situations. By performing error correction processing on the reset signal through the triple modular redundancy circuit, the accuracy and stability of the reset process can be ensured. This can reduce system anomalies or crashes caused by incorrect reset signals and improve the overall performance and stability of the system. The design of the reset selection circuit and its reset control unit, especially the introduction of the triple modular redundancy circuit, enables the system to make correct and reliable responses when facing various reset requests. This can enhance the overall reliability of the system and ensure that the system can operate stably in various complex environments. Although the triple modular redundancy circuit increases the complexity of the system, in the long run, it simplifies other aspects of the system design. By introducing the triple modular redundancy technology, the dependence on a single reset source can be reduced, thereby reducing the complexity and risk of system design. At the same time, this also provides more convenience and flexibility for system maintenance and upgrade. The triple modular redundancy circuit design in the reset selection circuit and its reset control unit brings significant technical effects, including improving the reliability of the reset signal, enhancing the fault-tolerant ability of the system, optimizing the reset process, enhancing the reliability of the system, and simplifying the system design, etc. These technical effects act together on the system, enabling the system to make correct and reliable responses when facing various abnormal situations and reset requests, thus ensuring the stable operation of the system.

[0149] In an embodiment of the present invention, the reset synchronization processing circuit includes an asynchronous reset module and a synchronization processing module;

[0150] The asynchronous reset module is used to control the reset signal not to be affected by the clock signal and perform a reset at a low level, that is, the reset signal does not need to be synchronized with the clock;

[0151] The synchronization processing module is used to synchronize the target signal RST_N with the clock CP when the reset is invalid.

[0152] The working principle of the above technical solution is as follows: The reset signal after passing through the reset selection circuit, since it is an asynchronous reset signal, needs to be synchronized to ensure the consistency and stability of the signal among various modules inside the FPGA. The reset synchronization processing circuit converts the asynchronous reset signal into a synchronous reset signal through a specific synchronization mechanism, thus avoiding potential problems caused by clock domain crossing. It can effectively prevent signal distortion and data corruption caused by clock domain asynchronization. This process usually involves using flip-flops and clock signals to ensure the stability and reliability of the reset signal. After synchronization processing, the reset signal will be transmitted to the reset release circuit, which is responsible for releasing the reset signal at an appropriate time point, enabling the FPGA to safely transition from the reset state to the normal working state.

[0153] The adopted method is the synchronous processing of asynchronous reset

[0154] Asynchronous reset: That is, the reset signal can be directly unaffected by the clock signal and can be reset as long as it is at a low level at any moment, that is, the reset signal does not need to be synchronized with the clock.

[0155] Synchronous processing: When the reset is invalid, the target signal RST_N can be synchronized with the clock CP to achieve synchronization, avoiding the metastability problem easily caused by asynchronous reset. The asynchronous reset synchronous processing circuit is as Figure 8 shown. Among them, CP represents the clock signal of the flip-flop, RST_N represents the reset signal of the flip-flop and is also the target signal to be processed, D represents the input signal of the flip-flop, which is fixedly connected to a high level, and the signal output after passing through two-level flip-flops is the reset signal synchronized with the clock. VCC represents the power supply voltage.

[0156] The technical effects of the above technical solution are as follows: The asynchronous reset module allows the reset signal to perform a reset when it is at a low level and does not require synchronization with the clock signal. This design improves the flexibility of the reset signal, enabling the system to respond to a reset request at any point in time without waiting for the rising or falling edge of the clock signal. Asynchronous reset can quickly restore the system to its initial state, especially when the system encounters a serious error or anomaly. This ability to immediately reset can prevent the propagation of error states, thereby enhancing the stability of the system. By separating the reset signal from the clock signal, the asynchronous reset module avoids potential conflicts between the reset signal and the clock signal. This can reduce system instability or abnormal behavior caused by signal synchronization problems. When the reset is invalid, the synchronization processing module synchronizes the target signal RST_N with the clock CP. This ensures that the system signals after reset can be synchronized with the clock signal, thus avoiding timing problems caused by signal asynchrony. The design of the reset synchronization processing circuit optimizes the system performance. Asynchronous reset ensures that the system can quickly respond to a reset request, while synchronization processing ensures that the system signals after reset can be correctly and stably synchronized with the clock signal. This design can reduce the delay and overhead caused by system reset and improve the overall performance of the system. The reset synchronization processing circuit combines the asynchronous control and synchronization processing of the reset signal, simplifying the complexity of the system design. This design enables system designers to focus more on the functional implementation and performance optimization of the system without paying too much attention to the processing and synchronization of the reset signal. The reset synchronization processing circuit, through the collaborative work of the asynchronous reset module and the synchronization processing module, improves the flexibility of the reset signal, enhances the system stability, avoids conflicts between the reset signal and the clock signal, ensures the synchronization of the signals after reset, optimizes the system performance, and simplifies the system design. These technical effects act together on the system, enabling the system to make a quick, accurate, and reliable response when facing a reset request.

[0157] In one embodiment of the present invention, the reset release module includes a clock cycle monitoring module, a delay cycle monitoring module, and a high-level output module;

[0158] The clock cycle monitoring module is used to monitor a specific clock cycle, and the specific clock cycle indicates that each module inside the FPGA has completed initialization and is ready;

[0159] The delay cycle monitoring module is used to obtain an additional delay cycle, and the additional delay cycle ensures that all possible initialization operations have been completed;

[0160] The high-level output module is used to output a high-level signal indicating the end of the reset state when the specific clock cycle and the additional delay cycle are obtained; the high-level signal, through the logic gate circuit inside the FPGA, converts the entire system from the reset state to the normal working state.

[0161] The working principle of the above technical solution is as follows: After receiving the reset signal after synchronous processing, the reset release circuit determines the optimal timing to release the reset signal according to the timing logic inside the FPGA. First, the circuit monitors a specific clock cycle, which indicates that all modules inside the FPGA have completed initialization and are ready. Then, the reset release circuit waits for an additional delay cycle to ensure that all possible initialization operations have been completed. Once these conditions are met, the reset release circuit outputs a high-level signal indicating the end of the reset state. This high-level signal passes through the logic gate circuit inside the FPGA, ultimately causing the entire system to transition from the reset state to the normal operating state. During the transition process, the reset release circuit continuously monitors the system status to ensure a smooth and error-free transition.

[0162] After the moment when the reset signal arrives at the reset release circuit, counting is performed. When the count reaches 25 cycles, a reset clear signal is generated, which resets the registers of the triple modular redundancy to ensure that the reset only lasts for a certain period of time, and then initialization is performed and the bitstream is reloaded to ensure that the chip does not remain in the reset state all the time.

[0163] The technical effects of the above technical solution are as follows: The clock cycle monitoring module can accurately monitor the specific clock cycles when each module inside the FPGA completes initialization and is ready. This ensures that the system has gone through the necessary initialization stage before the reset release. The delay cycle monitoring module further ensures that all possible initialization operations have been completed by obtaining additional delay cycles. This design can eliminate the system instability factors caused by incomplete initialization and improve the overall stability of the system. After obtaining the specific clock cycle and additional delay cycles, the high-level output module will output a clear high-level signal indicating the end of the reset state. This signal can reliably switch the entire system from the reset state to the normal working state through the logic gate circuit inside the FPGA, avoiding the confusion and conflict between the reset state and the normal working state. The design of the reset release module optimizes the system startup process. By precisely controlling the release timing of the reset state, the system can enter the normal working state faster, reducing the delay and overhead during the startup process. The design of the reset release module enables the system to more accurately determine the end timing of the reset state, thereby improving the reliability of the system. At the same time, this design also makes it easier to troubleshoot and repair faults during system maintenance, reducing the maintenance cost. Through the collaborative work of the clock cycle monitoring module and the delay cycle monitoring module, the reset release module can support complex initialization requirements. This enables the system to perform sufficient initialization in the face of different hardware and software environments to ensure the normal operation of the system. Through the collaborative work of the clock cycle monitoring module, the delay cycle monitoring module, and the high-level output module, the reset release module ensures the integrity of system initialization, enhances system stability, provides a clear indication of the end of the reset state, optimizes the system startup process, improves system reliability and maintainability, and supports complex initialization requirements. These technical effects act on the system together, enabling the system to operate more stably and reliably.

[0164] In an embodiment of the present invention, the general reset method includes:

[0165] Classify the reset signals generated during the FPGA configuration process through the reset request circuit, and perform preset signal processing according to the preset functional scenarios and priorities. The signal processing includes filtering out glitches, broadening, and synchronization;

[0166] Select among multiple reset requests through the reset selection circuit and respond to the reset requests in the predetermined priority order;

[0167] Synchronously process the reset signals from the reset request circuit through the reset synchronization processing circuit to control the transmission of signals between clock domains;

[0168] After the reset operation is completed through the reset release circuit, convert the FPGA from the reset state to the normal working state.

[0169] The working principle of the above technical solution is as follows: It is applicable to the FPGA configuration reset requirements in multiple scenarios and can effectively solve the metastability problem during the transmission of reset signals. The stability of FPGA configuration reset is directly related to whether the chip can be normally configured and successfully started. The present invention aims to provide a stable and reliable general reset circuit solution.

[0170] The reset system adopts synchronous design technology to ensure stable operation at various working frequencies. It includes a reset request circuit, a reset selection circuit, a reset synchronization processing circuit, and a reset release circuit.

[0171] The reset request module can automatically detect the reset state during power-on or reset, and process it to ensure the reliability of the reset process, generating a unified request signal to be transmitted to the lower-level module; the reset selection module classifies and selects the reset request signal through two major scenarios of user and configuration, while the synchronization module ensures the synchronous transmission of the reset signal among various modules, avoiding the metastability problem caused by signal asynchronization; the reset release module performs a zeroing operation on the generated reset to ensure that the chip will not remain in the reset state continuously and can be restored to the normal configuration.

[0172] In addition, the system also has a user processing reset operation, which can ensure that in the user mode, if a reset occurs, the user has the right to choose whether to reset. Through these designs, the reset system of the present invention can greatly improve the success rate of FPGA configuration and the stability of the system.

[0173] The technical effects of the above technical solution are as follows: By classifying the reset signals generated during the FPGA configuration process through the reset request circuit and performing preset signal processing (such as debouncing, widening, and synchronization) according to preset functional scenarios and priorities, the accuracy and reliability of the reset signals can be ensured. This refined processing can reduce system instability or failures caused by abnormal reset signals. The reset selection circuit can select among multiple reset requests and respond to the reset requests in a predetermined priority order. This design enables the system to efficiently process multiple reset sources and ensures that in case of errors or abnormalities, it can quickly respond and recover the system according to the priority order. The reset synchronization processing circuit can synchronously process the reset signals from the reset request circuit and control the signal transmission between clock domains. This can ensure the synchronization of reset signals between different clock domains and avoid timing problems or system abnormalities caused by asynchronous signals. The reset release circuit can convert the FPGA from the reset state to the normal operating state after the reset operation is completed. This design ensures the stability and reliability of the system after reset and avoids system problems caused by incomplete reset or abnormal reset state transition. Overall, through refined reset signal processing, efficient reset request response, ensuring synchronous signal transmission, and reliable reset state transition, the reset management system significantly improves the overall system performance and reliability during the FPGA configuration process. This enables the system to maintain a stable operating state in the face of various complex environments and abnormal situations and quickly respond and recover. The introduction of this reset management system also simplifies the complexity of system design and maintenance. Through modular design, system designers can more conveniently design the system architecture and signal processing, while reducing the cost and difficulty of system maintenance.

[0174] In an embodiment of the present invention, the configuration reset method of the reset request circuit includes:

[0175] Perform USER reset in user mode. When detecting the user instantiation of the startup primitive, generate a USER reset request in the encryption and decryption mode;

[0176] Perform FALLBACK reset in configuration mode. When detecting errors such as ID_ERR, CRC_ERR, or WTO_ERR, generate a FALLBACK reset request;

[0177] Perform a forced reset operation during the configuration process through PROGRAM reset, which consists of PROGRAM_B and ISC_PROGRAM_KEY_RESET, and reset all registers;

[0178] Trigger PROGRAMSCUB reset through self-refresh, reload the bitstream, and reset all registers;

[0179] Debounce the USER, FALLBACK, PROGRAM, and PROGRAMSCUB signals, and then widen the single clock cycle signal:

[0180] Latch the corresponding signal in its clock domain, perform an operation on the latched signal and the signal before latching to obtain the corresponding widened signal;

[0181] After widening, perform two - cycle synchronization processing on the signal in the corresponding clock domain. The signal after processing is the qualified reset request signal.

[0182] The working principle of the above - mentioned technical solution is as follows: USER reset occurs in user mode. When detecting that the user instantiates the startup primitive and in the encryption / decryption mode, a USER reset request is generated. In this scenario, subsequently, in the reset selection circuit part, a request can be sent to the user. The user can agree to the reset or determine that it is a false trigger and thus intercept the reset for remedy, realizing the reset interception function.

[0183] FALLBACK reset is in the configuration mode. When detecting errors such as ID_ERR, CRC_ERR, or WTO_ERR, a FALLBACK reset request is generated. Subsequently, after passing through the reset synchronization processing circuit, other modules are commanded to perform a fallback operation and trigger a reset for initialization and re - configuration. Also, when in the main bpi or main spi mode (two of the loading modes of the FPGA), when detecting a multiboot operation, the FPGA sends an uper address to the flash (flash memory) for updating the bitstream. At the same time, the FPGA parses the iprog instruction from the bitstream, triggers a reset initialization, and then reloads the updated bitstream of the flash for re - configuration.

[0184] PROGRAM reset involves a forced reset operation during the configuration process and is composed of PROGRAM_B (a fixed pin of the FPGA for forced reset initialization), JPROGRAM (one of the related JTAG instructions, with the same meaning as PROGRAM_B), and ISC_PROGRAM_KEY_RESET (the reset generated by the storage key module in non - secure mode). It can reset all registers and has the highest priority.

[0185] PROGRAMSCUB reset (this reset means that during the read - back process, when detecting an error greater than 2 bits, suspecting that the fpga configuration bits are problematic, and then reloading the flash to refresh the fpga configuration bits) is triggered by self - refresh. The bitstream will be re - loaded, and it can also reset all registers and has the highest priority.

[0186] (The FALLBACK reset can only reset the configuration registers except those related to multiboot. However, registers related to multiboot such as the timer register, BSPI register, and WBSTAR register cannot be reset by FALLBACK; the MULTIBOOT reset can reset all registers.)

[0187] The technical effects of the above technical solutions are as follows: The system supports multiple reset modes such as USER, FALLBACK, PROGRAM, and PROGRAMSCUB, and appropriate reset methods can be selected according to different error or requirement scenarios. This design enhances the reset flexibility of the system, enabling the system to more accurately handle various abnormal situations. In the USER reset mode, a reset request is generated by detecting the user-instantiated startup primitive, ensuring the pertinence of the reset operation. In the FALLBACK reset mode, the reset is triggered by detecting errors such as ID_ERR, CRC_ERR, or WTO_ERR, improving the accuracy and timeliness of the reset request. The PROGRAM reset mode resets all registers through a forced reset operation to ensure the correctness and stability of the system configuration. The PROGRAMSCUB reset mode further enhances the reliability of the system configuration through self-refresh triggering and bitstream reloading. Debouncing the reset signals such as USER, FALLBACK, PROGRAM, and PROGRAMSCUB can effectively eliminate false triggers caused by signal jitter or interference. At the same time, stretching the single clock cycle signal can ensure the stability and reliability of the reset signal within the clock domain. After stretching, performing two-beat synchronization processing on the signal in the corresponding clock domain can ensure the synchronization of the reset request signal between different clock domains. This design avoids timing problems or system anomalies caused by signal asynchronization and improves the overall stability of the system. Through modular design, separating steps such as the generation, processing, and synchronization of the reset request enables system designers to more conveniently design the system architecture and signal processing. At the same time, this design also reduces the cost and difficulty of system maintenance and improves the maintainability of the system. Through technical effects such as enhancing reset flexibility, improving the accuracy of the reset request, ensuring the stability of the system configuration, optimizing reset signal processing, achieving cross-clock domain signal synchronization, and simplifying system design and maintenance, the overall performance and reliability of the system are significantly improved. This enables the system to maintain a stable operating state in the face of various complex environments and abnormal situations and respond and recover quickly.)

[0188] In an embodiment of the present invention, the debouncing of the USER, FALLBACK, PROGRAM, and PROGRAMSCUB signals includes:

[0189] When the glitch is active high, the signal generating the glitch is double-registered by the target clock, and the signal after the second registration is ANDed with the signal after the first registration to obtain glitch removal information;

[0190] When the glitch is active low, the signal after the second registration is ORed with the signal after the first registration.

[0191] The working principle of the above technical solution is as follows: Since the four reset signals have different generation logics, generated clocks, and generation conditions, the widths and validities of the signals are different. It is necessary to uniformly process these signals, perform glitch processing on the signals, and then widen the single clock cycle signal: The signal is registered in its clock domain, and the registered signal is ORed with the signal before registration to obtain the corresponding widened signal. After widening, the signal is synchronously processed for two registrations in the corresponding clock domain. The signal after processing is the qualified reset request signal.

[0192] After the reset initial signal arrives at the reset request module, the initial reset signal is first subjected to glitch processing. Glitch processing is as Figure 2-5 shown. Generally speaking, glitches are less than one cycle.

[0193] If the glitch is active high, the filtering method is to double-register the signal generating the glitch using the target clock, and AND the signal after the second registration with the signal after the first registration. It can be seen that the glitch disappears. If the glitch is active low, the signal after the second registration should be ORed with the signal after the first registration. The specific timing is as Figure 2 shown;

[0194] Among them, CP represents the clock terminal of the flip-flop, RST_N represents the reset terminal of the flip-flop, D is the input signal of the flip-flop, that is, the glitch signal to be filtered. Q output by the first-stage flip-flop is the signal after the first registration, and Q output by the second-stage flip-flop is the signal after the second registration.

[0195] The technical effects of the above technical solution are as follows: By double-registering the signal generating glitches with the target clock, the stability and synchronization of the signal within the clock domain can be ensured. This processing can eliminate the short abnormal states caused by signal jitter or interference and improve the reliability of the signal. For the glitches with high-level validity, the signal after the second register is compared with the signal after the first register through an AND operation. Only when both signals are at high level, the output result is at high level. This can effectively remove the short high-level glitches and ensure the accuracy of the signal. For the low-level glitches, the short low-level abnormal states can also be removed through an OR operation. When one of the two signals is at low level, the output result is at low level. However, considering the actual processing, the removal of low-level glitches is usually not achieved through a simple OR operation (because the OR operation will retain any low level). By judging the signal states after double-registering, if the signal after the second register returns to the normal high level (assuming the normal state is high level), it can be considered that the low-level glitches have been "ignored" or "filtered", because what the system ultimately focuses on is the stable high-level state. The glitch processing realizes the effective removal of glitches through simple double-registering and logical operations (AND or OR), without the need for complex filtering circuits or algorithms, reducing the complexity and cost of system design. By removing the glitches in the signal, the system malfunctions or faults caused by signal anomalies can be reduced, improving the robustness and stability of the system. This is particularly important for application scenarios that require high reliability. The stable signal input enables the system to execute instructions and data processing more accurately, thereby improving the overall performance of the system. The introduction of glitch processing can ensure that the system can still maintain a stable operating state in the face of various signal interferences.

[0196] Obviously, those skilled in the art can make various changes and deformations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and deformations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and deformations.

Claims

1. A universal reset system for FPGA chip configuration circuit, characterized in that: The system includes a reset request circuit, a reset selection circuit, a reset synchronization processing circuit and a reset release circuit; The reset request circuit is used to classify the reset signal generated during the FPGA configuration process and perform corresponding signal processing according to the preset functional scenario and priority; the signal processing includes filtering burrs, widening and synchronization; The reset selection circuit is used to select among multiple reset requests, and the control system responds to the reset requests in a preset priority order; The reset synchronization processing circuit is used to synchronously process and transmit the reset signal from the reset request circuit; The reset release circuit is used to safely guide the FPGA from a reset state to a normal working state after the reset operation is completed.

2. A universal reset system for FPGA chip configuration circuit according to claim 1, characterized in that: The reset request circuit is connected to a configuration reset module; The configuration reset module includes USER, FALLBACK, PROGRAM and PROGRAMSCUB; The USER is used to generate a USER reset request in the user mode when a user instantiates the startup primitive and in the encryption and decryption mode; The FALLBACK is used to generate a FALLBACK reset request when an error such as ID_ERR, CRC_ERR or WTO_ERR is detected in the configuration mode; The PROGRAM is used to perform a forced reset operation during the configuration process, and is composed of PROGRAM_B, JPROGRAM and ISC_PROGRAM_KEY_RESET, and resets all registers according to preset demand information; PROGRAMSCUB is used to reload the bit stream through self-refresh trigger and reset all registers according to preset requirement information.

3. A universal reset system for FPGA chip configuration circuit according to claim 2, characterized in that: The reset request circuit includes a burr removal module and a widening module; The burr removal module is used to perform burr processing on the initial reset signal after the reset initial signal reaches the reset request module; The stretching module is used to stretch a single clock cycle signal: the signal is beat in its clock domain, and the signal after the beat is calculated with the signal before the beat to obtain a corresponding stretched signal.

4. A universal reset system for FPGA chip configuration circuit according to claim 1, characterized in that: The reset selection circuit includes a valid control module and an invalid control module; Divide the reset source into user mode and configuration mode; The effective control module is used to send a PREQ signal to the user through the STARTUP primitive when pack_active is effective and in the user mode when an error occurs, and determine whether to send a response to the reset system through the STARTUP primitive; The invalid control module is used to generate a reset request in the configuration mode by default when pack_active is invalid.

5. A universal reset system for FPGA chip configuration circuit according to claim 4, characterized in that: The reset selection circuit also includes a reset control unit; The reset control unit is used to receive reset request signals from different reset sources; The reset control unit includes a triple-module redundant circuit; The triple-module redundant circuit is used to receive various reset signals through the triple-module redundant clock end, and perform AND after the three-way trigger output. Only when all three-way triggers are valid, the final output will be valid, and then error correction is performed.

6. A universal reset system for FPGA chip configuration circuit according to claim 1, characterized in that: The reset synchronization processing circuit comprises an asynchronous reset module and a synchronization processing module; The asynchronous reset module is used to control the reset signal to be unaffected by the clock signal and to perform reset at a low level; The synchronization processing module is used to synchronize the target signal RST_N with the clock CP when the reset is invalid.

7. A universal reset system for FPGA chip configuration circuit according to claim 1, characterized in that: The reset release module includes a clock cycle monitoring module, a delay cycle monitoring module and a high level output module; The clock cycle monitoring module is used to monitor a specific clock cycle; The delay period monitoring module is used to obtain an additional delay period; The high-level output module is used to output a high-level signal to indicate the end of the reset state after obtaining a specific clock cycle and an additional delay cycle; the high-level signal passes through the logic gate circuit inside the FPGA to convert the entire system from the reset state to the normal working state.

8. A universal reset method for a universal reset system applied to an FPGA chip configuration circuit, characterized in that: The general reset method comprises: The reset signal generated during the FPGA configuration process is classified by the reset request circuit, and the preset signal processing is performed according to the preset functional scenario and priority, and the signal processing includes filtering burrs, widening and synchronization; Selecting from a plurality of reset requests through a reset selection circuit, and responding to the reset requests in a predetermined priority order; The reset signal from the reset request circuit is synchronously processed by the reset synchronization processing circuit, and the control signal is transmitted between the clock domains; After the reset operation is completed, the reset release circuit converts the FPGA from the reset state to the normal working state.

9. A universal reset method for a universal reset system applied to an FPGA chip configuration circuit according to claim 8, characterized in that: The configuration reset method of the reset request circuit includes: Perform USER reset in user mode. When a user instantiates the startup primitive, a USER reset request is generated in encryption and decryption mode. Perform FALLBACK reset in configuration mode. When an ID_ERR, CRC_ERR, or WTO_ERR error is detected, a FALLBACK reset request is generated. Perform a forced reset operation during the configuration process through PROGRAM reset, which consists of PROGRAM_B and ISC_PROGRAM_KEY_RESET to reset all registers; Trigger PROGRAMSCUB reset through self-refresh, reload the bitstream, and reset all registers; Glitch the USER, FALLBACK, PROGRAM, and PROGRAMSCUB signals, and then stretch the single clock cycle signal: Beat the corresponding signal in its clock domain, and perform calculation on the signal after beating and the signal before beating to obtain the corresponding stretched signal; After widening, the signal is subjected to two-beat synchronization processing in the corresponding clock domain, and the processed signal is a qualified reset request signal.

10. The universal reset method of a universal reset system applied to a FPGA chip configuration circuit according to claim 9, characterized in that: The glitch processing of USER, FALLBACK, PROGRAM and PROGRAMSCUB signals includes: When the glitch is high level effective, the signal generating the glitch is tapped twice by the target clock, and the signal after the second tap is ANDed with the signal after the first tap to obtain the glitch removal information; When the glitch is low, the signal after the second tap is ORed with the signal after the first tap.

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