A two-phase interleaved parallel BUCK drive circuit

Abstract

The present application discloses a two-phase staggered parallel BUCK driving circuit, including: a pulse signal generating circuit for outputting a pulse signal that meets a set frequency, the output end of the pulse signal generating circuit is connected to the input end of the pulse staggered circuit; the input end of the pulse staggered circuit is used to receive the pulse signal generated by the pulse signal generating circuit; the pulse staggered circuit is used to phase-shift and stagger the base frequency signal of the received pulse signal by 180° and then output two pulse signals with a phase difference of 180°; the output end of the pulse staggered circuit is respectively connected to the input end of the first driving circuit and the second driving circuit, and the output end of the first driving circuit and the second driving circuit is connected to the power MOS tube. Through the present application, the requirements for heat dissipation measures can be lowered, and discrete devices can be used at the same time, which is convenient for debugging and maintenance.

Description

Technical Field

[0001] The present application relates to the technical field of BUCK topology application design, and in particular to a two-phase staggered parallel BUCK driving circuit. Background Art

[0002] With the development and progress of science and technology, the speed of electronic product updates and iterations is getting faster and faster. Not only have the product performance and functions become richer and more powerful, but the appearance has also gradually developed in the direction of miniaturization and lightness. The charging method of its energy storage battery has gradually been upgraded to fast charging. Fast charging has put forward higher requirements on the performance of various charging power sources, such as low voltage, high current and smaller ripple, and at the same time requires small size, light weight and high efficiency.

[0003] As a classic topology for low-voltage, high-current power conversion, the BUCK topology is often used to design charging circuits with various functions. With the miniaturization of electronic equipment, sometimes there is a small installation space or light weight requirements, and the BUCK topology is often needed to be staggered in parallel, which can make the inductor and capacitor smaller and reduce the output ripple. Two-phase staggered parallel BUCK drive often uses a dedicated BUCK topology staggered parallel drive chip. The traditional BUCK topology staggered parallel drive chip has high functional integration and high requirements for printed circuit copper wiring, which can easily interfere with chip control and have an adverse effect on electrical performance control. Because traditional chips have many integrated functions, higher requirements are also placed on heat dissipation measures. In addition, during the debugging process, it is often impossible to accurately locate the cause of failure due to abnormalities in certain chip functions, and the chip needs to be replaced, which is not convenient for debugging and maintenance. Utility Model Content

[0004] Based on this, in order to solve the above technical problems, a two-phase staggered parallel BUCK drive circuit is provided to solve the problems that the multifunctional integrated chip is easily affected by the interference of copper wiring, which has an adverse effect on the electrical performance control, has high requirements for heat dissipation measures, and is inconvenient for debugging and maintenance.

[0005] A two-phase staggered parallel BUCK driving circuit, the circuit comprising: a pulse signal generating circuit, a pulse staggered circuit and a first driving circuit and a second driving circuit;

[0006] The pulse signal generating circuit is used to output a pulse signal that meets the set frequency, and the output end of the pulse signal generating circuit is connected to the input end of the pulse interleaving circuit; the input end of the pulse interleaving circuit is used to receive the pulse signal generated by the pulse signal generating circuit; the pulse interleaving circuit is used to phase-shift and interleave the baseband signal of the received pulse signal by 180° and then output two pulse signals with a phase difference of 180°;

[0007] The output end of the pulse interleaving circuit is connected to the input end of the first driving circuit and the input end of the second driving circuit respectively, and the output end of the first driving circuit and the output end of the second driving circuit are connected to the power MOS tube.

[0008] In the above scheme, optionally, the pulse signal generating circuit includes: a 555 timer U1, resistors R1, R2 and R3, capacitors C1, C2, C3;

[0009] Pin 1 of the 555 timer U1 is grounded, pin 4 is connected to the power supply VCC, and pin 5 is connected to capacitor C1 and then grounded; pin 2 of the 555 timer U1 is connected to pin 6, pin 6 of the 555 timer U1 is connected to pin 7 through resistor R1, pin 7 of the 555 timer U1 is connected to pin 8 through resistor R2, and pin 8 of the 555 timer U1 is connected to the power supply VCC; pin 8 of the 555 timer U1 is connected to pin 1 through capacitor C2; pin 1 of the 555 timer U1 is connected to pin 2 through capacitor C3; pin 3 of the 555 timer U1 is connected to one end of resistor R3.

[0010] In the above scheme, further optionally, the pulse interleaving circuit includes: a dual-channel high-speed low-side gate driver U2, a resistor R4, a resistor R5 and a capacitor C4;

[0011] Pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2 are connected, and the other end of the resistor R3 is connected to the connecting line between pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2; pin 3 of the dual-channel high-speed low-side gate driver U2 is grounded; pin 7 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R5; pin 5 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R4; pin 6 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the capacitor C4, and a first node is set on the connecting line between pin 6 of the dual-channel high-speed low-side gate driver U2 and one end of the capacitor C4, and a first branch is led out from the first node, and the first branch is grounded; pin 1 and pin 8 of the dual-channel high-speed low-side gate driver U2 are suspended and vacant.

[0012] In the above solution, further optionally, the first driving circuit includes: a fixed frequency current mode controller U3, resistors R6, R7, R8, R9, R10, R11, capacitors C5, C6, C7, a diode D1, and a transistor Q1;

[0013] The other end of the resistor R5, the capacitor C5, the diode D1 and the base of the transistor Q1 are connected in sequence; the collector of the transistor Q1 is connected to the pin 8 of the fixed frequency current mode controller U3; a second node is set on the connection line between the capacitor C5 and the diode D1, a second branch is drawn from the second node and connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the capacitor C4; the other end of the resistor R6 is grounded; a third node is set on the connection line between the diode D1 and the base of the transistor Q1, a third branch is drawn from the third node and connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6; the emitter of the transistor Q1 is connected to one end of the resistor R9; the other end of the resistor R9 and the other end of the resistor R7 are connected through the resistor R 8; a fourth node is set on the connection line between the collector of the transistor Q1 and the pin 8 of the fixed frequency current mode controller U3, and a fourth branch is drawn from the fourth node to sequentially connect the resistor R10 and one end of the capacitor C7; the other end of the capacitor C7 is connected to the resistor R9 through the capacitor C6; the other end of the capacitor C7 is also connected to the pin 5 of the fixed frequency current mode controller U3 through the resistor R11, and the pin 5 of the fixed frequency current mode controller U3 is connected to the ground; the pin 4 of the fixed frequency current mode controller U3 is connected to the connection line between the resistor R10 and one end of the capacitor C7; the pin 7 of the fixed frequency current mode controller U3 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U3 is connected to the power MOS tube;

[0014] The second driving circuit includes: a fixed frequency current mode controller U4, resistors R12, R13, R14, R15, R16, R17, capacitors C8, C9, C10, a diode D2, and a transistor Q2;

[0015] The other end of the resistor R4, the capacitor C8, the diode D2 and the base of the transistor Q2 are connected in sequence; the collector of the transistor Q2 is connected to the pin 8 of the fixed frequency current mode controller U4; a fifth node is set on the connection line between the capacitor C8 and the diode D2, and a fifth branch is drawn from the fifth node and connected to one end of the resistor R12, and the other end of the resistor R12 is grounded; a sixth node is set on the connection line between the diode D2 and the base of the transistor Q2, and a sixth branch is drawn from the sixth node and connected to one end of the resistor R13, and the other end of the resistor R13 is connected to the other end of the resistor R12; the emitter of the transistor Q2 is connected to one end of the resistor R15; the other end of the resistor R15 is connected to the other end of the resistor R13 through the resistor R14; A seventh node is set on the connection line between the collector of the diode Q2 and the pin 8 of the fixed frequency current mode controller U4, and a seventh branch is drawn from the seventh node to sequentially connect the resistor R16 and one end of the capacitor C10; the other end of the capacitor C10 is connected to the resistor R15 through the capacitor C9; the other end of the capacitor C10 is also connected to the pin 5 of the fixed frequency current mode controller U4 through the resistor R117, and the pin 5 of the fixed frequency current mode controller U4 is grounded; the pin 4 of the fixed frequency current mode controller U4 is connected to the connection line between the resistor R16 and one end of the capacitor C10, and the pin 7 of the fixed frequency current mode controller U4 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U4 is connected to the power MOS tube.

[0016] In the above scheme, further optionally, the set frequency of the pulse signal output by the pulse signal generating circuit is obtained by the following formula:

[0017]

[0018] Wherein, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and C3 is the capacitance value of the capacitor C3.

[0019] This application has at least the following beneficial effects:

[0020] The present application outputs a pulse signal that meets the set frequency through a pulse signal generating circuit, a pulse interleaving circuit is used to phase-shift and interleave the pulse signal by 180° before outputting it, and a driving circuit is used to synchronize the driving output waveform with the pulse signal and then drive the subsequent switch MOS tube. Therefore, the functional integration of the present application is low, the requirements for heat dissipation measures are lower, and discrete devices are used, which is convenient for debugging and maintenance, and can accurately realize electrical performance control. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A principle circuit diagram of a two-phase staggered parallel BUCK drive circuit is provided for one embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In one embodiment, Figure 1 As shown, a two-phase staggered parallel BUCK driving circuit is provided, the circuit comprising: a pulse signal generating circuit, a pulse staggered circuit and a first driving circuit and a second driving circuit;

[0024] The pulse signal generating circuit is used to output a pulse signal that meets the set frequency, and the output end of the pulse signal generating circuit is connected to the input end of the pulse interleaving circuit; the input end of the pulse interleaving circuit is used to receive the pulse signal generated by the pulse signal generating circuit; the pulse interleaving circuit is used to phase-shift and interleave the baseband signal of the received pulse signal by 180° and then output two pulse signals with a phase difference of 180°;

[0025] The output end of the pulse interleaving circuit is connected to the input end of the first driving circuit and the input end of the second driving circuit respectively, and the output end of the first driving circuit and the output end of the second driving circuit are connected to the power MOS tube.

[0026] Specifically, the pulse signal generating circuit is used to generate a pulse signal, which is used to set a base frequency signal of a fixed frequency. By setting parameters, a pulse signal that meets the set frequency can be output. The pulse interleaving circuit is used to phase-shift and interleave the pulse signal by 180° before outputting it. The driving circuit is used to synchronize the frequency of the driving output waveform with the pulse signal and then drive the subsequent switch MOS tube.

[0027] In the above-mentioned two-phase staggered parallel BUCK driving circuit, a pulse signal that meets the set frequency is outputted through a pulse signal generating circuit, and a pulse staggering circuit is used to output the pulse signal after phase shifting and staggering it by 180°, and a driving circuit is used to synchronize the driving output waveform with the pulse signal and then drive the subsequent switch MOS tube. Therefore, the functional integration of the present application is low, and the requirements for heat dissipation measures are lower. At the same time, discrete devices are used, which is convenient for debugging and maintenance, and can accurately realize electrical performance control.

[0028] In one embodiment, the pulse signal generating circuit includes: a 555 timer U1, resistors R1, R2 and R3, capacitors C1, C2 and C3;

[0029] Pin 1 of the 555 timer U1 is grounded, pin 4 is connected to the power supply VCC, and pin 5 is connected to capacitor C1 and then grounded; pin 2 of the 555 timer U1 is connected to pin 6, pin 6 of the 555 timer U1 is connected to pin 7 through resistor R1, pin 7 of the 555 timer U1 is connected to pin 8 through resistor R2, and pin 8 of the 555 timer U1 is connected to the power supply VCC; pin 8 of the 555 timer U1 is connected to pin 1 through capacitor C2; pin 1 of the 555 timer U1 is connected to pin 2 through capacitor C3; pin 3 of the 555 timer U1 is connected to one end of resistor R3.

[0030] In one embodiment, the pulse interleaving circuit includes: a dual-channel high-speed low-side gate driver U2, a resistor R4, a resistor R5 and a capacitor C4;

[0031] Pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2 are connected, and the other end of the resistor R3 is connected to the connecting line between pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2; pin 3 of the dual-channel high-speed low-side gate driver U2 is grounded; pin 7 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R5; pin 5 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R4; pin 6 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the capacitor C4, and a first node is set on the connecting line between pin 6 of the dual-channel high-speed low-side gate driver U2 and one end of the capacitor C4, and a first branch is led out from the first node, and the first branch is grounded; pin 1 and pin 8 of the dual-channel high-speed low-side gate driver U2 are suspended and vacant.

[0032] Specifically, in actual implementation, U2 uses a dual-channel high-speed low-side gate driver, and its output channels are divided into reverse output channel A and same-direction output channel B. Reverse output channel A outputs the input signal after reverse interleaving 180°, and same-direction output channel B outputs the input signal in phase, thereby obtaining a set of pulse signals with a phase shift and interleaving of 180°.

[0033] In one embodiment, the first driving circuit includes: a fixed frequency current mode controller U3, resistors R6, R7, R8, R9, R10, R11, capacitors C5, C6, C7, a diode D1, and a transistor Q1;

[0034] The other end of the resistor R5, the capacitor C5, the diode D1 and the base of the transistor Q1 are connected in sequence; the collector of the transistor Q1 is connected to the pin 8 of the fixed frequency current mode controller U3; a second node is set on the connection line between the capacitor C5 and the diode D1, a second branch is drawn from the second node and connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the capacitor C4; the other end of the resistor R6 is grounded; a third node is set on the connection line between the diode D1 and the base of the transistor Q1, a third branch is drawn from the third node and connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6; the emitter of the transistor Q1 is connected to one end of the resistor R9; the other end of the resistor R9 and the other end of the resistor R7 are connected through the resistor R 8; a fourth node is set on the connection line between the collector of the transistor Q1 and the pin 8 of the fixed frequency current mode controller U3, and a fourth branch is drawn from the fourth node to sequentially connect the resistor R10 and one end of the capacitor C7; the other end of the capacitor C7 is connected to the resistor R9 through the capacitor C6; the other end of the capacitor C7 is also connected to the pin 5 of the fixed frequency current mode controller U3 through the resistor R11, and the pin 5 of the fixed frequency current mode controller U3 is connected to the ground; the pin 4 of the fixed frequency current mode controller U3 is connected to the connection line between the resistor R10 and one end of the capacitor C7; the pin 7 of the fixed frequency current mode controller U3 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U3 is connected to the power MOS tube;

[0035] The second driving circuit includes: a fixed frequency current mode controller U4, resistors R12, R13, R14, R15, R16, R17, capacitors C8, C9, C10, a diode D2, and a transistor Q2;

[0036] The other end of the resistor R4, the capacitor C8, the diode D2 and the base of the transistor Q2 are connected in sequence; the collector of the transistor Q2 is connected to the pin 8 of the fixed frequency current mode controller U4; a fifth node is set on the connection line between the capacitor C8 and the diode D2, and a fifth branch is drawn from the fifth node and connected to one end of the resistor R12, and the other end of the resistor R12 is grounded; a sixth node is set on the connection line between the diode D2 and the base of the transistor Q2, and a sixth branch is drawn from the sixth node and connected to one end of the resistor R13, and the other end of the resistor R13 is connected to the other end of the resistor R12; the emitter of the transistor Q2 is connected to one end of the resistor R15; the other end of the resistor R15 is connected to the other end of the resistor R13 through the resistor R14; A seventh node is set on the connection line between the collector of the diode Q2 and the pin 8 of the fixed frequency current mode controller U4, and a seventh branch is drawn from the seventh node to sequentially connect the resistor R16 and one end of the capacitor C10; the other end of the capacitor C10 is connected to the resistor R15 through the capacitor C9; the other end of the capacitor C10 is also connected to the pin 5 of the fixed frequency current mode controller U4 through the resistor R117, and the pin 5 of the fixed frequency current mode controller U4 is grounded; the pin 4 of the fixed frequency current mode controller U4 is connected to the connection line between the resistor R16 and one end of the capacitor C10, and the pin 7 of the fixed frequency current mode controller U4 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U4 is connected to the power MOS tube.

[0037] Specifically, the first driving circuit and the second driving circuit have the same parameter settings for the two driving circuit units, and U3 and U4 are commonly used fixed-frequency current mode controllers, and their peripheral parameter settings are typical peripheral circuit parameter settings.

[0038] In actual implementation, the first drive circuit is used as an example for explanation. U3 in the first drive unit is a fixed frequency current mode controller, and its operating frequency can be set through resistors R10, C7, and R11. In normal operation, the REF1 voltage charges C7 through R10 and R11. When the charging voltage of the C7 capacitor reaches the internal reference threshold voltage, the C7 capacitor begins to discharge, thereby generating a driving pulse with a fixed frequency and a fixed duty cycle. When the synchronization pulse of U2 channel A is transmitted to the pin 4 input of U3 through C5, D1, Q1, R9 and C6, the superposition of the pulse amplitude will quickly charge C7, changing the charging time of capacitor C7, so that the frequency of the output drive is finally consistent with the frequency of the pulse signal, and the requirement of synchronous frequency drive output is achieved.

[0039] The pulse signal is used to set the base frequency signal of the fixed frequency parameter; the pulse interleaving circuit is used to phase-shift and interleave the base frequency signal of the received pulse signal by 180° and then output it as two pulse signals with a phase difference of 180°; the driving circuit synchronizes the frequency with the pulse signal and then outputs it, and its output end is connected to the power MOS tube to drive the corresponding MOS tube to work according to the synchronized pulse frequency.

[0040] In one embodiment, the set frequency of the pulse signal output by the pulse signal generating circuit is obtained by the following formula:

[0041]

[0042] Wherein, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and C3 is the capacitance value of the capacitor C3.

[0043] Specifically, in actual implementation, the 555 timer cooperates with peripheral parameters to set the frequency and duty cycle of the output baseband pulse signal. The frequency of this signal is the synchronization frequency of the subsequent drive signal. The frequency parameters can be adjusted by adjusting the resistance values ​​of resistors R1 and R2 and the capacitance value of C3.

[0044] In an exemplary embodiment of the present utility model, the present utility model embodiment includes at least the following advantages:

[0045] 1. The circuit design is simple and the layout takes up little space;

[0046] 2. The electronic components are universal models with low cost;

[0047] 3. Use discrete devices to facilitate debugging and maintenance;

[0048] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A two-phase staggered parallel BUCK drive circuit, characterized in that: The circuit comprises: a pulse signal generating circuit, a pulse interleaving circuit, a first driving circuit and a second driving circuit; The pulse signal generating circuit is used to output a pulse signal that meets the set frequency, and the output end of the pulse signal generating circuit is connected to the input end of the pulse interleaving circuit; the input end of the pulse interleaving circuit is used to receive the pulse signal generated by the pulse signal generating circuit; the pulse interleaving circuit is used to phase-shift and interleave the baseband signal of the received pulse signal by 180° and then output two pulse signals with a phase difference of 180°; The output end of the pulse interleaving circuit is connected to the input end of the first driving circuit and the input end of the second driving circuit respectively, and the output end of the first driving circuit and the output end of the second driving circuit are connected to the power MOS tube.

2. The two-phase staggered parallel BUCK driving circuit according to claim 1, characterized in that: The pulse signal generating circuit includes: a 555 timer U1, resistors R1, R2 and R3, capacitors C1, C2 and C3; Pin 1 of the 555 timer U1 is grounded, pin 4 is connected to the power supply VCC, and pin 5 is connected to capacitor C1 and then grounded; pin 2 of the 555 timer U1 is connected to pin 6, pin 6 of the 555 timer U1 is connected to pin 7 through resistor R1, pin 7 of the 555 timer U1 is connected to pin 8 through resistor R2, and pin 8 of the 555 timer U1 is connected to the power supply VCC; pin 8 of the 555 timer U1 is connected to pin 1 through capacitor C2; pin 1 of the 555 timer U1 is connected to pin 2 through capacitor C3; pin 3 of the 555 timer U1 is connected to one end of resistor R3.

3. The two-phase staggered parallel BUCK driving circuit according to claim 2, characterized in that: The pulse interleaving circuit includes: a dual-channel high-speed low-side gate driver U2, a resistor R4, a resistor R5 and a capacitor C4; Pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2 are connected, and the other end of the resistor R3 is connected to the connecting line between pin 2 and pin 4 of the dual-channel high-speed low-side gate driver U2; pin 3 of the dual-channel high-speed low-side gate driver U2 is grounded; pin 7 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R5; pin 5 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the resistor R4; pin 6 of the dual-channel high-speed low-side gate driver U2 is connected to one end of the capacitor C4, and a first node is set on the connecting line between pin 6 of the dual-channel high-speed low-side gate driver U2 and one end of the capacitor C4, and a first branch is led out from the first node, and the first branch is grounded; pin 1 and pin 8 of the dual-channel high-speed low-side gate driver U2 are suspended and vacant.

4. The two-phase staggered parallel BUCK driving circuit according to claim 3, characterized in that: The first driving circuit includes: a fixed frequency current mode controller U3, resistors R6, R7, R8, R9, R10, R11, capacitors C5, C6, C7, a diode D1, and a transistor Q1; The other end of the resistor R5, the capacitor C5, the diode D1 and the base of the transistor Q1 are connected in sequence; the collector of the transistor Q1 is connected to the pin 8 of the fixed frequency current mode controller U3; a second node is set on the connection line between the capacitor C5 and the diode D1, a second branch is drawn from the second node and connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the other end of the capacitor C4; the other end of the resistor R6 is grounded; a third node is set on the connection line between the diode D1 and the base of the transistor Q1, a third branch is drawn from the third node and connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the other end of the resistor R6; the emitter of the transistor Q1 is connected to one end of the resistor R9; the other end of the resistor R9 and the other end of the resistor R7 are connected through the resistor R 8; a fourth node is set on the connection line between the collector of the transistor Q1 and the pin 8 of the fixed frequency current mode controller U3, and a fourth branch is drawn from the fourth node to sequentially connect the resistor R10 and one end of the capacitor C7; the other end of the capacitor C7 is connected to the resistor R9 through the capacitor C6; the other end of the capacitor C7 is also connected to the pin 5 of the fixed frequency current mode controller U3 through the resistor R11, and the pin 5 of the fixed frequency current mode controller U3 is connected to the ground; the pin 4 of the fixed frequency current mode controller U3 is connected to the connection line between the resistor R10 and one end of the capacitor C7; the pin 7 of the fixed frequency current mode controller U3 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U3 is connected to the power MOS tube; The second driving circuit includes: a fixed frequency current mode controller U4, resistors R12, R13, R14, R15, R16, R17, capacitors C8, C9, C10, a diode D2, and a transistor Q2; The other end of the resistor R4, the capacitor C8, the diode D2 and the base of the transistor Q2 are connected in sequence; the collector of the transistor Q2 is connected to the pin 8 of the fixed frequency current mode controller U4; a fifth node is set on the connection line between the capacitor C8 and the diode D2, and a fifth branch is drawn from the fifth node and connected to one end of the resistor R12, and the other end of the resistor R12 is grounded; a sixth node is set on the connection line between the diode D2 and the base of the transistor Q2, and a sixth branch is drawn from the sixth node and connected to one end of the resistor R13, and the other end of the resistor R13 is connected to the other end of the resistor R12; the emitter of the transistor Q2 is connected to one end of the resistor R15; the other end of the resistor R15 is connected to the other end of the resistor R13 through the resistor R14; A seventh node is set on the connection line between the collector of the diode Q2 and the pin 8 of the fixed frequency current mode controller U4, and a seventh branch is drawn from the seventh node to sequentially connect the resistor R16 and one end of the capacitor C10; the other end of the capacitor C10 is connected to the resistor R15 through the capacitor C9; the other end of the capacitor C10 is also connected to the pin 5 of the fixed frequency current mode controller U4 through the resistor R117, and the pin 5 of the fixed frequency current mode controller U4 is grounded; the pin 4 of the fixed frequency current mode controller U4 is connected to the connection line between the resistor R16 and one end of the capacitor C10, and the pin 7 of the fixed frequency current mode controller U4 is connected to the power supply VCC; the pin 6 of the fixed frequency current mode controller U4 is connected to the power MOS tube.

5. The two-phase staggered parallel BUCK driving circuit according to claim 2, characterized in that: The set frequency of the pulse signal output by the pulse signal generating circuit is obtained by the following formula: Wherein, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and C3 is the capacitance value of the capacitor C3.

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