Pixel structure

Abstract

The utility model provides a pixel structure, the pixel structure comprises a transistor, the transistor comprises a first metal layer, a second metal layer, a control line, a data line, an insulation layer and a first protection layer, a first via hole and a second via hole are arranged between the first metal layer and the second metal layer, the control line extends to the first metal layer from a gate driver, and the data line extends to the second metal layer from the gate driver. The first metal layer is electrically connected with the second metal layer through the first via hole and is electrically isolated from the first metal layer; the data line extends from the source driver to the second metal layer, is electrically connected with the first metal layer through the second via hole, and is electrically isolated from the second metal layer. Based on the scheme, the load of the data line can be reduced, and the crosstalk phenomenon can be effectively avoided even under the condition that the pixel charging rate is maximized.

Description

Technical Field

[0001] The present application relates to the field of liquid crystal display technology, and more specifically, to a pixel structure. Background Art

[0002] In order to meet the user's demand for ultra-long standby time of products including screens, it is usually necessary to reduce backlight power consumption and improve pixel transmittance. In the pixel design of the screen, the design of the common electrode of the pixel structure has a great influence on the pixel transmittance. The smaller the spacing between the common electrodes of adjacent sub-pixels, the greater the pixel transmittance of the pixel structure.

[0003] However, while reducing the spacing between the common electrodes of adjacent sub-pixels, the area facing the common electrode and the data line will increase, thereby increasing the load on the data line and increasing the capacitance effect inside the transistor applied to the pixel structure. This may cause the voltage on the pixel electrode to be affected by the data line, thereby generating crosstalk and affecting the picture quality. Utility Model Content

[0004] The present application provides a pixel structure that is beneficial to reducing the load on the data line and weakening the capacitance effect inside the transistor used in the pixel structure. Even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided.

[0005] In a first aspect, a pixel structure is provided, which includes: a transistor, which includes: a first metal layer, a second metal layer, a control line, a data line, an insulating layer, and a first protective layer, wherein the insulating layer covers the first metal layer; the second metal layer is located on the insulating layer; the first protective layer is located on the second metal layer; a first via is provided between the first metal layer and the second metal layer, the first end of the first via is located in the first metal layer, and the second end of the first via is located in the second metal layer, the control line extends from the gate driver to the first metal layer, and is electrically connected to the second metal layer through the first via, and is electrically isolated from the first metal layer, the control line is used to transmit the gate control signal issued by the gate driver to the second metal layer; a second via is also provided between the first metal layer and the second metal layer, the first end of the second via is located in the second metal layer, and the second end of the second via is located in the first metal layer, the data line extends from the source driver to the second metal layer, and is electrically connected to the first metal layer through the second via, and is electrically isolated from the second metal layer, the data line is used to transmit the image data signal issued by the source driver to the first metal layer.

[0006] In combination with the first aspect, in certain implementations of the first aspect, the pixel structure also includes: a common electrode and a pixel electrode, wherein the common electrode and the pixel electrode are isolated by a first protective layer, the pixel electrode is electrically connected to the second metal layer, the pixel electrode is used to receive an image data signal, the common electrode is used to form a variable electric field with the pixel electrode, and the variable electric field is used for imaging.

[0007] In combination with the first aspect, in certain implementations of the first aspect, the second metal layer includes a first part and a second part, the control line is electrically isolated from the first metal layer through a first via and connected to the first part of the second metal layer, and the data line is electrically isolated from the second part of the second metal layer through a second via and connected to the first metal layer.

[0008] Based on the above technical solution, in the transistor applied to the pixel structure, the first metal layer with a lower structure level of the transistor is connected to the data line, so that the first metal layer is used to realize the source and drain functions, and the second metal layer with a higher structure level of the transistor is connected to the control line, so that the second metal layer is used to realize the gate function, and the first metal layer and the common electrode are separated by at least a first protective layer and an insulating layer. Compared with the pixel structure prepared by the existing process, it is equivalent to increasing the distance between the source and drain and the common electrode, thereby reducing the capacitance between the first metal layer and the common electrode, which is beneficial to reducing the load of the data line, and even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided.

[0009] In a second aspect, a pixel structure is provided, which includes: a transistor, which includes: a first metal layer, a second metal layer, a control line, a data line, an insulating layer, and a first protective layer, wherein the insulating layer covers the first metal layer; the data line extends from the source driver to the first metal layer and is connected to the first metal layer, and the data line is used to transmit the image data signal emitted by the source driver to the first metal layer; the second metal layer is located on the insulating layer; the control line extends from the gate driver to the second metal layer and is connected to the second metal layer, and the control line is used to transmit the gate control signal emitted by the gate driver to the second metal layer; the first protective layer covers the second metal layer.

[0010] In combination with the second aspect, in certain implementations of the second aspect, the above-mentioned pixel structure also includes: a common electrode and a pixel electrode, wherein the common electrode and the pixel electrode are isolated by a first protective layer and an insulating layer, the pixel electrode is electrically connected to the first metal layer, the pixel electrode is used to receive an image data signal, the common electrode is used to form a variable electric field with the pixel electrode, and the variable electric field is used for imaging.

[0011] In combination with the second aspect, in certain implementations of the second aspect, the above-mentioned transistor also includes: an active layer, which is covered by an insulating layer, the active layer covers at least a portion of the above-mentioned first metal layer, and the active layer overlaps with the projection of the channel of the transistor in the first direction; and a shielding layer, which is arranged at the channel, and is used to shield the photogenerated carriers generated in the channel.

[0012] In combination with the second aspect, in some implementations of the second aspect, the transistor further includes: a second protective layer, the second protective layer covers the shielding layer, and the second protective layer is located under the first metal layer.

[0013] Based on the above technical solution, the existing pixel structure is adjusted, the first metal layer is directly connected to the data line, so that the first metal layer is used to realize the source and drain function, and the second metal layer is directly connected to the control line, so that the second metal layer is used to realize the gate function. Compared with the structure in which there is only one protective layer between the source and drain and the common electrode in the existing pixel structure, the pixel structure proposed in this solution has at least a first protective layer and an insulating layer between the first metal layer and the common electrode, thereby increasing the distance between the source and drain and the common electrode, reducing the capacitance between the first metal layer and the common electrode, and helping to reduce the load of the data line. Even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided. In addition, the pixel structure proposed in this solution does not need to transfer the control line originally connected to the first metal layer to the second metal layer through a via, nor does it need to transfer the data line originally connected to the second metal layer to the first metal layer through a via, so the preparation difficulty and cost of the pixel structure proposed in this solution are lower, and it also helps to improve the pixel transmittance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of the structural relationship of a pixel structure 200 prepared based on the existing process;

[0015] Figure 2 is a cross-sectional view of a pixel structure 200 prepared based on an existing process;

[0016] Figure 3 (a) is a schematic diagram of the connection between the functional unit components of a gate driver;

[0017] Figure 3 (b) is a schematic diagram of the connection between functional unit components of another gate driver;

[0018] Figure 4 is a schematic diagram of the structural relationship of a pixel structure 400 proposed in an embodiment of the present application;

[0019] Figure 5 is a cross-sectional view of a pixel structure 400 proposed in an embodiment of the present application;

[0020] Figure 6 is a schematic diagram of the structural relationship of a pixel structure 600 proposed in an embodiment of the present application;

[0021] Figure 7 is a cross-sectional view of another pixel structure 600 proposed in an embodiment of the present application;

[0022] Figure 8 is a cross-sectional view of another pixel structure 600 proposed in an embodiment of the present application;

[0023] Fig. 9 is a cross-sectional view of another pixel structure 600 proposed in an embodiment of the present application;

[0024] Fig.10 It is a flowchart of key steps of a method 1000 for preparing a pixel structure proposed in an embodiment of the present application;

[0025] Fig.11 It is a flow chart of another method 1100 for preparing a pixel structure proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0027] It should be noted that, in the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in this article is merely a way to describe the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0028] In the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In addition, in the description of the embodiments of the present application, "multiple" refers to two or more than two, "at least one" and "one or more" refer to one, two or more. The singular expressions "one", "a kind", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context.

[0029] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0030] In the description of the embodiments of the present application, the terms "upper", "lower", "left", "right", "inside", "outside", "vertical", "horizontal", etc. indicate orientations or positional relationships that are defined relative to the orientations or positions of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for description and clarification relative to the drawings, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. It may change accordingly according to the change in the orientation of the components placed in the drawings, and therefore cannot be understood as a limitation on the present application. In addition, the "vertical" involved in the present application is not vertical in the strict sense, but is within the allowable error range. "Parallel" is not parallel in the strict sense, but is within the allowable error range.

[0031] In the embodiments of the present application, the same reference numerals are used to represent the same components or parts. For the same parts in the embodiments of the present application, only one of the parts or parts may be marked with a reference numeral in the figure. It should be understood that the reference numerals are also applicable to other identical parts or parts. In addition, the various parts in the drawings are not drawn to scale, and the sizes and dimensions of the parts shown in the drawings are only exemplary and should not be understood as limiting the present application.

[0032] As an important carrier for user interaction, the screen can be applied to products in various fields and is the main power-consuming device in the product. In order to improve the user experience of the product and enable the product to have a longer standby time, the optimization of the power consumption of the screen is an important breakthrough.

[0033] Generally, during the product design stage, the screen can be designed to have a higher pixel transmittance structure, thereby reducing the backlight power consumption of the screen. In the pixel design of the screen, the design of the common electrode of the pixel electrode has a great influence on the pixel transmittance. The smaller the spacing between the common electrodes of adjacent pixels, the greater the pixel transmittance of the pixel structure.

[0034] It should be noted that the "screen" mentioned in the embodiments of the present application refers to a device used to display images and colors, and may also be called a screen, screen, screen, display screen, display, etc. The embodiments of the present application do not limit this.

[0035] Figure 1 It is a schematic diagram of the structural relationship of a pixel structure 100 prepared based on the existing process.

[0036] Figure 2 It is a cross-sectional view of a pixel structure 100 prepared based on the existing process.

[0037] It should be understood that the above Figure 2 The pixel structure 100 shown is based on Figure 1 Prepared by the existing process shown.

[0038] It should be noted that Figure 1 The upper and lower relationship of each layer is only the order of deposition during preparation. The dielectric layer deposited later is deposited on the basis of all the dielectric layers deposited earlier, but it does not mean that the dielectric layer deposited later will completely cover all the dielectric layers deposited earlier. The dielectric layer deposited later and the dielectric layer deposited earlier can also be located at the same layer in the hierarchical architecture of the entire pixel structure.

[0039] refer to Figure 1 As shown, the preparation steps of the pixel structure 100 are as follows:

[0040] S110 : depositing the pixel electrode 110 .

[0041] S120: depositing a gate 120, which may also be referred to as a G electrode for short. The G electrode and the pixel electrode are located at the same layer in the hierarchical architecture of the pixel structure.

[0042] S130: depositing a gate insulator (GI) layer 130. The GI layer covers the G electrode, thereby isolating the G electrode from other dielectric layers.

[0043] S140: depositing an active layer 140 on the GI layer.

[0044] S150: depositing a source electrode 151 and a drain electrode 152 on the active layer, wherein the source electrode 151 may also be referred to as an S electrode, and the drain electrode 152 may also be referred to as a D electrode. Structurally, the S electrode and the D electrode are used to receive different signals, but the S electrode and the D electrode are usually located at the same layer in the hierarchical architecture of the transistor in the pixel structure, so the S electrode and the D electrode may also be collectively referred to as SD electrode 150.

[0045] S160 : depositing a protection layer 160 , wherein a first portion 161 of the protection layer 160 covers a first portion of the SD electrode 150 , and a second portion 162 of the protection layer 160 is on the pixel electrode 110 .

[0046] S170 : depositing a common electrode 170 on the first protection layer 160 .

[0047] S180 : depositing a dielectric layer 175 on the second portion of the SD electrode 150 (that is, at least a portion of the D electrode) and at least a portion of the pixel electrode 110 . The dielectric layer 175 is used to transmit the signal of the SD electrode 150 to the pixel electrode 110 .

[0048] Typically, the material of the dielectric layer 175 is the same as that of the common electrode 170 , so that the dielectric layer 175 can be deposited while the common electrode 170 is deposited, that is, S170 and S180 can be completed in one process.

[0049] It should be understood that the above-mentioned pixel structure 100 may include a transistor part and a non-transistor part, wherein the transistor part includes the above-mentioned G electrode 120, GI layer 120, active layer 140, SD electrode 150, and protective layer 160, and the non-transistor part includes a dielectric layer 175, a common electrode 170 and a pixel electrode 110.

[0050] refer to Figure 2 As shown, the G electrode 120 is used to receive a gate control signal through a gate on array (GOA) and a control line derived from the gate driver. The SD electrode 150 is used to receive a data signal, which can also be transmitted to the SD electrode 150 through a corresponding circuit of the pixel structure 100. The SD electrode 150 and the common electrode 170 are separated by at least the above-mentioned first protective layer.

[0051] and Figure 2 The pixel structure 100 shown can be used to form a GOA unit functional component on an array, and the display module of the screen can include multiple interconnected GOA unit functional components. Each GOA unit functional component corresponds to a sub-pixel, and the implementation of the sub-pixel can adopt the above pixel structure 100.

[0052] Figure 3 (a) is a schematic diagram of the connections between the functional unit components of a gate driver.

[0053] refer to Figure 3(a), usually, there is a gap 301 between two adjacent sub-pixels, and the exposed portion of the gap is part of the SD electrode 150. However, in order to maximize the pixel transmittance, in the pixel design, the common electrodes 170 of adjacent sub-pixels can be connected to each other.

[0054] Figure 3 (b) is a schematic diagram of the connections between functional unit components of another gate driver.

[0055] refer to Figure 3 (b), although the pixel transmittance can be maximized by connecting the common electrodes 170 of two adjacent sub-pixels, this will cause the common electrode 170 to completely cover the data line 180 between the adjacent sub-pixels, thereby increasing the load of the data line 180 and reducing the pixel charging rate. In addition, the area directly facing the SD electrode 150 and the common electrode 170 reaches the maximum. According to the capacitance formula: C = εs / d, where C represents capacitance, ε represents dielectric constant, s represents the area directly facing the SD electrode 150 and the common electrode 170, and d represents the distance between the SD electrode 150 and the common electrode 170, it can be determined that when s reaches the maximum while d remains unchanged, the corresponding C also reaches the maximum, which may cause the voltage on the pixel electrode 110 to be affected by the data line, thereby generating crosstalk and affecting the picture quality.

[0056] At present, there are two main methods for improving the crosstalk phenomenon of pixel structures: one is to reduce the coverage area of ​​the common electrode and the data line, thereby reducing the coupling capacitance between the SD electrode 150 and the common electrode 170; the other is to increase the size of the pixel structure and reduce the impact of crosstalk by increasing the pixel charging rate. However, both methods will lead to a decrease in pixel transmittance.

[0057] In view of this, the embodiments of the present application propose a pixel structure that maximizes the pixel transmittance without increasing the difficulty of the pixel structure manufacturing process, while ensuring that the pixel charging rate is not affected by the maximization of the pixel transmittance.

[0058] Figure 4 It is a schematic diagram of the structural relationship of a pixel structure 400 proposed in an embodiment of the present application.

[0059] The pixel structure 400 includes: a transistor, which includes: a first metal layer 410, a second metal layer 420, a control line 430, a data line 440, an insulating layer 450, and a first protective layer 460, wherein the insulating layer 450 covers the first metal layer 410; the second metal layer 420 is located on the insulating layer 450; the first protective layer 460 is located on the second metal layer 420; a first via hole 481 is provided between the first metal layer 410 and the second metal layer 420, a first end 4811 of the first via hole 481 is located in the first metal layer 410, and a second end 4812 of the first via hole 481 is located in the second metal layer 420, and the control line 430 extends from the gate driver to the first metal layer 410 and passes through the first via hole 4811. 1 is electrically connected to the second metal layer 420 and electrically isolated from the first metal layer 410, and the control line 430 is used to transmit the gate control signal issued by the gate driver to the second metal layer 420; a second via hole 482 is also provided between the first metal layer 410 and the second metal layer 420, and the first end 4821 of the second via hole 482 is located in the second metal layer 420, and the second end 4822 of the second via hole 482 is located in the first metal layer 410, and the data line 440 extends from the source driver to the second metal layer 420, and is electrically connected to the first metal layer 410 through the second via hole 482, and is electrically isolated from the second metal layer 420, and the data line 440 is used to transmit the image data signal issued by the source driver to the first metal layer 410.

[0060] Figure 5 It is a cross-sectional view of a pixel structure 400 proposed in an embodiment of the present application.

[0061] exist Figure 5 In the figure, the graphic portion filled with black dots is the second metal layer 420 deployed in the horizontal direction inside the transistor of the pixel structure 400, the graphic portion filled with oblique lines is the first metal layer 410 deployed in the vertical direction inside the transistor of the pixel structure 400, the graphic portion filled with intersecting oblique lines is the pixel electrode 490 in the pixel structure 400, the graphic portion filled with vertical lines is the common electrode 470 in the pixel structure 400, and the rectangle filled with gray is used to represent vias, including the first via 481 and the second via 482. In addition, there is also a via between the pixel electrode 490 and the common electrode 470, and this via also exists in the existing pixel structure. The function of this via is different from the first via 481 or the second via 482. This via is used to realize the transmission of current or signal between the pixel electrode 490 and the second metal layer 420, that is, to realize the electrical connection between the pixel electrode 490 and the second metal layer 420.

[0062] It should be noted that in order to reflect Figure 5 The hierarchical relationship (or deposition order) between the various material layers in Figure 5The transparency of the images used to represent each material layer is also different. The higher the image transparency, the higher the level of the corresponding material layer (or the later the deposition order). Figure 5 Taking the second metal layer 420 and the first metal layer 410 as an example, the graphic representing the first metal layer 410 can be seen through the graphic representing the second metal layer 420 , so the second metal layer 420 is located above the first metal layer 410 .

[0063] In some possible embodiments, the first via 481 or the second via 482 is not directly connected from the first metal layer 410 to the second metal layer 420, and the first via 481 or the second via 482 may also pass through other material layers of the pixel structure 400. It is only necessary to ensure that the two ends of the first via 481 or the second via 482 are respectively located in the first metal layer 410 and the second metal layer 420. The embodiment of the present application does not limit the specific structure of the first via 481 or the second via 482.

[0064] In some possible embodiments, reference Figure 4 or Figure 5 It can be seen that the above-mentioned pixel structure 400 also includes: a common electrode 470 and a pixel electrode 490, wherein the common electrode 470 and the pixel electrode 490 can be isolated by a first protective layer 460, the pixel electrode 490 is electrically connected to the second metal layer 420, the pixel electrode 490 is used to receive image data signals, and the common electrode 470 is used to form a variable electric field with the pixel electrode 490, and the variable electric field is used for imaging.

[0065] In some possible embodiments, the pixel electrode 490 and the first metal layer 410 may be located at the same layer in the hierarchical structure of the pixel structure 400 , and the pixel electrode 490 and the first metal layer 410 are isolated from each other by the insulating layer 450 .

[0066] refer to Figure 4 It can be seen that the above-mentioned second metal layer 420 includes a first part 421 and a second part 422, the control line 430 is electrically isolated from the first metal layer 410 through the first via 481, and is connected to the first part 421 of the second metal layer 420, so that the first part 421 of the second metal layer 420 is used to constitute the gate (G electrode) of the transistor, and the data line 440 is electrically isolated from the second part 422 of the second metal layer 420 through the second via 482, and is connected to the first metal layer 410, so that the above-mentioned first metal layer 410 is used to constitute the source and drain (SD electrode) of the transistor.

[0067] It should be understood that based on the above-mentioned pixel structure 400, the gate control signal from the gate controller is received by the second metal layer 420 through the first via 481, and is used to adjust the voltage of the second metal layer 420. When the voltage of the second metal layer 420 is greater than a first threshold value (the size of the first threshold value is related to the material and process used to prepare the transistor), the transistor is turned on, so that the image data signal from the source controller is received by the first metal layer 410 through the second via 482, and is transmitted from the first metal layer 410 to the pixel electrode 490.

[0068] In addition, the pixel structure 400 further includes a dielectric layer 475 , which is located above the second portion of the second metal layer 420 and at least a portion of the pixel electrode 490 , and is used to transmit a signal received by the second portion of the second metal layer 420 to the pixel electrode 490 .

[0069] In some possible embodiments, the material of the first metal layer 410 may be metal, such as aluminum (Al), or may be polysilicon or other materials.

[0070] In some possible embodiments, the material of the second metal layer 420 may be silicon, semiconductor compounds, etc., such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC).

[0071] In some possible embodiments, the material of the insulating layer 450 may be silicon dioxide (SiO2), an insulating material with a high dielectric constant, an organic insulating material, or silicon nitride (SiNx), etc., which is not limited in the embodiments of the present application.

[0072] In some possible embodiments, the material of the first protective layer 460 may be a polyvinyl chloride-based material.

[0073] In some possible embodiments, the material of the common electrode 470 may be nano-indium tin oxide (ITO), so the common electrode 470 may also be referred to as common-ITO, COM-ITO or C-ITO, which is not limited in the embodiments of the present application.

[0074] In some possible embodiments, the material of the dielectric layer 475 may be the same as that of the common electrode 470 . Based on this, when depositing the common electrode 470 , the dielectric layer 475 may also be deposited, thereby simplifying the semiconductor manufacturing process.

[0075] In some possible embodiments, the material of the pixel electrode 490 may also be ITO, so the pixel electrode may also be referred to as pixel-ITO or P-ITO.

[0076] It should be noted that the reference Figure 4 As shown, the pixel structure 400 further includes an active layer 455, and the active layer 455 can be prepared using the existing process, and the position, shape and structure of the active layer 455 can be the same as the active layer in the pixel structure prepared based on the existing process.

[0077] Combining the above Figure 1 and Figure 4 From the perspective of the pixel structure in these two figures, the main difference is that Figure 4 The pixel structure 400 in FIG. 4 has a first via hole 481 and a second via hole 482. In essence, the introduction of the first via hole 481 and the second via hole 482 is to exchange the functions of the first metal layer 410 and the second metal layer 420.

[0078] In the pixel structure 100, at least the first protective layer 160 is between the SD electrode 150 and the common electrode 170. In the pixel structure 400, based on the special structural design of the pixel structure 400, the gate control signal is ultimately received by the second metal layer 420 through the control line 430 passing through the first via hole 481, so compared with the pixel structure 100, although the second metal layer 420 is located at the source and drain position of the transistor in the pixel structure 100, the function of the second metal layer 420 is substantially transformed into the gate function, and at this time, the second metal layer 420 is equivalent to the gate; similarly, the image data signal is ultimately received by the first metal layer 410 through the data line 440 passing through the second via hole 482, so compared with the pixel structure 100, although the first metal layer 410 is located at the gate position of the transistor in the pixel structure 100, the function of the first metal layer 410 is substantially transformed into the source and drain function, and at this time, the first metal layer 410 is equivalent to the source and drain.

[0079] Based on this, it can be known that there is at least a first protective layer 460 and an insulating layer 450 between the first metal layer 410 equivalent to the source and drain and the common electrode 470, and based on the above capacitance calculation formula, it can be known that the distance between the first metal layer 410 and the common electrode 470 in the pixel structure 400 is greater than the distance between the SD electrode 150 and the common electrode 170 in the pixel structure 100, so the capacitance between the first metal layer 410 and the common electrode 470 in the pixel structure 400 is smaller.

[0080] Based on the above technical solution, by introducing a first via 481 and a second via 482 inside the transistor applied to the pixel structure 400, the control line 430 originally connected to the first metal layer 410 is transferred to the second metal layer 420, and the data line 440 originally connected to the second metal layer 420 is transferred to the first metal layer 410, so that the functions of the first metal layer 410 and the second metal layer 420 are swapped, that is, the first metal layer 410 is used to realize the source and drain functions, and the second metal layer 420 is used to realize the gate function. Compared with the structure in which there is only one protective layer between the SD electrode and the common electrode in the existing pixel structure, the pixel structure proposed in this solution has at least a first protective layer 460 and an insulating layer 450 between the first metal layer 410 and the common electrode 470, thereby increasing the distance between the source and drain and the common electrode 470, reducing the capacitance between the first metal layer 410 and the common electrode 470, which is beneficial to reducing the load of the data line 440. Even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided.

[0081] Figure 6 It is a schematic diagram of the structural relationship of a pixel structure 600 proposed in an embodiment of the present application.

[0082] Similar to the pixel structure 400, the pixel structure 600 also includes: a transistor, which includes: a first metal layer 410, a second metal layer 420, a control line 430, a data line 440, an insulating layer 450, and a first protective layer 460, wherein the insulating layer 450 covers the first metal layer 410; the data line 440 extends from the source driver to the first metal layer 410 and is connected to the first metal layer 410, and the data line 440 is used to transmit the image data signal emitted by the source driver to the first metal layer 410; the second metal layer 420 is located on the insulating layer 450; the control line 430 extends from the gate driver to the second metal layer 420 and is connected to the second metal layer 420, and the control line 430 is used to transmit the gate control signal emitted by the gate driver to the second metal layer 420; the first protective layer 460 covers the second metal layer 420.

[0083] Figure 7 It is a cross-sectional view of a pixel structure 600 proposed in an embodiment of the present application.

[0084] and Figure 5 Similar, in Figure 7 In the figure, the graphic portion filled with black dots is the second metal layer 420 deployed horizontally inside the transistor of the pixel structure 600, the graphic portion filled with oblique lines is the first metal layer 410 deployed vertically inside the transistor of the pixel structure 600, the graphic portion filled with intersecting oblique lines is the pixel electrode 490 in the pixel structure 600, and the graphic portion filled with vertical lines is the common electrode 470 in the pixel structure 600.

[0085] It should be noted that in order to reflect Figure 7 The hierarchical relationship (or deposition order) between the various material layers in Figure 5 The transparency of the images used to represent each material layer is also different. The higher the image transparency, the higher the level of the corresponding material layer (or the later the deposition order). For example, the graphic used to represent the second metal layer 420 can pass through the graphic used to represent the first metal layer 410, and the first metal layer 410 is located under the second metal layer.

[0086] contrast Figure 5 It can be seen that: in the pixel structure 400, the control line 430 needs to be transferred to the second metal layer 420 through the first via 481, and the data line 440 needs to be transferred to the first metal layer 410 through the second via; while in the pixel structure 600, the control line 430 is directly connected to the second metal layer 420, and the data line 440 is directly connected to the first metal layer 410, so there is no need to set a first via 481 or a second via 482 between the first metal layer 410 and the second metal layer 420 for transferring the control line 430 or the data line 440.

[0087] Based on the above technical solution, the existing pixel structure is adjusted, the first metal layer 410 is directly connected to the data line 440, so that the first metal layer 410 is used to realize the source and drain functions, and the second metal layer 420 is directly connected to the control line 430, so that the second metal layer 420 is used to realize the gate function. Compared with the structure in which there is only one protective layer between the SD electrode and the common electrode in the existing pixel structure, the pixel structure 600 proposed in this solution has at least a first protective layer 460 and an insulating layer 450 between the first metal layer 410 and the common electrode 470, thereby increasing the distance between the source and drain and the common electrode 470, reducing the capacitance between the first metal layer 410 and the common electrode 470, which is beneficial to reducing the load of the data line 440, and can effectively avoid the occurrence of crosstalk even when the pixel charging rate is maximized. In addition, the pixel structure 600 proposed in this solution does not need to transfer the control line 430 originally connected to the first metal layer 420 to the second metal layer 420 through a via, nor does it need to transfer the data line 440 originally connected to the second metal layer 420 to the first metal layer 410 through a via. Therefore, the preparation difficulty and cost of the pixel structure 600 proposed in this solution are lower, and it also helps to improve the pixel transmittance.

[0088] In some possible embodiments, similar to the pixel structure 400, the pixel structure 600 also includes: a common electrode 470 and a pixel electrode 490, wherein the common electrode 470 and the pixel electrode 490 are isolated from each other by a first protective layer 460 and an insulating layer 450, the pixel electrode 490 is electrically connected to the first metal layer 410, the pixel electrode 490 is used to receive an image data signal, and the common electrode 470 is used to form a variable electric field with the pixel electrode 490, and the variable electric field is used for imaging.

[0089] refer to Figure 6 It can be seen that in the pixel structure 600, no vias are used, but the data line 440 is directly connected to the first metal layer 410, and the control line 430 is directly connected to the second metal layer 420, so the first metal layer 410 can be directly used to form the source and drain of the transistor in the pixel structure 600, and the second metal layer 420 can be directly used to form the gate of the transistor in the pixel structure 600.

[0090] Accordingly, the structure of the first metal layer 410 may be similar to the structure of the second metal layer 420 in the pixel structure 400 , and also includes two parts.

[0091] In some possible embodiments, since the pixel electrode 490 needs to receive an image data signal from the data line 440 , the pixel electrode 490 may be directly electrically connected to at least a portion of the first metal layer 410 .

[0092] Based on the structure of the existing pixel structure 100, it can be known that the image data signal can be transmitted to the SD electrode through the data line, but the SD electrode and the pixel electrode are not in direct contact, so the SD electrode and the pixel electrode need to be connected through a dielectric layer, and the data signal received by the SD electrode is transmitted to the pixel electrode through the dielectric layer. However, the data line 440 in the pixel structure 600 proposed in the embodiment of the present application is connected to the first metal layer 410, and at least part of the first metal layer 410 is also directly electrically connected to the pixel electrode 490, so there is no need to transfer the image data signal from the first metal layer 410 to the pixel electrode 490 through an additional dielectric layer.

[0093] Based on the above technical solution, since the data line 440 in the pixel structure 600 is directly connected to the first metal layer 410, and at least a portion of the first metal layer 410 is also directly electrically connected to the pixel electrode 490, and the image data signal is also required to be transmitted through a via between the SD electrode and the pixel electrode in the pixel structure 100, then based on the pixel structure 600, when the transistor is turned on, the image data signal can be directly transmitted to the pixel electrode 490 through the first metal layer 410. Not only does it not need to transfer the image data signal to the pixel electrode 490 through the dielectric layer, it is also not necessary to set a via for transmitting the image data signal on the pixel electrode 490. Therefore, the preparation difficulty and cost of the pixel structure 600 proposed in this solution can be further reduced.

[0094] refer to Figure 6 As shown, the pixel structure 600 further includes an active layer 455 , which is covered by the insulating layer 450 . The active layer 455 covers at least a portion of the first metal layer 410 , and the active layer 455 overlaps with a projection of the channel of the transistor in the first direction.

[0095] For example, the first direction is a vertical direction.

[0096] In some possible embodiments, the material of the active layer 455 is amorphous silicon (A-Si) or low temperature polysilicon (LTPS).

[0097] It should be understood that the mobility of A-Si material or LTPS material is more sensitive to light intensity. In the structure of the pixel structure 600, the projection of the active layer 455 and the channel in the first direction overlaps. When photogenerated carriers are generated in the channel of the pixel structure 600, the characteristics of the active layer 455 will be directly affected.

[0098] Figure 8 It is a cross-sectional view of another pixel structure 600 proposed in an embodiment of the present application.

[0099] refer to Figure 8 As shown, the transistor of the pixel structure 600 further includes a shielding layer 465 , which is disposed at the channel of the transistor and is used to shield the photogenerated carriers generated in the channel.

[0100] Fig. 9 It is a cross-sectional view of another pixel structure 600 proposed in an embodiment of the present application.

[0101] and Figure 7 Similar, in Fig. 9In the figure, the graphic part filled with black dots is the second metal layer 420 horizontally deployed inside the transistor of the pixel structure 600, the graphic part filled with oblique lines is the first metal layer 410 vertically deployed inside the transistor of the pixel structure 600, the graphic part filled with intersecting oblique lines is the pixel electrode 490 in the pixel structure 600, and the graphic part filled with vertical lines is the common electrode 470 in the pixel structure 600. The image part drawn with dotted lines and filled with gray under the layer of the second metal layer 420 is the shielding layer 465 in the pixel structure 600. It can be seen from the transparency of the graphics that the graphics used for the first metal layer 410 and the second metal layer 420 can both pass through the gray graphics used to represent the shielding layer 465, so the shielding layer 465 is set under the first metal layer 410, and the graphics used to represent the second metal layer 420 can pass through the graphics used to represent the first metal layer 410, and the first metal layer 410 is located under the second metal layer.

[0102] Based on the above technical solution, by setting a blocking layer 465 at the channel of the pixel structure 600, even if the material of the active layer 455 overlapping with the channel in the first direction is A-Si or LTPS material that is more sensitive to light intensity, the characteristics of the active layer 455 will not be affected by the photogenerated carriers generated in the channel.

[0103] refer to Figure 8 As shown, the transistor of the pixel structure 600 further includes a second protective layer 495, which covers the shielding layer 465, and the second protective layer 495 is located under the first metal layer 410. In other words, the second protective layer 495 and the shielding layer 465 are equivalent to the substrate of the pixel structure 600, and the remaining layers in the pixel structure 600 are deposited on the substrate formed by the second protective layer 495 and the shielding layer 465.

[0104] In addition, based on the pixel structure 400 and the pixel structure 600 proposed in the aforementioned embodiments, the embodiments of the present application correspondingly propose a method for preparing the pixel structure.

[0105] In some possible embodiments, for preparing the pixel structure 400, the deposition process and deposition order of each layer can follow the existing process, so the pixel structure prepared based on the method includes: a transistor, the transistor includes: a first metal layer, a second metal layer, a control line, a data line, an insulating layer, and a first protective layer, wherein the insulating layer covers the first metal layer, the second metal layer is located on the insulating layer, and the first protective layer is located on the second metal layer.

[0106] However, compared with the existing process, the following key steps need to be performed:

[0107] Fig.10It is a flow chart of key steps of a method 1000 for preparing a pixel structure proposed in an embodiment of the present application.

[0108] S1010: Disposing a first via hole between the first metal layer and the second metal layer, wherein a first end of the first via hole is located in the first metal layer, and a second end of the first via hole is located in the second metal layer.

[0109] S1020: Extend a control line from the gate driver to the first metal layer, and electrically connect the control line to the second metal layer through a first via hole, and electrically isolate the control line from the first metal layer. The control line is used to transmit a gate control signal from the gate driver to the second metal layer.

[0110] S1030: Disposing a second via hole between the first metal layer and the second metal layer, wherein a first end of the second via hole is located in the second metal layer, and a second end of the second via hole is located in the first metal layer.

[0111] S1040: Extending a data line from the source driver to the second metal layer, electrically connecting the data line to the first metal layer through a second via hole, and electrically isolating the data line from the second metal layer, wherein the data line is used to transmit an image data signal from the source driver to the first metal layer.

[0112] It should be noted that Fig.10 The two adjacent steps shown do not mean that they are executed continuously. Other necessary process flows may be added between the two adjacent steps, and the embodiments of the present application do not limit this.

[0113] In some possible embodiments, the second metal layer includes a first portion and a second portion, then in the process of S1020: the control line is connected to the first portion of the second metal layer through the first via hole, and is electrically isolated from the first metal layer. In the process of S1040: the data line is connected to the first metal layer through the second via hole, and is electrically isolated from the second portion of the second metal layer. So that the first portion of the second metal layer is used to receive the gate control signal, and the data line originally connected to the second portion of the second metal layer is transferred to the first metal layer.

[0114] In some possible embodiments, before depositing the first protective layer, a pixel electrode is deposited, the pixel electrode is electrically connected to the second metal layer, and the pixel electrode is used to receive an image data signal; on the first protective layer, a common electrode is deposited, the common electrode is used to form a variable electric field with the pixel electrode, and the variable electric field is used for imaging.

[0115] Based on the above technical scheme, by introducing a first via and a second via into the transistor of the pixel structure, the control line originally connected to the first metal layer is transferred to the second metal layer, and the data line originally connected to the second metal layer is transferred to the first metal layer, so that the functions of the first metal layer and the second metal layer are swapped, that is, the first metal layer is used to realize the source and drain functions, and the second metal layer is used to realize the gate function. Compared with the structure in which there is only one protective layer between the S electrode and the common electrode in the existing pixel structure, the pixel structure proposed in this scheme has at least a first protective layer and an insulating layer between the first metal layer and the common electrode, thereby increasing the distance between the source and drain and the common electrode, reducing the capacitance between the first metal layer and the common electrode, which is beneficial to reducing the load on the data line. Even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided.

[0116] In some possible embodiments, for preparing the pixel structure 600 , the embodiment of the present application proposes another method for preparing the pixel structure.

[0117] Fig.11 1 is a flow chart of another method 1100 for preparing a pixel structure proposed in an embodiment of the present application. The method 1100 includes the following steps for preparing a transistor in a pixel structure:

[0118] S1110: depositing a first metal layer.

[0119] In some possible embodiments, the deposition process used in the embodiments of the present application may be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a volatile compound deposition process, or a sputtering deposition process.

[0120] S1120: depositing an insulating layer on the first metal layer, wherein the insulating layer covers the first metal layer.

[0121] S1130: depositing a second metal layer on the insulating layer.

[0122] S1140: depositing a first protective layer on the second metal layer, wherein the first protective layer covers the second metal layer.

[0123] S1150: Prepare a data line, and extend the data line from the source driver to the first metal layer, and connect the data line to the first metal layer. The data line is used to transmit the image data signal sent by the source driver to the first metal layer.

[0124] S1160: Prepare a control line, and extend the control line from the gate driver to the second metal layer, and connect the control line to the second metal layer. The control line is used to transmit the gate control signal sent by the gate driver to the second metal layer.

[0125] In some possible embodiments, the data line or the control line may be generated by metallization wiring, and the metallization wiring includes the following processes: PVD process, CVD process, electroplating, etc.

[0126] Based on the above technical scheme, compared with the existing process for preparing pixel structures, in the process flow for preparing pixel structures proposed in this scheme, the first metal layer with a lower transistor architecture level of the pixel structure is directly connected to the data line, so that the first metal layer is used to realize the source and drain functions, and the second metal layer with a higher transistor architecture level of the pixel structure is directly connected to the control line, so that the second metal layer is used to realize the gate function. Such a processing flow does not increase the number of masks used in the process of preparing the pixel structure, and compared with the structure in which there is only one protective layer between the S electrode and the common electrode in the existing pixel structure, the first metal layer of the transistor of the pixel structure proposed in this scheme is separated from the common electrode by at least a first protective layer and an insulating layer, which is equivalent to increasing the distance between the source and drain and the common electrode, reducing the capacitance between the first metal layer and the common electrode, and is beneficial to reducing the load on the data line. Even when the pixel charging rate is maximized, the occurrence of crosstalk can be effectively avoided, and it is also helpful to improve the pixel transmittance, and the preparation difficulty and cost are lower.

[0127] It should be understood that the first metal layer directly exists as the source and drain of the transistor in the pixel structure. Therefore, the first metal layer includes two parts, wherein the first part can be used as the source of the transistor and the second part can be used as the drain of the transistor.

[0128] In some possible embodiments, the method 1100 further includes the following steps:

[0129] A pixel electrode is deposited, the pixel electrode is electrically connected to the first metal layer, and the pixel electrode is used to receive an image data signal; a common electrode is deposited on the first protective layer, and the common electrode is used to form a variable electric field with the pixel electrode, and the variable electric field is used for imaging.

[0130] In some possible embodiments, if the pixel electrode is deposited first, the first metal layer is deposited adjacent to the pixel electrode; if the first metal layer is deposited first, the pixel electrode is deposited adjacent to the first metal layer.

[0131] Based on the above technical solution, since the data line in the pixel structure is directly connected to the first metal layer, and at least part of the first metal layer is also directly electrically connected to the pixel electrode, and the image data signal needs to be transmitted through a via between the SD electrode and the pixel electrode in the existing pixel structure, then based on the pixel structure prepared by this solution, when the transistor is turned on, the image data signal can be directly transmitted to the pixel electrode through the first metal layer. Not only does it no longer need to transfer the image data signal to the pixel electrode through the dielectric layer, but it can also reduce the vias at the connection of the pixel electrode. Therefore, the difficulty and cost of preparing the pixel structure proposed by this solution can be further reduced.

[0132] In some possible embodiments, before the above-mentioned 1120, method 1100 also includes the following steps: depositing a shielding layer, the position of the shielding layer corresponds to the channel of the transistor, and the shielding layer is used to shield the photogenerated carriers generated in the channel; depositing an active layer, the active layer covers at least part of the first metal layer, and the active layer overlaps with the projection of the channel of the transistor in the first direction.

[0133] Considering that the material of the active layer is A-Si material or LTPS material, the mobility of A-Si material or LTPS material is more sensitive to light intensity, and there is an overlap between the projection of the active layer and the channel in the first direction, then when photogenerated carriers are generated in the channel inside the transistor of the pixel structure, it will directly affect the characteristics of the active layer, so the above method 1100 may also include the following steps: depositing a shielding layer, the position of the shielding layer corresponds to the channel of the transistor, and the shielding layer is used to shield the photogenerated carriers generated in the channel.

[0134] In some possible embodiments, the method 1100 may further include the following steps: depositing a second protective layer, the second protective layer covers the shielding layer, and the first metal layer is deposited on the second protective layer. It can be seen that the deposition of the shielding layer and the deposition of the second protective layer are completed before the deposition of the first metal layer and the deposition of the pixel electrode.

[0135] Based on the above technical solution, by setting a blocking layer at the channel of the transistor applied to the pixel structure, even if the material of the active layer overlapping with the channel in the first direction is A-Si or LTPS material that is more sensitive to light intensity, the characteristics of the active layer will not be affected by the photogenerated carriers generated in the channel.

[0136] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0137] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0138] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0141] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0142] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A pixel structure, characterized in that: include: A transistor, comprising: a first metal layer (410), a second metal layer (420), a control line (430), a data line (440), an insulating layer (450), and a first protective layer (460), The insulating layer (450) covers the first metal layer (410); The second metal layer (420) is located on the insulating layer (450); The first protective layer (460) is located on the second metal layer (420); A first via hole (481) is provided between the first metal layer (410) and the second metal layer (420); a first end (4811) of the first via hole (481) is located in the first metal layer (410); a second end (4812) of the first via hole (481) is located in the second metal layer (420); the control line (430) extends from the gate driver to the first metal layer (410), and is electrically connected to the second metal layer (420) through the first via hole (481), and is electrically isolated from the first metal layer (410); the control line (430) is used to transmit a gate control signal sent by the gate driver to the second metal layer (420); A second via hole (482) is also provided between the first metal layer (410) and the second metal layer (420); a first end (4821) of the second via hole (482) is located in the second metal layer (420); a second end (4822) of the second via hole (482) is located in the first metal layer (410); the data line (440) extends from the source driver to the second metal layer (420), and is electrically connected to the first metal layer (410) through the second via hole (482), and is electrically isolated from the second metal layer (420); the data line (440) is used to transmit an image data signal emitted by the source driver to the first metal layer (410).

2. The pixel structure according to claim 1, characterized in that: The pixel structure further comprises: a common electrode (470) and a pixel electrode (490), wherein the common electrode (470) and the pixel electrode (490) are isolated from each other by the first protective layer (460), the pixel electrode (490) is electrically connected to the second metal layer (420), the pixel electrode (490) is used to receive the image data signal, and the common electrode (470) is used to form a variable electric field with the pixel electrode (490), and the variable electric field is used for imaging.

3. The pixel structure according to claim 1 or 2, characterized in that: The second metal layer (420) includes a first part (421) and a second part (422); the control line (430) is electrically isolated from the first metal layer (410) through the first via hole (481) and connected to the first part (421) of the second metal layer (420); the data line (440) is electrically isolated from the second part (422) of the second metal layer (420) through the second via hole (482) and connected to the first metal layer (410).

4. A pixel structure, characterized in that: include: A transistor, comprising: a first metal layer (410), a second metal layer (420), a control line (430), a data line (440), an insulating layer (450), and a first protective layer (460), The insulating layer (450) covers the first metal layer (410); The data line (440) extends from the source driver to the first metal layer (410) and is connected to the first metal layer (410), and the data line (440) is used to transmit the image data signal sent by the source driver to the first metal layer (410); The second metal layer (420) is located on the insulating layer (450); The control line (430) extends from the gate driver to the second metal layer (420) and is connected to the second metal layer (420), and the control line (430) is used to transmit the gate control signal sent by the gate driver to the second metal layer (420); The first protective layer (460) covers the second metal layer (420).

5. The pixel structure according to claim 4, characterized in that: The pixel structure further comprises: a common electrode (470) and a pixel electrode (490); the common electrode (470) and the pixel electrode (490) are isolated from each other by the first protective layer (460) and the insulating layer (450); the pixel electrode (490) is electrically connected to the first metal layer (410); the pixel electrode (490) is used to receive the image data signal; the common electrode (470) is used to form a variable electric field with the pixel electrode (490); and the variable electric field is used for imaging.

6. The pixel structure according to claim 4 or 5, characterized in that: The transistor further comprises: an active layer (455), the active layer (455) being covered by the insulating layer (450), the active layer (455) covering at least a portion of the first metal layer (410), and the active layer (455) overlapping with a projection of a channel of the transistor in a first direction; A shielding layer (465), the shielding layer (465) is arranged at the channel, and the shielding layer (465) is used to shield the photogenerated carriers generated in the channel.

7. The pixel structure according to claim 6, characterized in that: The transistor further comprises: A second protective layer (495), the second protective layer covers the shielding layer (465), and the second protective layer (495) is located under the first metal layer (410).

Images