Light-emitting display device

Abstract

According to an embodiment, a light-emitting display device is provided, the light-emitting display device comprising: a substrate; a first anode and a second anode, located on the substrate; a plurality of conductive layers, at least one semiconductor layer and a plurality of insulating layers, located between the substrate and the first anode and between the substrate and the second anode, wherein the plurality of conductive layers comprises a capacitor trilayer, a first stacked wiring and a second stacked wiring, the first stacked wiring and the second stacked wiring are at least partially stacked on a plane, at least a portion of the first anode is stacked with the capacitor trilayer on a plane, and a first portion of the second anode is stacked with the first stacked wiring and the second stacked wiring. According to an embodiment, a reflection diffraction pattern or a reflection color band generated when external light is reflected can be reduced.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0086431 filed in the Korean Intellectual Property Office on July 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a light-emitting display device. Background Art

[0003] A display device is a device for displaying an image, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED) display, etc. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game machines, and various terminals.

[0004] A light emitting display device such as an organic light emitting display may have a structure in which the display device may be bent or folded by using a flexible substrate. Utility Model Content

[0005] The utility model aims to provide a light-emitting display device for reducing a reflection diffraction pattern or a reflection color band generated when external light is reflected.

[0006] According to the embodiment, the light-emitting display device includes: a substrate; a first anode and a second anode, which are located on the substrate; a plurality of conductive layers, at least one semiconductor layer and a plurality of insulating layers, which are located between the substrate and the first anode and between the substrate and the second anode, wherein the plurality of conductive layers include a capacitor three-layer, a first stacked wiring and a second stacked wiring, the first stacked wiring and the second stacked wiring are at least partially stacked, at least a portion of the first anode is stacked with the capacitor three-layer, and a first portion of the second anode is stacked with the first stacked wiring and the second stacked wiring.

[0007] Multiple conductive layers, at least one semiconductor layer and multiple insulating layers may include: a first semiconductor layer, located on a substrate; a first gate insulating layer, located on the first semiconductor layer; a first gate conductive layer, located on the first gate insulating layer; a second gate insulating layer, located on the first gate conductive layer; a second gate conductive layer, located on the second gate insulating layer; a first interlayer insulating layer, located on the second gate conductive layer; an auxiliary conductive layer, located on the first interlayer insulating layer; a second interlayer insulating layer, located on the auxiliary conductive layer; an oxide semiconductor layer, located on the second interlayer insulating layer; a third gate insulating layer, located on the oxide semiconductor layer; a third gate conductive layer, located on the third gate insulating layer; a third interlayer insulating layer, located on the third gate conductive layer; a first data conductive layer, located on the third interlayer insulating layer; a first organic layer, located on the first data conductive layer; a second data conductive layer, located on the first organic layer; and a second organic layer, located on the second data conductive layer.

[0008] The three layers of the capacitor may include: a driving gate electrode, included in a first gate conductive layer; a second storage electrode, included in a second gate conductive layer; and a first holding electrode, included in an auxiliary conductive layer, and at least a portion of the driving gate electrode, at least a portion of the second storage electrode, and at least a portion of the first holding electrode may overlap each other.

[0009] The first anode and the second anode may overlap the second data conductive layer.

[0010] The first anode and the second anode may overlap the driving voltage line in the second data conductive layer.

[0011] The first stacked wiring may be located in one conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and the second stacked wiring may be located in a different conductive layer from the first stacked wiring which is one conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer.

[0012] The multiple conductive layers may also include a third stacked wiring, which may be at least partially overlapped with the first stacked wiring and the second stacked wiring, and the third stacked wiring may be a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and may be located in a different conductive layer from the first stacked wiring and the second stacked wiring.

[0013] The first overlapping wiring may be a repair line in the second gate conductive layer, the second overlapping wiring may be a lower second initialization voltage line in the auxiliary conductive layer, and the third overlapping wiring may be an upper second initialization voltage line in the third gate conductive layer.

[0014] The multiple conductive layers may also include a fourth stacked wiring, a fifth stacked wiring and a sixth stacked wiring, the fourth stacked wiring, the fifth stacked wiring and the sixth stacked wiring may at least partially overlap each other, and the second portion of the second anode may overlap with the fourth stacked wiring, the fifth stacked wiring and the sixth stacked wiring.

[0015] The fourth overlapped wiring may be a third scan line in the first gate conductive layer, the fifth overlapped wiring may be a first initialization voltage line in the second gate conductive layer, and the sixth overlapped wiring may be a first scan line in the third gate conductive layer.

[0016] The first overlapping wiring may be a third scan line in the first gate conductive layer, the second overlapping wiring may be a first initialization voltage line in the second gate conductive layer, and the third overlapping wiring may be a first scan line in the third gate conductive layer.

[0017] According to an embodiment, the light-emitting display device includes: a substrate; a first anode located on the substrate; and a plurality of conductive layers, at least one semiconductor layer and a plurality of insulating layers located between the substrate and the first anode, wherein the plurality of conductive layers include a capacitor three-layer, a first stacked wiring and a second stacked wiring, the first stacked wiring and the second stacked wiring are at least partially stacked, at least a first portion of the first anode is stacked with the capacitor three-layer, and at least a second portion of the first anode is stacked with the first stacked wiring and the second stacked wiring.

[0018] Multiple conductive layers, at least one semiconductor layer and multiple insulating layers may include: a first semiconductor layer, located on a substrate; a first gate insulating layer, located on the first semiconductor layer; a first gate conductive layer, located on the first gate insulating layer; a second gate insulating layer, located on the first gate conductive layer; a second gate conductive layer, located on the second gate insulating layer; a first interlayer insulating layer, located on the second gate conductive layer; an auxiliary conductive layer, located on the first interlayer insulating layer; a second interlayer insulating layer, located on the auxiliary conductive layer; an oxide semiconductor layer, located on the second interlayer insulating layer; a third gate insulating layer, located on the oxide semiconductor layer; a third gate conductive layer, located on the third gate insulating layer; a third interlayer insulating layer, located on the third gate conductive layer; a first data conductive layer, located on the third interlayer insulating layer; a first organic layer, located on the first data conductive layer; a second data conductive layer, located on the first organic layer; and a second organic layer, located on the second data conductive layer.

[0019] The three layers of the capacitor may include: a driving gate electrode, included in a first gate conductive layer; a second storage electrode, included in a second gate conductive layer; and a first holding electrode, included in an auxiliary conductive layer, wherein at least a portion of the driving gate electrode, at least a portion of the second storage electrode, and at least a portion of the first holding electrode may overlap each other.

[0020] The entire first anode may overlap the second data conductive layer.

[0021] The entire first anode may overlap the driving voltage line positioned in the second data conductive layer.

[0022] The first stacked wiring may be located in a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and the second stacked wiring may be a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and be located in a different conductive layer from the first stacked wiring.

[0023] The multiple conductive layers may also include a third stacked wiring, which may be at least partially overlapped with the first stacked wiring and the second stacked wiring, and the third stacked wiring may be a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and may be located in a different conductive layer from the first stacked wiring and the second stacked wiring.

[0024] Two of the first stacked wiring, the second stacked wiring, and the third stacked wiring may receive the same voltage or signal.

[0025] The first overlapping wiring may be a lower first initialization voltage line located in the first gate conductive layer, the second overlapping wiring may be an upper first initialization voltage line located in the second gate conductive layer, and the third overlapping wiring may be a second / first scan line located in the third gate conductive layer.

[0026] According to an embodiment, since the polarizer is not formed on the front surface, even if incident external light is reflected from the anode, the flatness of the anode can be improved to prevent the reflected light from diffusing asymmetrically, thereby improving the display quality by reducing the reflected diffraction pattern or the reflected color band phenomenon caused by the reflected light.

[0027] In addition, by positioning the three conductive layers below the anode, there is no height difference between the anodes stacked with the two capacitors and the anode is flattened, so that reflected light is not asymmetrically diffused.

[0028] In addition, since the black pixel defining layer is used as a pixel defining layer that separates the light emitting layers from each other instead of a polarizer, the ratio of reflected external light can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is an equivalent circuit diagram of one pixel included in a light emitting display device according to an embodiment.

[0030] Figure 2 is shown applied to Figure 1 Waveform diagram of the pixel signal.

[0031] Figure 3 is a cross-sectional view of a light emitting display device according to an embodiment.

[0032] Figure 4is a view schematically showing a layer structure of a light emitting display device according to an embodiment.

[0033] Figure 5 is a view showing a planar structure of some conductive layers and an anode of a lower panel layer in a light-emitting display device according to an embodiment.

[0034] Figure 6 is based on Figure 5 A cross-sectional view of a light-emitting display device of an embodiment.

[0035] Figure 7 is a view showing a planar structure of some conductive layers and an anode of a lower panel layer in a light-emitting display device according to a comparative example.

[0036] Figure 8 is based on Figure 7 A cross-sectional view of a light-emitting display device of an embodiment.

[0037] Fig. 9 is a view showing a planar structure of some conductive layers and anodes of a lower panel layer in a light-emitting display device according to another embodiment.

[0038] Fig.10 is based on Fig. 9 A cross-sectional view of a light-emitting display device of an embodiment.

[0039] Fig.11 is a view showing a planar structure of some conductive layers and anodes of a lower panel layer in a light-emitting display device according to another comparative example.

[0040] Fig.12 is based on Fig.11 A cross-sectional view of a light-emitting display device of an embodiment.

[0041] Fig.13 It is a view schematically comparing the structures of a comparative example and one embodiment. DETAILED DESCRIPTION

[0042] The present invention will be described more fully below with reference to the accompanying drawings, in which embodiments of the present invention are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0043] In order to clarify the present invention, parts irrelevant to the description will be omitted, and the same elements or equivalents are denoted by the same reference numerals throughout the specification.

[0044] In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively displayed for better understanding and ease of description.

[0045] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element such as a layer, film, region, or substrate may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean being positioned on or below an object portion, and do not necessarily mean being positioned on the upper side of the object portion based on the direction of gravity.

[0046] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0047] Furthermore, in the specification, the phrase "on a plane" means when the subject portion is viewed from above, and the phrase "on a cross section" means when a cross section taken by vertically cutting the subject portion is viewed from the side.

[0048] In addition, in the specification, the expression "connected to" means not only that two or more constituent elements are directly connected, but also that two or more constituent elements are electrically connected through other constituent elements as well as indirectly connected and physically connected, or it may mean that they are referred to by different names according to position or function but are integrated.

[0049] In addition, throughout the specification, when components such as wiring, layers, films, regions, boards, and constituent elements are referred to as "extending in the first direction or the second direction", this not only means a straight line shape extending linearly in the corresponding direction, but also includes a structure that is bent in a portion, has a Z-shaped structure, or is bent while extending generally along the first direction or the second direction.

[0050] In addition, electronic devices (e.g., mobile phones, TVs, monitors, laptop computers) including the display devices and display panels described in the specification, or electronic devices including the display devices and display panels manufactured by the manufacturing methods described in the specification, are not excluded from the scope of this specification.

[0051] In the following, reference is made to Figure 1 A circuit structure of one pixel in the light emitting display device according to the embodiment is described.

[0052] Figure 1 is an equivalent circuit diagram of one pixel included in a light emitting display device according to an embodiment.

[0053] Reference Figure 1 , one pixel includes a light emitting diode LED and a pixel circuit unit for driving the light emitting diode LED, and the pixel circuit unit is arranged in a matrix type. The pixel circuit unit includes Figure 1 All other components except the LED in the Figure 1 The pixel circuit unit of the pixel of the embodiment includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a storage capacitor Cst and a holding capacitor Chold. In addition, the pixel circuit unit is connected to a first scan line 161 to which a first scan signal GW is applied, a second scan line 162 to which a second scan signal GC is applied, a second / first scan line 167 to which a second / first scan signal GC2 corresponding to the second scan signal GC is applied, a third scan line 163 to which a third scan signal GI is applied, light emitting signal lines 164 and 165 to which light emitting signals EM1 and EM2 are applied, a fourth scan line 166 to which a fourth scan signal EB is applied, and a data line 171 to which a data voltage VDATA is applied. In addition, the pixel can receive a driving voltage ELVDD (hereinafter referred to as the first driving voltage), a driving low voltage ELVSS (hereinafter referred to as the second driving voltage), a first initialization voltage VINT, a second initialization voltage VAINT, a reference voltage VREF and a bias voltage Vbias through a driving voltage line 172, a driving low voltage line 179, a first initialization voltage line 173, a second initialization voltage line 175, a reference voltage line 174 and a bias voltage line 176, respectively.

[0054] The structure of a pixel is described as follows, focusing on each element (transistor, capacitor, and light emitting diode) included in the pixel.

[0055] The driving transistor T1 includes a gate electrode (hereinafter, referred to as a driving gate electrode) connected to the first electrode of the storage capacitor Cst (also referred to as a first storage electrode), a first electrode (input side electrode) connected to the driving voltage line 172 through the ninth transistor T9, and a second electrode (output side electrode) outputting a current according to the voltage of the driving gate electrode.

[0056] The gate electrode of the driving transistor T1 (hereinafter, also referred to as the first transistor) is connected to the second electrode (output side electrode) of the eleventh transistor T11 and the first electrode of the storage capacitor Cst. The first electrode of the driving transistor T1 is connected to the second electrode (output side electrode) of the ninth transistor T9 and the second electrode (output side electrode) of the eighth transistor T8 to receive the driving voltage ELVDD and / or the bias voltage Vbias, and the second electrode of the driving transistor T1 is connected to the first electrode (input side electrode) of the third transistor T3 and the first electrode (input side electrode) of the sixth transistor T6. The output current of the driving transistor T1 passes through the sixth transistor T6 and is transmitted to the light emitting diode LED so that the light emitting diode LED emits light. The brightness of the light emitted by the light emitting diode LED is determined according to the size of the output current of the driving transistor T1. At the same time, the driving transistor T1 may also include a stacking electrode BML stacked with at least a portion (e.g., a channel) of the semiconductor (e.g., a polycrystalline semiconductor) of the driving transistor T1. Figure 1 It is shown using a dotted line that the stacked electrode BML can be connected to the driving voltage line 172 to receive the driving voltage ELVDD. The dotted line connection shows that the connection is only an option. In some embodiments, the stacked electrode BML may not be connected to the driving voltage line 172, but may be connected to another part (e.g., the first electrode or the second electrode of the driving transistor T1, or another voltage line).

[0057] The second transistor T2 (hereinafter, also referred to as a data input transistor) includes a gate electrode connected to the first scan line 161 to which the first scan signal GW is applied, a first electrode (input side electrode) connected to the data line 171 to which the data voltage VDATA is applied, and a second electrode (output side electrode) connected to the second electrode of the fifth transistor T5 and the first electrode of the tenth transistor T10. The second transistor T2 inputs the data voltage VDATA into the pixel according to the first scan signal GW to store the data voltage VDATA in the second electrode (also referred to as the second storage electrode) of the storage capacitor Cst through the tenth transistor T10.

[0058] The third transistor T3 (hereinafter, also referred to as the first compensation transistor) includes a gate electrode connected to the second scan line 162 to which the second scan signal GC is applied, a first electrode (input side electrode) connected to the second electrode of the driving transistor T1 and the first electrode of the sixth transistor T6, and a second electrode (output side electrode) connected to the first electrode of the eleventh transistor T11 and the second electrode of the fourth transistor T4. The third transistor T3 forms a compensation path for compensating the threshold voltage of the driving transistor T1 together with the eleventh transistor T11 (hereinafter, also referred to as the second compensation transistor) so that the threshold voltage of the driving transistor T1 can be stored in the first electrode of the storage capacitor Cst to be compensated. As a result, even if the threshold voltage of the driving transistor T1 included in each pixel is different, the driving transistor T1 can output a constant output current according to the applied data voltage VDATA.

[0059] The fourth transistor T4 (hereinafter, referred to as the first initialization transistor) includes a gate electrode connected to the third scan line 163 to which the third scan signal GI is applied, a first electrode receiving the first initialization voltage VINT, and a second electrode connected to the second electrode of the third transistor T3 and the first electrode of the eleventh transistor T11. The fourth transistor T4 is used to initialize the second electrode of the third transistor T3 and the first electrode of the eleventh transistor T11 to the first initialization voltage VINT by transmitting the first initialization voltage VINT into the pixel, and if the eleventh transistor T11 is turned on in a subsequent period, the gate electrode of the driving transistor T1 connected to the eleventh transistor T11 and the first electrode of the storage capacitor Cst (i.e., the gate node G_node) can be initialized.

[0060] The fifth transistor T5 (hereinafter, also referred to as a data node initialization transistor) includes a gate electrode connected to the second scan line 162 to which the second scan signal GC is applied, a first electrode receiving a reference voltage VREF, and a second electrode connected to the first electrode of the tenth transistor T10 and the second electrode of the second transistor T2. The fifth transistor T5 is used to change each of the second electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold to be initialized into the reference voltage VREF through the tenth transistor T10. Meanwhile, according to an embodiment, the driving voltage ELVDD instead of the reference voltage VREF may be applied to the first electrode of the fifth transistor T5.

[0061] The sixth transistor T6 (hereinafter, also referred to as a current transmission transistor) includes a gate electrode connected to the second light emitting signal line 165 to which the second light emitting signal EM2 is applied, a first electrode (input side electrode) connected to the second electrode of the driving transistor T1 and the first electrode of the third transistor T3, and a second electrode (output side electrode) connected to the anode of the light emitting diode LED and the second electrode of the seventh transistor T7. The sixth transistor T6 is used to transmit the output current of the driving transistor T1 to the light emitting diode LED based on the second light emitting signal EM2, or to block the output current of the driving transistor T1 from being transmitted to the light emitting diode LED based on the second light emitting signal EM2.

[0062] The seventh transistor T7 (hereinafter, also referred to as an anode initialization transistor) includes a gate electrode connected to the fourth scan line 166 to which the fourth scan signal EB is applied, a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to the anode of the light emitting diode LED and the second electrode of the sixth transistor T6. The seventh transistor T7 is used to initialize the anode of the light emitting diode LED to the second initialization voltage VAINT. According to an embodiment, the seventh transistor T7 may be an oxide transistor including an oxide semiconductor, and may be turned on by a high level voltage and turned off by a low level voltage. In addition, according to an embodiment, the gate electrode of the seventh transistor T7 may be connected to a separate signal line other than the fourth scan line 166 (for example, one of the light emitting signal lines 164 and 165 to which the light emitting signals EM1 and EM2 are applied).

[0063] The eighth transistor T8 (hereinafter, referred to as a bias transistor) includes a gate electrode connected to the fourth scan line 166 to which the fourth scan signal EB is applied, a first electrode receiving a bias voltage Vbias, and a second electrode connected to the first electrode of the driving transistor T1 and the second electrode of the ninth transistor T9. The eighth transistor T8 can transmit the bias voltage Vbias to the first electrode of the driving transistor T1 so that the characteristics of the driving transistor T1 can be kept constant. For example, if the bias voltage Vbias is transmitted to the first electrode of the driving transistor T1, even if the driving transistor T1 does not receive a separate data voltage VDATA, an output current can be constantly generated using the previously received data voltage VDATA. This operation can be used to maintain the characteristics of the driving transistor T1 during high-speed driving or low-speed driving.

[0064] The ninth transistor T9 (hereinafter, also referred to as a driving voltage transmission transistor) includes a gate electrode connected to the first light emitting signal line 164 to which the first light emitting signal EM1 is applied, a first electrode (input side electrode) receiving the driving voltage ELVDD, and a second electrode (output side electrode) connected to the first electrode of the driving transistor T1 and the second electrode of the eighth transistor T8. The ninth transistor T9 can transmit the driving voltage ELVDD to the first electrode of the driving transistor T1, so that the driving transistor T1 can generate a current.

[0065] The tenth transistor T10 (hereinafter, also referred to as a data voltage transmission transistor) includes a gate electrode connected to the second / first scan line 167 (hereinafter, referred to as an oxide transistor scan line) to which the second / first scan signal GC2 is applied, a first electrode connected to the second electrode of the second transistor T2 and the second electrode of the fifth transistor T5, and a second electrode connected to the second electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold. The tenth transistor T10 is used to change the voltage of the gate electrode of the driving transistor T1 by transmitting the data voltage VDATA to the second electrode of the storage capacitor Cst; in addition, the reference voltage VREF may be transmitted to the second electrode of the storage capacitor Cst according to the timing. Here, the node connected to the second electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold is the node to which the data voltage VDATA is transmitted, and is therefore also referred to as a data node D_node. At the same time, the tenth transistor T10 may further include a first auxiliary electrode CMTL1 overlapping at least a portion (e.g., a channel) of the semiconductor (e.g., an oxide semiconductor) of the tenth transistor T10. Figure 1 The first auxiliary electrode CMTL1 connected to the second / first scan line 167 is shown in dotted lines. The connection using dotted lines means that the first auxiliary electrode CMTL1 is not connected to the second / first scan line 167 of the current stage, and can be connected to another part (for example, any voltage line or the second / first scan line 167 of the previous stage or the next stage).

[0066] The eleventh transistor T11 (hereinafter, also referred to as the second compensation transistor) includes a gate electrode connected to the second / first scan line 167 to which the second / first scan signal GC2 is applied, a first electrode connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, and a second electrode connected to the gate electrode of the driving transistor T1 and the first electrode of the storage capacitor Cst. The eleventh transistor T11, together with the third transistor T3, can form a compensation path for compensating the threshold voltage of the driving transistor T1, so that the threshold voltage of the driving transistor T1 can be stored in the first electrode of the storage capacitor Cst to be compensated. As a result, even if the threshold voltage of the driving transistor T1 included in each pixel is different, the driving transistor T1 can output a constant output current according to the applied data voltage VDATA. At the same time, the eleventh transistor T11 may further include a second auxiliary electrode CMTL2 overlapping at least a portion (e.g., a channel) of the semiconductor (e.g., an oxide semiconductor) of the eleventh transistor T11. Figure 1 The second auxiliary electrode CMTL2 is shown to be connected to the second / first scan line 167 and / or the gate electrode (hereinafter, also referred to as the gate) of the eleventh transistor T11 by a dotted line. The connection using a dotted line means that it is not connected to the second / first scan line 167 of the current stage, and can be connected to another part (for example, any voltage line or the second / first scan line 167 of the previous stage or the next stage).

[0067] exist Figure 1 In the embodiment of FIG. 1 , all transistors can be divided into p-type transistors formed using polycrystalline semiconductors and n-type transistors formed using oxide semiconductors. Figure 1 , the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are polycrystalline transistors including polycrystalline semiconductors, and the tenth transistor T10 and the eleventh transistor T11 are oxide transistors including oxide semiconductors. In addition, Figure 1 In the embodiment of the present invention, the polycrystalline transistor is a p-type transistor that can be turned on by a low-level voltage and turned off by a high-level voltage. On the other hand, the oxide transistor is an n-type transistor and can be turned on by a high-level voltage and turned off by a low-level voltage. According to an embodiment, the seventh transistor T7 may be an oxide transistor including an oxide semiconductor and can be turned on by a high-level voltage and turned off by a low-level voltage.

[0068] The storage capacitor Cst (hereinafter, also referred to as a voltage transfer capacitor) includes a first electrode (hereinafter, also referred to as a first storage electrode) connected to the gate electrode of the driving transistor T1 and the second electrode of the eleventh transistor T11 (i.e., the gate node G_node), and a second electrode (hereinafter, also referred to as a second storage electrode) connected to the second electrode of the tenth transistor T10 and the second electrode of the holding capacitor Chold (i.e., the data node D_node). The storage capacitor Cst receives the data voltage VDATA through the second transistor T2 and the tenth transistor T10, or receives the reference voltage VREF through the fifth transistor T5 and the tenth transistor T10 to change the voltage of the gate electrode of the driving transistor T1 and maintain the transfer voltage until the next voltage is transmitted. In the pixel of the present embodiment, the data voltage VDATA is not directly transmitted to the gate electrode of the driving transistor T1, but is transmitted through the storage capacitor Cst. Due to the fact that the voltage of the first electrode of the storage capacitor Cst also rises when the voltage of the second electrode thereof suddenly rises, this is a method of indirectly transmitting the data voltage VDATA to the gate electrode of the driving transistor T1. According to this method, even if leakage occurs in at least one transistor (for example, the second transistor T2) among the transistors included in the pixel, the voltage of the gate electrode of the driving transistor T1 does not leak directly, thereby minimizing any negative impact from the leakage. In addition, in the present embodiment, the data voltage VDATA passes through the storage capacitor Cst and is directly transmitted to the gate electrode of the driving transistor T1 without passing through other electrodes of the driving transistor T1, so even if the driving voltage ELVDD differs according to the position of the pixel, the driving voltage ELVDD can be changed according to the pixel position, and there is also an advantage of determining the voltage stored in the storage capacitor Cst without affecting the difference.

[0069] The holding capacitor Chold includes a first electrode (hereinafter, also referred to as a first holding electrode) receiving the driving voltage ELVDD, and a second electrode (hereinafter, also referred to as a second holding electrode) connected to the second electrode of the storage capacitor Cst and the second electrode of the tenth transistor T10 (ie, the data node D_node), and is used to keep the voltage of the second electrode of the storage capacitor Cst (ie, the voltage of the data node D_node) constant. That is, according to the holding capacitor Chold, the voltage of the second electrode of the storage capacitor Cst (ie, the data node D_node) does not change, and can have a constant voltage even when the surrounding signal changes.

[0070] The light emitting diode LED includes an anode connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and a cathode connected to the driving low voltage line 179. The light emitting diode LED can emit light with a brightness corresponding to the current supplied from the pixel circuit unit (actually, the driving transistor T1) by being located between the pixel circuit unit and the driving low voltage line 179. The light emitting diode LED may include a light emitting layer, which includes at least one of an organic light emitting material and an inorganic light emitting material. Holes and electrons are injected into the light emitting layer from the anode and the cathode, respectively, and light emission occurs when the excitons formed by the injected holes and electrons recombine from the excited state to the ground state. The light emitting diode LED may emit light of one color in the primary colors or white light. Examples of primary colors include three primary colors of red, green and blue. Another example of primary colors includes yellow, cyan and magenta. According to an embodiment, the color display characteristics may be improved by further including an additional color filter or a color conversion layer.

[0071] In accordance with Figure 1 In the pixel of the embodiment, when driving the gate electrode 1151 (see Figure 3 ) on a path (hereinafter, referred to as a data voltage transmission path) for transmitting the data voltage VDATA, two transistors (a second transistor T2 and a tenth transistor T10) and a storage capacitor Cst are positioned. That is, the storage capacitor Cst and the tenth transistor T10 are located between the driving gate electrode 1151 of the driving transistor T1 and the second transistor T2. At this time, the data voltage VDATA is not directly transmitted to the driving gate electrode 1151 of the driving transistor T1, but is transmitted to the second storage electrode of the storage capacitor Cst. When the voltage of the second storage electrode is changed while the data voltage VDATA is applied to the second storage electrode, the data voltage VDATA is indirectly transmitted while changing the voltage of the first storage electrode and the voltage of the driving gate electrode 1151. When the two transistors (the second transistor T2 and the tenth transistor T10) are turned on together, the transmission of the data voltage VDATA is performed. In addition, the tenth transistor T10 has different characteristics from the driving transistor T1 and the second transistor T2, and the two transistors included in the data voltage transmission path have different characteristics. That is, the driving transistor T1 and the second transistor T2 are formed of p-type polycrystalline transistors, but the tenth transistor T10 is formed of an n-type oxide transistor. In addition, the tenth transistor T10 adjusts the voltage applied to the first auxiliary electrode CMTL1 to adjust the characteristics of the tenth transistor T10 so that the data voltage VDATA can be fully charged to the storage capacitor Cst even in a short time, thereby improving the display quality of the light-emitting display device.

[0072] In addition to the storage capacitor Cst, according to Figure 1The pixel of the embodiment of the present invention further includes a holding capacitor Chold to keep the voltage of the data node D_node (ie, the data voltage VDATA input to the pixel) more constant. Figures 3 to 13 , the driving gate electrode of the driving transistor T1, the storage capacitor Cst, and the holding capacitor Chold may be formed to be stacked on a plane.

[0073] In accordance with Figure 1 In the pixel of the embodiment of the present invention, two transistors (the third transistor T3 and the eleventh transistor T11) are formed on a compensation path for compensating the threshold voltage of the driving transistor T1, and the two transistors (the third transistor T3 and the eleventh transistor T11) must be turned on together to compensate for the threshold voltage of the driving transistor T1. In addition, the eleventh transistor T11 has different characteristics from the driving transistor T1 and the third transistor T3, and the two transistors included in the compensation path have different characteristics. That is, the driving transistor T1 and the third transistor T3 are formed by p-type polycrystalline transistors, but the eleventh transistor T11 is formed by an n-type oxide transistor. In addition, the eleventh transistor T11 adjusts the voltage applied to the second auxiliary electrode CMTL2 to adjust the characteristics of the eleventh transistor T11, so that the compensation operation can be performed even in a short time, thereby improving the display quality of the light-emitting display device even under high-speed driving.

[0074] In the following, the following is described in detail. Figure 2 The waveform signal is applied to Figure 1 Pixel-by-pixel operations.

[0075] Figure 2 is shown applied to Figure 1 Waveform diagram of the pixel signal.

[0076] Reference Figure 2 , if the signals applied to the pixels are divided into a plurality of parts, they are divided into an initialization and compensation part, a writing part, a bias part, and a light emitting part.

[0077] First, the light emitting part is the following part: the light emitting diode LED emits light, and the gate-on voltage (low level voltage) is applied to the first light emitting signal line 164 and the second light emitting signal line 165 to turn on the sixth transistor T6 and the ninth transistor T9. The driving voltage ELVDD is applied to the driving transistor T1, and the driving transistor T1 generates an output current according to the voltage of the driving gate electrode (or the first storage electrode), and the output current of the driving transistor T1 passes through the turned-on sixth transistor T6 and is transmitted to the light emitting diode LED. Therefore, in the light emitting part, the light emitting diode LED emits light according to the size of the transmitted output current. Figure 2In the embodiment, it is hardly shown that the gate-on voltage (low level voltage) is applied to the light-emitting parts of the light-emitting signal lines 164 and 165, but in fact, the light-emitting parts have the longest time. However, the light-emitting parts only perform the simple operation as described above, so in Figure 2 is simply shown in .

[0078] If the light emitting part ends, the initialization and compensation part begins. Here, in the initialization and compensation part, some electrodes and nodes are initialized, while other electrodes and nodes perform compensation operations.

[0079] When the second light emitting signal EM2 becomes the gate-off voltage (high level voltage), the light emitting part ends. The sixth transistor T6 applied with the second light emitting signal EM2 becomes the off state, the ninth transistor T9 applied with the first light emitting signal EM1 remains in the on state, and the driving voltage ELVDD is continuously applied to the first electrode of the driving transistor T1. The part applied with the gate-off voltage of the second light emitting signal EM2 includes an initialization and compensation part, a writing part, and a bias part.

[0080] After becoming the gate-off voltage of the second light emitting signal EM2, the second / first scanning signal GC2 becomes the gate-on voltage (high level voltage), and the third scanning signal GI becomes the gate-on voltage (low level voltage). As a result, the tenth transistor T10 and the eleventh transistor T11 receiving the second / first scanning signal GC2 are turned on, and the fourth transistor T4 receiving the third scanning signal GI is turned on.

[0081] Through the turned-on fourth transistor T4, the first initialization voltage VINT is transmitted to the second electrode of the third transistor T3 connected to the second electrode of the fourth transistor T4 and the first electrode of the eleventh transistor T11. At this time, since the eleventh transistor T11 is also turned on, the first initialization voltage VINT is transmitted to the gate node G_node, and then the driving gate electrode of the driving transistor T1 and the first storage electrode of the storage capacitor Cst are also initialized to the first initialization voltage VINT. Here, the first initialization voltage VINT may have a low level voltage value, and according to an embodiment, the first initialization voltage VINT may be a low voltage capable of turning on the driving transistor T1.

[0082] Meanwhile, at this time, the turned-on tenth transistor T10 does not perform any specific operation.

[0083] Then, while the third scanning signal GI is changed to a gate-off voltage (high level voltage), the second scanning signal GC is changed to a gate-on voltage (low level voltage). At this time, the gate-on voltage (high level voltage) of the second / first scanning signal GC2 is maintained.

[0084] As a result, the fourth transistor T4 is turned off, and the third transistor T3 and the fifth transistor T5 are turned on according to the second scan signal GC. At this time, the tenth transistor T10 and the eleventh transistor T11 remain turned on, and the ninth transistor T9 also remains turned on.

[0085] The reference voltage VREF is transmitted to the data node D_node through the turned-on fifth transistor T5 and the tenth transistor T10, and then the data node D_node, the second storage electrode, and the second electrode of the holding capacitor Chold are initialized to the reference voltage VREF. Due to the reference voltage VREF, the voltage of one terminal of each capacitor (the second electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold) is kept constant.

[0086] In addition, the operation for compensating the threshold voltage of the driving transistor T1 is performed by the turned-on third transistor T3 and the eleventh transistor T11. The first initialization voltage VINT applied to the gate node G_node is also transmitted to the second electrode of the driving transistor T1 through the turned-on third transistor T3 and the eleventh transistor T11. At this time, the driving transistor T1 has a diode connection structure in which the driving gate electrode and the second electrode are connected. The driving transistor T1 has a conducting state by the first initialization voltage VINT, and the driving voltage ELVDD transmitted to the first electrode of the driving transistor T1 is transmitted to the driving gate electrode of the driving transistor T1 and the first electrode of the storage capacitor Cst through the second electrode of the driving transistor T1, the third transistor T3 and the eleventh transistor T11. Therefore, the voltage of the driving gate electrode of the driving transistor T1 gradually rises from the first initialization voltage VINT, and then when it is lower than the driving voltage ELVDD by the threshold voltage of the driving transistor T1, the driving transistor T1 is turned off. When the driving transistor T1 is turned off, the voltage of the driving gate electrode is stored in the first storage electrode of the storage capacitor Cst, and the voltage of the first storage electrode of the storage capacitor Cst can be as shown in the following equation 1.

[0087] [Equation 1]

[0088] Vcst1=V ELVDD –Vth

[0089] Here, Vcst1 represents the voltage of the first storage electrode of the storage capacitor Cst, V ELVDD V represents the voltage value of the driving voltage ELVDD, and Vth represents the threshold voltage value of the driving transistor T1.

[0090] According to Equation 1, the threshold voltage value Vth, which may have a different value for each driving transistor T1, may be compensated.

[0091] According to the above compensation part, the second storage electrode of the storage capacitor Cst has the reference voltage VREF, and the first storage electrode has the voltage value of Equation 1.

[0092] The initialization and compensation part may be divided into a first part, in which the third scan signal GI is applied with a gate-on voltage (low level voltage) and the second scan signal GC is applied with a gate-off voltage (high level voltage), and a second part, in which the third scan signal GI is applied with a gate-off voltage (high level voltage) and the second scan signal GC is applied with a gate-on voltage (low level voltage). Figure 2 , the initialization and compensation part includes multiple alternating first and second parts. Figure 2 In the embodiment, the first part and the second part are both performed three times. However, according to an embodiment, the initialization and compensation part may include one first part and one second part.

[0093] exist Figure 2 In the embodiment of FIG. 5 , when the second scan signal GC and the third scan signal GI become the gate-off voltage (high level voltage), the initialization and compensation part ends and the writing part starts.

[0094] In the writing part, during 1H, a gate-off voltage (high level voltage) is applied as the second scan signal GC, the third scan signal GI and the second light-emitting signal EM2, and a gate-on voltage is applied as the second / first scan signal GC2 and the first light-emitting signal EM1, while the first scan signal GW becomes a gate-on voltage (low level voltage), and the data voltage VDATA enters the pixel.

[0095] In the writing section, the second transistor T2 applied with the first scan signal GW is turned on so that the data voltage VDATA is output to the second electrode of the second transistor T2 and transmitted to the second storage electrode of the storage capacitor Cst and the second electrode of the holding capacitor Chold through the tenth transistor T10.

[0096] In the writing part, the second electrode of the storage capacitor Cst changes from the reference voltage VREF as the voltage applied to the compensation part to the data voltage VDATA. At this time, the voltage value of the first electrode of the storage capacitor Cst changes in proportion to the voltage change amount of the second electrode of the storage capacitor Cst. That is, since the voltage change amount of the second electrode of the storage capacitor Cst is the voltage difference between the data voltage VDATA and the reference voltage VREF, the voltage of the first electrode of the storage capacitor Cst is additionally changed from the voltage value of equation 1 by a value proportional to the voltage difference between the data voltage VDATA and the reference voltage VREF. At this time, the voltage value of the first electrode of the storage capacitor Cst can be reduced. As the voltage value of the gate electrode of the driving transistor T1 decreases, the degree to which the driving transistor T1 is turned on is determined and the magnitude of the output current is determined.

[0097] exist Figure 2 In the embodiment, the gate-on voltage (low level voltage) of the first scanning signal GW may be maintained for 1H, 1H represents one horizontal period, and one horizontal period may correspond to one horizontal synchronization signal. 1H may mean the time when the gate-on voltage is applied to the scanning line of the next row after the gate-on voltage is applied to one scanning line. Figure 2 , it can be confirmed that the initialization and compensation part, the bias part and the light emitting part are longer than the writing part of 1H, and according to the embodiment, the compensation part can have a time of 3H or more, so that the threshold voltage of the driving transistor T1 can be fully compensated. That is, the pixel is divided into an initialization and compensation part for compensating the threshold voltage of the driving transistor T1 and a writing part for writing the data voltage VDATA. In the case of high-speed driving by extending the compensation time to three times the writing part 1H, even if the time of 1H is very short, a period of three times or more of 1H is ensured, so that the compensation time is not insufficient and sufficient compensation can be obtained during high-speed operation.

[0098] After that, the second / first scanning signal GC2 and the first light emitting signal EM1 become the gate-off voltage, the writing part ends and the biasing part starts.

[0099] The biasing part is a part where the fourth scan signal EB is applied at a gate-on voltage (low level voltage), and the anode of the light emitting diode LED is initialized to the second initialization voltage VAINT through the seventh transistor T7 applied with the fourth scan signal EB.

[0100] In addition, the bias voltage Vbias is applied to the first electrode of the driving transistor T1 through the eighth transistor T8 receiving the fourth scan signal EB. The characteristics of the driving transistor T1 applied with the bias voltage Vbias can be kept constant, and in particular, even if the separate data voltage VDATA is not input to the pixel, the driving transistor T1 can generate an output current constantly using the previously transmitted data voltage VDATA. This operation is used to maintain the characteristics of the driving transistor T1 during high-speed driving or low-speed driving, and can also reduce power consumption.

[0101] Reference Figure 2 , a period during which the fourth scan signal EB maintains the gate-on voltage (low-level voltage) may be 1H, and the fourth scan signal EB may apply the gate-on voltage (low-level voltage) multiple times. Figure 2 An embodiment in which the fourth scan signal EB applies the gate-on voltage (low-level voltage) three times is shown.

[0102] After that, the first light emitting signal EM1 and the second light emitting signal EM2 become the gate-on voltage (low level voltage), and the light emitting part starts. At this time, the driving transistor T1 receives the driving voltage ELVDD to generate an output current according to the voltage of the driving gate electrode (the voltage of the first storage electrode) so that the output current is output to the anode of the light emitting diode LED. As a result, the light emitting diode LED receives the output current of the driving transistor T1 and emits light.

[0103] So far, the circuit structure and operation of the pixel have been described.

[0104] The structure of the embodiments described below may have Figure 1 The circuit structure shown in FIG. Figure 2 However, the embodiments described below are not limited to Figure 1 The circuit structure or receiving Figure 2 The signal has the waveform shown in .

[0105] Reference Figure 3 and Figure 4 The layer structures of a pixel circuit unit and an anode in a pixel according to an embodiment are schematically described.

[0106] Figure 3 is a cross-sectional view of a light emitting display device according to an embodiment. Figure 4 is a view schematically showing a layer structure of a light emitting display device according to an embodiment.

[0107] Figure 3 The detailed cross-sectional structure is schematically shown. Figure 4 is to show the process sequence based on Figure 3 Schematic diagram of each layer.

[0108] Reference Figure 3 and Figure 4 , the stacked electrode BML is located on the substrate 110 .

[0109] The substrate 110 may include a rigid material such as glass or a flexible material such as plastic or polyimide. In the case of a flexible substrate, it may have a double-layer structure of polyimide and a barrier layer formed thereon of an inorganic insulating material.

[0110] The stacking electrode BML may be formed at a position overlapping with a channel of the driving transistor T1 in the subsequent first semiconductor layer ACT in a plan view, and is also referred to as a lower shielding layer.

[0111] The stacked electrode BML may also be stacked in a plane with one of other transistors including the first semiconductor layer ACT in addition to the driving transistor T1. The stacked electrode BML may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0112] On the substrate 110 and the stacked electrode BML, a buffer layer 111 is positioned to cover them.

[0113] The buffer layer 111 may be used to block the penetration of impurity elements from the lower portion during the crystallization process of the first semiconductor layer ACT, and may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiON x ) and the like. It includes a plurality of inorganic insulating layers.

[0114] The first semiconductor layer ACT formed of a silicon semiconductor (eg, a polycrystalline semiconductor) is located above the buffer layer 111. The first semiconductor layer ACT includes a channel 130 of a polycrystalline transistor including the driving transistor T1 and a first region and a second region located at both sides of the channel 130. Figure 1 In the embodiment, in addition to the driving transistor T1, the polycrystalline transistor may further include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9. In addition, both sides of the channel 130 of the polycrystalline transistor have regions having conductive properties through plasma treatment or doping process, and the regions may be used as the first electrode and the second electrode of the transistor.

[0115] The first gate insulating layer 141 may be located on the first semiconductor layer ACT. The first gate insulating layer 141 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiONx ) and the like, and may include multiple inorganic insulating layers.

[0116] The first gate conductive layer GAT1 including the gate electrode of the polycrystalline transistor may be located on the first gate insulating layer 141. The first gate conductive layer GAT1 includes the driving gate electrode 1151 of the driving transistor T1. The first gate conductive layer GAT1 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a plurality of layers.

[0117] After forming the first gate conductive layer GAT1, plasma treatment or a doping process may be performed to make the exposed region of the first semiconductor layer ACT conductive. That is, the first semiconductor layer ACT covered by the first gate conductive layer GAT1 is not conductive, and the portion of the first semiconductor layer ACT not covered by the first gate conductive layer GAT1 may have the same characteristics as the conductive layer.

[0118] The second gate insulating layer 142 may be located on the first gate conductive layer GAT1 and the first gate insulating layer 141. The second gate insulating layer 142 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiON x ) and the like, and may include multiple inorganic insulating layers.

[0119] The second gate conductive layer GAT2 including the second storage electrode Cst2 of the storage capacitor Cst may be located on the second gate insulating layer 142. The second gate conductive layer GAT2 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a plurality of layers. Here, the storage capacitor Cst may be formed by using the driving gate electrode 1151 of the driving transistor T1 and the second storage electrode Cst2 as two electrodes and using the second gate insulating layer 142 located therebetween as a dielectric layer.

[0120] The first interlayer insulating layer 151 may be located on the second gate conductive layer GAT2. The first interlayer insulating layer 151 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiON x ) and the like, and may include a plurality of inorganic insulating layers. In addition, according to the embodiment, the inorganic insulating material may be formed thick.

[0121] On the first interlayer insulating layer 151, an auxiliary conductive layer CMTL including a first holding electrode Chold1 of a holding capacitor Chold is positioned. The auxiliary conductive layer CMTL also includes an auxiliary electrode line CMTL-1 located below and overlapping the oxide transistor, the characteristics of the oxide transistor change according to the voltage applied to the auxiliary electrode line CMTL-1, and according to an embodiment, the auxiliary electrode line CMTL-1 may be formed as an auxiliary electrode having an island structure. The auxiliary conductive layer CMTL may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or multiple layers. Here, the holding capacitor Chold may be formed by using the second storage electrode Cst2 and the first holding electrode Chold1 as two electrodes and using the first interlayer insulating layer 151 located therebetween as a dielectric layer.

[0122] The second interlayer insulating layer 152 may be located on the auxiliary conductive layer CMTL. The second interlayer insulating layer 152 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiON x ) and the like, and may include a plurality of inorganic insulating layers. In addition, according to the embodiment, the inorganic insulating material may be formed thick.

[0123] An oxide semiconductor layer OACT including a channel ChO10 of an oxide transistor, a first region, and a second region may be located on the second interlayer insulating layer 152. Here, the channel ChO10 of the oxide transistor may be Figure 1 The channel of the tenth transistor T10 or the eleventh transistor T11 in the embodiment.

[0124] The third gate insulating layer 143 may be located on the oxide semiconductor layer OACT. The third gate insulating layer 143 may be located on the entire surface of the oxide semiconductor layer OACT and the second interlayer insulating layer 152. The third gate insulating layer 143 may include silicon oxide (SiO x )、Silicon Nitride(SiN x ), silicon oxynitride (SiON x ) and the like, and may include multiple inorganic insulating layers.

[0125] The third gate conductive layer GAT3 including the second / first scan line 167 including the gate electrode of the oxide transistor may be located on the third gate insulating layer 143. The gate electrode of the oxide transistor may overlap with the channel. The third gate conductive layer GAT3 may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti), and may be composed of a single layer or a plurality of layers.

[0126] After forming the third gate conductive layer GAT3, the exposed region of the oxide transistor can be made conductive by performing a plasma treatment or a doping process. That is, the channel ChO10 of the oxide transistor covered by the third gate conductive layer GAT3 is not conductive, and the portion of the oxide transistor not covered by the third gate conductive layer GAT3 can have the same characteristics as the conductive layer.

[0127] The third interlayer insulating layer 153 may be located on the third gate conductive layer GAT3. The third interlayer insulating layer 153 may have a single layer or a multi-layer structure. The third interlayer insulating layer 153 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) and may include an organic material according to an embodiment. According to an embodiment, the third interlayer insulating layer 153 may also be formed as a single layer or a multilayer.

[0128] On the third interlayer insulating layer 153, a first data conductive layer SD1 may be positioned, the first data conductive layer SD1 including a plurality of connection electrodes SD1ce and SD1ano that may be connected to the first and second regions of each of the polycrystalline transistor and the oxide transistor. Among the plurality of connection electrodes located in the first data conductive layer SD1, the first anode connection electrode SD1ano electrically connects one of the polycrystalline transistors to the anode Anode, and the connection electrode SD1ce connects the second / first scan line 167 including the gate electrode of the oxide transistor and the auxiliary electrode line CMTL-1 located under the oxide transistor. According to an embodiment, the first data conductive layer SD1 may further include various connection electrodes, and may be omitted. Figure 3 At least one of the connection electrodes shown in . The first data conductive layer SD1 may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or a multilayer.

[0129] The first organic layer 181 may be located on the first data conductive layer SD1. The first organic layer 181 may be an organic insulator including an organic material, and the organic material may include one or more materials selected from the group consisting of polyimide, polyamide, acryl resin, benzocyclobutene, and phenolic resin.

[0130] On the first organic layer 181, a second data conductive layer SD2 including a second anode connection electrode SD2ano may be positioned. The second data conductive layer SD2 may further include a data line or a driving voltage line. The second anode connection electrode SD2ano electrically connects one of the polycrystalline transistors with the anode Anode located on the first data conductive layer SD1 and the first anode connection electrode SD1ano. The second data conductive layer SD2 may include a metal or a metal alloy such as aluminum (Al), copper (Cu), molybdenum (Mo), or titanium (Ti), and may be composed of a single layer or multiple layers.

[0131] The second organic layer 182 and the third organic layer 183 are located on the second data conductive layer SD2, and an opening is formed in the second organic layer 182 and the third organic layer 183 so that the second anode connection electrode SD2ano and the anode Anode are electrically connected. The second organic layer 182 and the third organic layer 183 may include one or more materials selected from the group consisting of polyimide, polyamide, acryl resin, benzocyclobutene, and phenolic resin. According to an embodiment, the third organic layer 183 may be omitted.

[0132] On the third organic layer 183, an anode Anode constituting a light emitting diode is positioned. The anode Anode may be composed of a single layer including a transparent conductive oxide film or a metal material or a multilayer including a transparent conductive oxide film and / or a metal material. The transparent conductive oxide layer may include indium tin oxide (ITO), polycrystalline-ITO, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). The metal material may include silver (Ag), molybdenum (Mo), copper (Cu), gold (Au), and aluminum (Al).

[0133] On the anode Anode, a pixel defining layer 380 covering at least a portion of the anode Anode while having an opening OP exposing the anode Anode may be positioned. The pixel defining layer 380 may be a black pixel defining layer formed of an organic material having a black color so that light applied from the outside is not reflected back to the outside, and according to an embodiment, it may be formed of a transparent organic material. A spacer (not shown) may be located above the pixel defining layer 380, and the spacer may be formed of the same material as the pixel defining layer 380.

[0134] Figure 3 and Figure 4 The structure of the pixel defining layer 380 and its lower portion is shown, but according to an embodiment, a structure similar to the following may be provided.

[0135] On the anode Anode and the pixel defining layer 380, a functional layer and a cathode are sequentially formed, and the functional layer and the cathode may be located in the entire area in the display area. The light-emitting layer may be located between the functional layers, and the light-emitting layer may be located only within the opening OP of the pixel defining layer 380. Hereinafter, the combination of the functional layer and the light-emitting layer may be referred to as an intermediate layer. The functional layer may include at least one of the auxiliary layers such as an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer, the hole injection layer and the hole transport layer may be located below the light-emitting layer, and the electron transport layer and the electron injection layer may be located on the light-emitting layer.

[0136] The encapsulation layer is located on the cathode. The encapsulation layer may include at least one inorganic film and at least one organic layer, and according to one embodiment, may have a three-layer structure including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer may be used to protect the light-emitting layer from moisture or oxygen that may flow in from the outside. According to an embodiment, the encapsulation layer may include a structure in which an inorganic layer and an organic layer are further stacked in sequence.

[0137] According to an embodiment, a plurality of sensing electrodes for touch sensing and a sensing insulating layer may be located on the encapsulation layer.

[0138] In addition, a light blocking layer and a color filter layer may be located on the encapsulation layer. According to an embodiment, a color conversion layer may be formed instead of the color filter layer. The color conversion layer may include quantum dots.

[0139] In the above, the layer structures of the entire light emitting display device and pixels are described.

[0140] In the following, reference is made to Figure 5 The planar structures of conductive layers and semiconductor layers excluding some conductive layers are described in detail.

[0141] Figure 5 is a view showing a planar structure of some conductive layers and anodes among a lower panel layer of a light emitting display device according to an embodiment.

[0142] Figure 5 Not shown included Figure 4 The substrate 110, the buffer layer 111 and each insulating layer (the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 151, the second interlayer insulating layer 152, the third gate insulating layer 143, the third interlayer insulating layer 153, the first organic layer 181, the second organic layer 182, the third organic layer 183) among the layers in the figure are shown. In addition, the stacked electrode BML, the first semiconductor layer ACT, the oxide semiconductor layer OACT and the pixel defining layer 380 are not shown. Therefore, Figure 5A first gate conductive layer GAT1, a second gate conductive layer GAT2, an auxiliary conductive layer CMTL, a third gate conductive layer GAT3, a first data conductive layer SD1, a second data conductive layer SD2, and anodes Anode1 and Anode2 are shown. Figure 5 , only the conductive layers as above are shown in order to omit the stacked electrode BML, the first semiconductor layer ACT, and the oxide semiconductor layer OACT because they have little influence in the step of disposing each conductive layer so that the anodes Anode1 and Anode2 have a flat characteristic.

[0143] Specifically, including Figure 5 Each part shown in the embodiment is Figure 5 The conductive layers are summarized as follows.

[0144] The first gate conductive layer GAT1 includes a driving gate electrode 1151 and a third scan line 163, the second gate conductive layer GAT2 includes a repair line RPL, a first initialization voltage line 173, a second storage electrode Cst2 and a lower fourth scan line 166a, the auxiliary conductive layer CMTL includes a lower second initialization voltage line 175a and a first holding electrode Chold1, the third gate conductive layer GAT3 includes an upper second initialization voltage line 175b, a first scan line 161 and a second / first scan line 167, the first data conductive layer SD1 includes a second scan line 162, a first light emitting signal line 164, a second light emitting signal line 165 and an upper fourth scan line 166b, and the second data conductive layer SD2 includes a data line 171, a driving voltage line 172 and a reference voltage line 174.

[0145] Among them, the data line 171 , the driving voltage line 172 , and the reference voltage line 174 included in the second data conductive layer SD2 extend in the second direction DR2 .

[0146] On the other hand, the third scan line 163 included in the first gate conductive layer GAT1, the repair line RPL included in the second gate conductive layer GAT2, the first initialization voltage line 173 and the lower fourth scan line 166a, the lower second initialization voltage line 175a included in the auxiliary conductive layer CMTL, the upper second initialization voltage line 175b included in the third gate conductive layer GAT3, the first scan line 161 and the second / first scan line 167, and the second scan line 162, the first light emitting signal line 164, the second light emitting signal line 165 and the upper fourth scan line 166b included in the first data conductive layer SD1 extend in the first direction DR1.

[0147] In addition, the driving gate electrode 1151 included in the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2, and the first holding electrode Chold1 included in the auxiliary conductive layer CMTL overlap each other and each has an island structure. The driving gate electrode 1151, the second storage electrode Cst2, and the first holding electrode Chold1 overlap each other on a plane to form a storage capacitor Cst and a holding capacitor Chold. Specifically, the driving gate electrode 1151 and the second storage electrode Cst2 may be two electrodes of the storage capacitor Cst, and the second storage electrode Cst2 and the first holding electrode Chold1 may be two electrodes of the holding capacitor Chold. Therefore, the driving gate electrode 1151 may be used as one electrode of the storage capacitor Cst and play the role of the gate electrode of the driving transistor T1, and the second storage electrode Cst2 may also play the role of one electrode of the holding capacitor Chold and the role of the other electrode of the storage capacitor Cst.

[0148] exist Figure 5 In the embodiment, the repair line RPL is included in the second gate conductive layer GAT2, but according to an embodiment, the repair line RPL may not be included in an embodiment in which the repair line RPL is not included; and instead, another wiring (for example, a driving low voltage line 179 or a bias voltage line 176) may be located therein.

[0149] Figure 5 Two anodes Anode1 and Anode2 are shown.

[0150] exist Figure 5 In the figure, the first anode Anode1 overlaps in plane with the driving gate electrode 1151 included in the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2, and the first holding electrode Chold1 included in the auxiliary conductive layer CMTL. That is, the first anode Anode1 overlaps with three conductive layers of the first gate conductive layer GAT1, the second gate conductive layer GAT2, and the auxiliary conductive layer CMTL except for the stacking electrode BML, the first semiconductor layer ACT, and the oxide semiconductor layer OACT. Hereinafter, the three conductive layers of the first gate conductive layer GAT1, the second gate conductive layer GAT2, and the auxiliary conductive layer CMTL may also be referred to as capacitor three layers. In addition, the first anode Anode1 and the second anode Anode2 overlap with the driving voltage line 172 located in the second data conductive layer SD2. Refer to Figure 5 The entire first anode Anode1 is located on the capacitor layer 3 and the driving voltage line 172, giving it an overall flat characteristic.

[0151] like Figure 5As shown in FIG. 1 , the second anode Anode 2 overlaps the first and second groups of triple overlapping wirings extending in the first direction DR1. The second anode Anode 2 also overlaps the first and second groups of triple overlapping wirings located in the second data conductive layer SD2 ( Figure 4 The driving voltage line 172 is overlapped with the driving voltage line 172 shown in FIG. As described above, the driving voltage line 172 is also overlapped with the first anode Anode1.

[0152] Specifically, the triple overlapped wiring included in the first group includes the third scan line 163 included in the first gate conductive layer GAT1, the first initialization voltage line 173 included in the second gate conductive layer GAT2, and the first scan line 161 included in the third gate conductive layer GAT3, and the triple overlapped wiring included in the first group overlaps a portion of the second anode Anode2. In addition, the triple overlapped wiring included in the second group includes the repair line RPL included in the second gate conductive layer GAT2, the lower second initialization voltage line 175a included in the auxiliary conductive layer CMTL, and the upper second initialization voltage line 175b included in the third gate conductive layer GAT3, and the triple overlapped wiring included in the second group overlaps a portion of the remaining portion of the second anode Anode2. Therefore, referring to Figure 5 Due to the two groups of triple overlapping wirings, the second anode Anode 2 can also have an overall flat characteristic. Hereinafter, the three triple overlapping wirings included in the second group are also referred to as the first overlapping wiring, the second overlapping wiring, and the third overlapping wiring. The three triple overlapping wirings included in the first group can also be referred to as the fourth overlapping wiring, the fifth overlapping wiring, and the sixth overlapping wiring.

[0153] Although each of the first anode Anode1 and the second anode Anode2 is stacked with different three conductive layers, since there is no significant difference in the thickness of the conductive layers under the first anode Anode1 and the second anode Anode2, and the three organic layers 181, 182 and 183 and the second data conductive layer SD2 are generally located under both the anodes Anode1 and Anode2, the organic layers 182 / 183 can be at the same height, thereby achieving flatness.

[0154] Reference Figure 6 The thickness and flatness characteristics of the first anode Anode1 and the second anode Anode2 are described in more detail.

[0155] Figure 6 is based on Figure 5 A cross-sectional view of a light-emitting display device of an embodiment.

[0156] Figure 6 and Figure 3 The cross-sectional structure corresponds to Figure 3Differently, the underlying structures of the first anode Anode 1 and the second anode Anode 2 are shown in detail.

[0157] Reference Figure 6 , the lower layer structure of the first anode Anode1 is sequentially stacked from the substrate 110 as shown below.

[0158] The stacked electrode BML is located on the substrate 110, the buffer layer 111 is located on the stacked electrode BML, the first semiconductor layer ACT is located on the buffer layer 111, the first gate insulating layer 141 is located on the first semiconductor layer ACT, the driving gate electrode 1151 included in the first gate conductive layer GAT1 is located on the first gate insulating layer 141, the second gate insulating layer 142 is located on the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2 is located on the second gate insulating layer 142, and the first interlayer insulating layer 151 is located on the second gate conductive layer GAT 2, the first holding electrode Chold1 included in the auxiliary conductive layer CMTL is located on the first interlayer insulating layer 151, the second interlayer insulating layer 152 is located on the auxiliary conductive layer CMTL, the third gate insulating layer 143, the third interlayer insulating layer 153 and the first organic layer 181 are sequentially located on the second interlayer insulating layer 152, the driving voltage line 172 set in the second data conductive layer SD2 is located on the first organic layer 181, the second organic layer 182 and the third organic layer 183 are sequentially located on the second data conductive layer SD2, and the first anode Anode1 is located on the third organic layer 183.

[0159] Meanwhile, the lower structure of the second anode Anode2 is as follows.

[0160] The buffer layer 111 is located on the substrate 110, the first gate insulating layer 141 is located on the buffer layer 111, the third scan line 163 included in the first gate conductive layer GAT1 is located on the first gate insulating layer 141, the second gate insulating layer 142 is located on the first gate conductive layer GAT1, the first initialization voltage line 173 and the repair line RPL included in the second gate conductive layer GAT2 are located on the second gate insulating layer 142, the first interlayer insulating layer 151 is located on the second gate conductive layer GAT2, the lower second initialization voltage line 175a included in the auxiliary conductive layer CMTL is located on the first interlayer insulating layer 151, and the second interlayer insulating layer 152 is located on the On the auxiliary conductive layer CMTL, the third gate insulating layer 143 is located on the second interlayer insulating layer 152, the first scan line 161 and the upper second initialization voltage line 175b included in the third gate conductive layer GAT3 are located on the third gate insulating layer 143, the third interlayer insulating layer 153 is located on the third gate conductive layer GAT3, the first organic layer 181 is located on the third interlayer insulating layer 153, the driving voltage line 172 included in the second data conductive layer SD2 is located on the first organic layer 181, the second organic layer 182 and the third organic layer 183 are sequentially located on the second data conductive layer SD2, and the second anode Anode2 is located on the third organic layer 183.

[0161] Since only three layers of capacitors are located below the first anode Anode1, the layer structure is simple, and the first anode Anode1 can be flat as a whole. On the other hand, because two groups of triple overlapping wirings are located below the second anode Anode2, the layer structure is slightly more complicated. Specifically, among the two groups of triple overlapping wirings located below the second anode Anode2, the triple overlapping wirings included in the first group may be composed of a third scan line 163 included in the first gate conductive layer GAT1, a first initialization voltage line 173 included in the second gate conductive layer GAT2, and a first scan line 161 included in the third gate conductive layer GAT3, and the triple overlapping wirings included in the second group may be composed of a repair line RPL included in the second gate conductive layer GAT2, a lower second initialization voltage line 175a included in the auxiliary conductive layer CMTL, and an upper second initialization voltage line 175b included in the third gate conductive layer GAT3. In addition, a portion of the second anode Anode 2 may be formed at the same height as the first anode Anode 1 through the triple overlapped wiring included in the first group, and a portion of the remaining portion of the second anode Anode 2 may be formed at the same height as the first anode Anode 1 through the triple overlapped wiring included in the second group. Figure 6The driving voltage line 172 in the second data conductive layer) and the organic layers 181, 182 and 183 located above and below the second data conductive layer, so the portion of the second anode Anode2 that does not overlap with the two sets of triple overlapped wirings on the plane can be formed at the same height as the first anode Anode1. In addition, since the second data conductive layer (refer to Figure 6 The second anode Anode 2 may have an overall flat characteristic although it overlaps two sets of triple overlapped wirings.

[0162] Now I will explain Figure 7 and Figure 8 , and will refer to Figure 7 and Figure 8 Example description Figure 5 and Figure 6 Features of an embodiment.

[0163] Figure 7 is a plan view showing a plan structure of some conductive layers and anodes among a lower panel layer of a light-emitting display device according to a comparative example.

[0164] First, through Figure 7 Describes the planar structure of the comparative example, and focuses on Figure 5 Different part descriptions Figure 7 A comparison example in .

[0165] exist Figure 7 In the comparative example, the first anode Anode1 overlaps the capacitor layer 3 and the driving voltage line 172 . Figure 5 The first anode Anode1 and Figure 7 There is no difference in the height and flatness of the first anode Anode1 in FIG. Figure 7 A comparison example with Figure 5 The difference of the embodiment is that the second anode Anode2 has a structure that does not overlap with the triple overlapped wiring. Figure 7 In the comparative example, the second anode Anode2 and the first anode Anode1 will not have the same height.

[0166] Included in Figure 5 Each of the two sets of triple overlapped wirings in is formed by a subsequent conductive layer at a position that does not overlap the second anode Anode2.

[0167] In a plan view, the first initialization voltage line 173, the third scan line 163, and the first scan line 161 are located at the second direction DR2 side of the second anode Anode 2 instead of under the second anode Anode 2. Here, the first initialization voltage line 173 may be formed of the second gate conductive layer GAT2, and the third scan line 163 and the first scan line 161 may be formed of the first data conductive layer SD1.

[0168] On the other hand, Figure 7 In the embodiment, the repair line RPL and the second initialization voltage line 175 are located on the opposite direction side of the second direction DR2 of the first anode Anode1, rather than under the first anode Anode1. Here, the repair line RPL may be formed by the second gate conductive layer GAT2, and the second initialization voltage line 175 may be formed by a single layer of the third gate conductive layer GAT3. According to the embodiment, even in the comparative example, the second initialization voltage line 175 may be formed as a lower and upper double-layer structure. In addition, as Figure 7 As shown in FIG. 1 , the repair line RPL and the second initialization voltage line 175 may extend in the first direction DR1 and be spaced apart from the first initialization voltage line 173 in the second direction DR2 .

[0169] Reference Figure 7 , since the first anode Anode1 and the second anode Anode2 have a constant stacking structure, each can have a flat characteristic. Figure 7 , only the driving voltage line 172 located in the second data conductive layer SD2 is located below the second anode Anode2 as a conductive layer, but the first anode Anode1 is also triple-stacked with the capacitor in addition to the driving voltage line 172. Therefore, the first anode Anode1 can be formed at a higher position than the second anode Anode2.

[0170] pass Figure 8 The heights of the first anode Anode1 and the second anode Anode2 are described in more detail.

[0171] Figure 8 is based on Figure 7 A cross-sectional view of a light-emitting display device of an embodiment.

[0172] exist Figure 8 , the height difference between the first anode Anode1 and the second anode Anode2 is clearly shown.

[0173] exist Figure 8 In the comparative example, the height of the first anode Anode1 is Figure 6 The height of the embodiment is the same, but as described below, Figure 8 The lower layer structure of the second anode Anode 2 in the comparative example is Figure 6The lower layer structure of the second anode Anode 2 in the embodiment is different. More specifically, Figure 6 Compared with the embodiment of FIG. 1 , the height of the second anode Anode 2 can be low.

[0174] exist Figure 8 In the comparative example, the lower layer structure of the second anode Anode2 is as follows.

[0175] The buffer layer 111 is located on the substrate 110, the first gate insulating layer 141 is located on the buffer layer 111, the second gate insulating layer 142 is located on the first gate insulating layer 141, the first interlayer insulating layer 151 is located on the second gate insulating layer 142, the second interlayer insulating layer 152 is located on the first interlayer insulating layer 151, the third gate insulating layer 143 is located on the second interlayer insulating layer 152, the third interlayer insulating layer 153 is located on the third gate insulating layer 143, the first organic layer 181 is located on the third interlayer insulating layer 153, the driving voltage line 172 included in the second data conductive layer SD2 is located on the first organic layer 181, the second organic layer 182 and the third organic layer 183 are sequentially located on the second data conductive layer SD2, and the second anode Anode2 is located on the third organic layer 183.

[0176] However, in Figure 8 In the comparative example of , the conductive layer is not located under the second anode Anode 2, so that it is formed to have a relatively low height.

[0177] like Figure 8 As shown in FIG. 1 , if the first anode Anode 1 and the second anode Anode 2 are located at different heights, when external light is incident on and reflected from each of the two anodes Anode 1 and Anode 2 , a reflection color band is generated due to the different lengths of the reflection paths of the external light. The reflection color band can be visually recognized by the user, resulting in degradation of display quality.

[0178] However, if Figure 5 and Figure 6 As shown in , if the first anode Anode1 and the second anode Anode2 having flat characteristics are formed at the same height, even if external light is reflected from each of the two anodes Anode1 and Anode2, there is no difference in the reflection path, so that no reflection color bands appear, and the display quality can have the advantage of being improved.

[0179] In the above, an embodiment is described that overcomes the problem of reflection color banding caused by the difference in reflection paths between two anodes Anode1 and Anode2. Hereinafter, an embodiment that overcomes the problem of reflection color banding that may occur due to a step in one anode will be described.

[0180] Reference Fig. 9 and Fig.10Another embodiment is described in detail. First, by Fig. 9 Describe the planar structure.

[0181] Fig. 9 It is also a view showing a planar structure of some conductive layers and anodes in a lower panel layer of a light-emitting display device according to another embodiment.

[0182] Fig. 9 and Figure 5 Correspondingly, the substrate 110, the buffer layer 111 and the Figure 4 Each insulating layer among the layers in (the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 151, the second interlayer insulating layer 152, the third gate insulating layer 143, the third interlayer insulating layer 153, the first organic layer 181, the second organic layer 182 and the third organic layer 183); in addition, the stacked electrode BML, the first semiconductor layer ACT, the oxide semiconductor layer OACT and the pixel defining layer 380 are not shown. Then, Fig. 9 A first gate conductive layer GAT1, a second gate conductive layer GAT2, an auxiliary conductive layer CMTL, a third gate conductive layer GAT3, a first data conductive layer SD1, a second data conductive layer SD2, and an anode Anode 1 are shown. Fig. 9 , only the conductive layers as described above are shown in order to omit the stacked electrode BML, the first semiconductor layer ACT, and the oxide semiconductor layer OACT because they have little influence in the step of disposing each conductive layer so that the anode Anode1 has a flat characteristic.

[0183] Specifically, the following are Fig. 9 An overview of which conductive layer each part is included in is shown in the embodiments.

[0184] The first gate conductive layer GAT1 includes a driving gate electrode 1151 and a lower first initialization voltage line 173a, the second gate conductive layer GAT2 includes a repair line RPL, an upper first initialization voltage line 173b, a second storage electrode Cst2 and a lower fourth scan line 166a, the auxiliary conductive layer CMTL includes a first holding electrode Chold1, the third gate conductive layer GAT3 includes a second initialization voltage line 175 and a second / first scan line 167, the first data conductive layer SD1 includes a first scan line 161, a second scan line 162, a third scan line 163, a first light emitting signal line 164, a second light emitting signal line 165 and an upper fourth scan line 166b, and the second data conductive layer SD2 includes a data line 171, a driving voltage line 172 and a reference voltage line 174.

[0185] Among them, the data line 171 , the driving voltage line 172 , and the reference voltage line 174 included in the second data conductive layer SD2 extend in the second direction DR2 .

[0186] On the other hand, the lower first initialization voltage line 173a included in the first gate conductive layer GAT1, the repair line RPL included in the second gate conductive layer GAT2, the upper first initialization voltage line 173b and the lower fourth scan line 166a, the second initialization voltage line 175 and the second / first scan line 167 included in the third gate conductive layer GAT3, and the first scan line 161, the second scan line 162, the third scan line 163, the first light emitting signal line 164, the second light emitting signal line 165 and the upper fourth scan line 166b included in the first data conductive layer SD1 extend in the first direction DR1.

[0187] In addition, the driving gate electrode 1151 included in the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2, and the first holding electrode Chold1 included in the auxiliary conductive layer CMTL overlap each other and each have an island structure, and the storage capacitor Cst and the holding capacitor Chold are as described above.

[0188] exist Fig. 9 In the embodiment, the repair line RPL is included in the second gate conductive layer GAT2. According to another embodiment, the repair line RPL may not be included, and another wiring (eg, the driving low voltage line 179 or the bias voltage line 176) may be located instead of the repair line RPL.

[0189] Fig. 9 Only one anode Anode1 is shown.

[0190] exist Fig. 9 In the figure, a portion of the first anode Anode1 is overlapped with the capacitor three-layer on a plane, and the capacitor three-layer is composed of a driving gate electrode 1151 included in a first gate conductive layer GAT1 on a plane, a second storage electrode Cst2 included in a second gate conductive layer GAT2, and a first holding electrode Chold1 included in an auxiliary conductive layer CMTL. Fig. 9 The stacking of the stacking electrode BML, the first semiconductor layer ACT and the oxide semiconductor layer OACT is not shown; in addition, the first anode Anode1 is overlapped with the driving voltage line 172 whose entirety is located in the second data conductive layer SD2.

[0191] Reference Fig. 9, another part of the first anode Anode1 is not triple-stacked with the capacitor. Instead, it is overlapped on a plane with a triple-stacked wiring, which is composed of a lower first initialization voltage line 173a located in the first gate conductive layer GAT1, an upper first initialization voltage line 173b included in the second gate conductive layer GAT2, and a second / first scan line 167 included in the third gate conductive layer GAT3, and the lower first initialization voltage line 173a and the upper first initialization voltage line 173b can receive the same voltage or signal. Fig. 9 In the embodiment of the present invention, the portion of the first anode Anode 1 overlapping the triple overlap wiring may be a portion including one end of the first anode Anode 1, and it may be a portion including an end portion in the second direction DR2 of the first anode Anode 1. The portion of the first anode Anode 1 overlapping the triple overlap wiring also overlaps the driving voltage line 172 located in the second data conductive layer SD2.

[0192] As described above, the first anode Anode 1 may be divided into a portion overlapping with the capacitor triple layer and a portion overlapping with the triple overlapping wiring. Here, since the entire first anode Anode 1 overlaps with the driving voltage line 172 and is located on the organic layers 181, 182, and 183, although the conductive layer located below the organic layers 181, 182, and 183 and overlapping with the first anode Anode 1 on the plane is different, the first anode Anode 1 may be formed to have an overall constant height and have a flat characteristic.

[0193] pass Fig.10 The height and flatness characteristics of the first anode Anode1 are described in more detail.

[0194] Fig.10 is based on Fig. 9 A cross-sectional view of a light-emitting display device of an embodiment.

[0195] Fig.10 Depicted with Figure 3 Similar cross-sectional structure, but showing the Figure 3 Different angles, which are: showing the underlying structure of the first anode Anode1 in detail.

[0196] Reference Fig.10 , the lower layer structure of the first anode Anode1 is sequentially stacked from the substrate 110 as shown below.

[0197] The stacked electrode BML is located on the substrate 110, the buffer layer 111 is located on the stacked electrode BML, the first semiconductor layer ACT is located on the buffer layer 111, the first gate insulating layer 141 is located on the first semiconductor layer ACT, the driving gate electrode 1151 included in the first gate conductive layer GAT1 and the lower first initialization voltage line 173a are located on the first gate insulating layer 141, the second gate insulating layer 142 is located on the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2 and the upper first initialization voltage line 173b are located on the second gate insulating layer 142, the first interlayer insulating layer 151 is located on the second gate conductive layer GAT2, and the auxiliary conductive layer CM is included in the auxiliary conductive layer CM. The first holding electrode Chold1 in TL is located on the first interlayer insulating layer 151, the second interlayer insulating layer 152 is located on the auxiliary conductive layer CMTL, the third gate insulating layer 143 is located on the second interlayer insulating layer 152, the second / first scanning line 167 included in the third gate conductive layer GAT3 is located on the third gate insulating layer 143, the third interlayer insulating layer 153 and the first organic layer 181 are sequentially located on the third gate conductive layer GAT3, the driving voltage line 172 located in the second data conductive layer SD2 is located on the first organic layer 181, the second organic layer 182 and the third organic layer 183 are sequentially located on the second data conductive layer SD2, and the first anode Anode1 is located on the third organic layer 183.

[0198] like Fig.10 As shown in FIG. 1 , a portion of the first anode Anode 1 is overlapped with the capacitor trilayer, but another portion is overlapped with a triple overlap wiring composed of a lower first initialization voltage line 173a located in the first gate conductive layer GAT1, an upper first initialization voltage line 173b included in the second gate conductive layer GAT2, and a second / first scan line 167 included in the third gate conductive layer GAT3. However, due to the organic layers 181, 182, and 183 located on top of the capacitor trilayer and the triple overlap wiring, and the driving voltage line 172 located in the second data conductive layer SD2, the first anode Anode 1 can be formed without a step and can have a flat characteristic.

[0199] We will now describe Fig.11 and Fig.12 Another comparative example of Fig.11 and Fig.12 describe Fig. 9 and Fig.10 Features of an embodiment.

[0200] Fig.11 is a view showing a planar structure of some conductive layers and anodes among a lower panel layer of a light emitting display device according to another comparative example.

[0201] First, through Fig.11 Describes the planar structure of another comparative example, and focuses on Fig. 9 Different parts to describe Fig.11 Description of the comparative example in .

[0202] exist Fig.11 In the comparative example, a portion of the first anode Anode1 is as shown in Fig. 9 In the middle, the capacitor three layers and the driving voltage line 172 are overlapped.

[0203] However, with Fig. 9 Differently, the rest of the first anode Anode 1 has a structure that is not overlapped with the triple overlapped wiring. Fig.11 In the comparative example, the remaining portion of the first anode Anode1 has a structure overlapping with the second / first scan line 167 located in the third gate conductive layer GAT3 and the first light emitting signal line 164 located in the first data conductive layer SD1, and the second / first scan line 167 and the first light emitting signal line 164 are positioned on a plane to be separated from each other without overlapping each other.

[0204] In addition, Fig.11 In the comparison example, Fig. 9 Differently, the first initialization voltage line 173 is formed of only the second gate conductive layer GAT2, has a single-layer structure, and is located in a portion that does not overlap the first anode Anode 1.

[0205] Fig.11 A comparative example can have Fig.12 Similar cross-sectional structure.

[0206] Fig.12 is based on Fig.11 A cross-sectional view of a light-emitting display device of an embodiment.

[0207] exist Fig.12 , the first anode Anode 1 is not formed to be flat as a whole, and a structure having a step is clearly shown.

[0208] exist Fig.12 In the comparative example of FIG. 1 , the first anode Anode 1 has a stepped structure. Since the conductive layer under the first organic layer 181 overlapped with the first anode Anode 1 does not have a flat top surface, the first anode Anode 1 partially has a step.

[0209] The stacking electrode BML is located on the substrate 110, the buffer layer 111 is located on the stacking electrode BML, the first semiconductor layer ACT is located on the buffer layer 111, the first gate insulating layer 141 is located on the first semiconductor layer ACT, the driving gate electrode 1151 included in the first gate conductive layer GAT1 is located on the first gate insulating layer 141, the second gate insulating layer 142 is located on the first gate conductive layer GAT1, the second storage electrode Cst2 included in the second gate conductive layer GAT2 is located on the second gate insulating layer 142, the first interlayer insulating layer 151 is located on the second gate conductive layer GAT2, the first holding electrode Chold1 included in the auxiliary conductive layer CMTL is located on the first interlayer insulating layer 151, and the second interlayer insulating layer 152 The third interlayer insulating layer 153 is located on the second interlayer insulating layer 152, the second / first scan line 167 included in the third gate conductive layer GAT3 is located on the third gate insulating layer 143, the third interlayer insulating layer 153 is located on the third gate conductive layer GAT3, the first light emitting signal line 164 included in the first data conductive layer SD1 is located on the third interlayer insulating layer 153, the first organic layer 181 is located on the first data conductive layer SD1, the driving voltage line 172 included in the second data conductive layer SD2 is located on the first organic layer 181, the second organic layer 182 and the third organic layer 183 are sequentially located on the second data conductive layer SD2, and the first anode Anode 1 is located on the third organic layer 183. Here, the second / first scan line 167 and the first light emitting signal line 164 are positioned so as not to overlap each other.

[0210] That is to say, Fig.12 In the comparative example of FIG. 1 , a portion of the first anode Anode1 overlaps the capacitor layer, a portion of the remaining portion overlaps the second / first scanning line 167 located in the third gate conductive layer GAT3, and another portion of the remaining portion overlaps the first light emitting signal line 164 located in the first data conductive layer SD1. Fig.12 As shown in FIG. 1 , even if the first anode Anode 1 overlaps the driving voltage line 172 located in the second data conductive layer SD2 and there are organic layers 181, 182, and 183, a step also exists in the first anode Anode 1 because a step is generated in the conductive layer located below the first organic layer 181. Therefore, according to Fig.11 and Fig.12 The first anode Anode1 of the comparative example in FIG. 4 does not have a flat structure but has a stepped structure.

[0211] If Fig.11 and Fig.12In the embodiment of the present invention, when external light is incident on the first anode Anode 1 and reflected, the length of the reflection path of the external light differs according to the point where the reflection occurs on the first anode Anode 1. As a result, a reflection color band is generated. Such a reflection color band can be visually recognized by the user, resulting in deterioration of display quality.

[0212] However, in Fig. 9 and Fig.10 In the embodiment, since the first anode Anode 1 has a flat characteristic, the reflection path has almost no difference no matter which point on the first anode Anode 1 the external light is reflected from. Avoiding a large variation in the length of the reflection path prevents reflection color bands and maintains high display quality.

[0213] In conclusion, Figure 5 and Figure 6 The embodiment in which the two anodes Anode1 and Anode2 are formed flat with a constant thickness has been described. Fig. 9 and Fig.10 An embodiment is disclosed in which the first anode Anode 1 is formed flat with a constant thickness without a step.

[0214] When one pixel has two capacitors and each of the capacitors has a three-layer structure formed by stacking three electrodes on a plane, at least a portion of the anode is stacked with the capacitor three layers on a plane. This structure generates a step in the anode. In order to form the anode to be flat and have a constant thickness, the portion of the anode that is not stacked with the capacitor three layers or a separate anode may also be formed to stack with three conductive layers (triplet stacking wiring). In this way, the portion of the anode above the capacitor three layers and the portion of the anode above the three conductive layers are at about the same height, thereby avoiding steps in the anode.

[0215] However, according to an embodiment, since the organic layer may be located below the anode and the second data conductive layer SD2 may also be co-located, the overlay wiring may be formed using less than three conductive layers, and in the following, referring to Fig.13 An embodiment in which the stacked wiring is formed of two conductive layers is schematically described.

[0216] Fig.13 The structures of the comparative example and one embodiment are schematically compared. Fig.13 (A) schematically shows a comparative example, Fig.13 (B) in the figure schematically shows the disclosed embodiment.

[0217] exist Fig.13 In FIG. 1 , unlike the previous drawings, anodes Anode1 and Anode2 are shown, and the three layers of capacitor Cst / Chold are briefly shown. In addition, Fig.13(B) in FIG. 4 shows double overlapping wirings SL1 and SL2. Fig.13 , the capacitor three-layer Cst / Chold is shown as a single layer, but actually, as described above, the capacitor three-layer Cst / Chold has a structure in which three conductive layers are stacked.

[0218] exist Fig.13 In the comparative example (A) in FIG. 1 , since the entire first anode Anode 1 is on the capacitor three layers Cst / Chold, the first anode Anode 1 can have a flat structure. However, a portion of the second anode Anode 2 is on the capacitor three layers Cst / Chold. For the second anode Anode 2, as shown in FIG. Fig.12 As shown in FIG. 1 , the first portion is on the capacitor trilayer Cst / Chold, and the second portion is not on the planar capacitor trilayer Cst / Chold. The height difference between the first portion and the second portion causes the second anode Anode 2 to have a step. The step causes a difference in the length of the reflection path of external light, which in turn causes reflection color bands and display degradation.

[0219] exist Fig.13 In (B), with Fig.13 Similar to the embodiment (A) in FIG. 1 , since the entire first anode Anode 1 is stacked with the planar capacitor three layers Cst / Chold, the first anode Anode 1 may have a flat structure. Fig.13 Similar to the embodiment (A) in FIG. 1 , a portion of the second anode Anode2 is above the capacitor layer Cst / Chold. However, Fig.13 The embodiment of (A) is different from Fig.10 Similar to the embodiment in FIG. 1 , the portion of the second anode Anode 2 that does not overlap the capacitor three layers Cst / Chold overlaps the double overlapping wirings SL1 and SL2. When the thickness of the double overlapping wirings SL1 and SL2 is selected to form a flat surface with the capacitor three layers Cst / Chold, the second anode Anode 2 may have a thickness of Figure 6 Moreover, the first anode Anode 1 and the second anode Anode 2 may be formed to have the same height. There should be almost no difference in the reflection path of external light, and as a result, the display quality is improved because no reflection color band is generated.

[0220] As a reference, in Fig.13 In the comparative example of (A), the second anode Anode2 can cause a step difference of about 2800Å, but in Fig.13In the embodiment of (B), the second anode Anode2 can result in a step difference of less than 1500 Å, and the step difference can be reduced to 500 Å by optimizing the thickness. Therefore, in the present disclosure, a "flat" anode refers to a case where the height difference between the highest part and the lowest part of the anode is 500 Å or more and 1500 Å or less.

[0221] exist Fig.13 In the embodiment (B), the double overlapping wirings SL1 and SL2 may be located at Figure 4 In the embodiment of the present invention, the first stacked wiring SL1 and the second stacked wiring SL2 are located in different conductive layers from each other among the first gate conductive layer GAT1, the second gate conductive layer GAT2, the auxiliary conductive layer CMTL, the third gate conductive layer GAT3 and the first data conductive layer SD1. In addition, the first stacked wiring SL1 may be located in a conductive layer closer to the substrate 110 than the second stacked wiring SL2, and the second stacked wiring SL2 may be located in a conductive layer closer to the anodes Anode1 and Anode2. In addition, the double stacked wirings SL1 and SL2 are layers located between the substrate 110 and the organic layers 181, 182 and 183, and may be located in a conductive layer other than the semiconductor layer.

[0222] exist Fig.13 In the embodiment (B) of , the first stacked wiring SL1 and the second stacked wiring SL2 may each be one of a scan line for transmitting a scan signal, a light emitting signal line for transmitting a light emitting signal, a voltage line for applying a specific voltage, and a repair line for repair. Figure 1 In the case of a pixel of an embodiment of the present invention, the first stacked wiring SL1 and the second stacked wiring SL2 may each be one of a first scan line 161 to which a first scan signal GW is applied, a second scan line 162 to which a second scan signal GC is applied, a second / first scan line 167 to which a second / first scan signal GC2 corresponding to the second scan signal GC is applied, a third scan line 163 to which a third scan signal GI is applied, light emitting signal lines 164 and 165 to which light emitting signals EM1 and EM2 are applied, a fourth scan line 166 to which a fourth scan signal EB is applied, a driving voltage line 172, a driving low voltage line 179, a first initialization voltage line 173, a second initialization voltage line 175, a reference voltage line 174, a bias voltage line 176, and a repair line RPL. In addition, according to an embodiment, the first stacked wiring SL1 and the second stacked wiring SL2 (for example, like Figure 5 The lower second initialization voltage line 175a and the upper second initialization voltage line 175b of the embodiment of the present invention may be a wiring having a double-layer structure and applying the same signal or voltage.

[0223] According to an embodiment, Figures 5 to 13 The planar structure and cross-sectional structure shown in the figure may not have Figure 1The pixel circuit may include a structure in which two capacitors are stacked. In addition, the stacked wiring stacked with the anode may be various other wirings or conductive layers. However, it may not be a wiring in which the semiconductor layer is made conductive.

[0224] While the present disclosure has been described in conjunction with what are presently considered to be practical exemplary embodiments, it will be understood that the inventive concepts are not limited to the disclosed embodiments. Rather, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A light-emitting display device, characterized in that: The light emitting display device comprises: substrate; A first anode and a second anode are disposed on the substrate; a plurality of conductive layers, at least one semiconductor layer and a plurality of insulating layers, located between the substrate and the first anode and between the substrate and the second anode, wherein the plurality of conductive layers include three capacitor layers, a first stacked wiring, and a second stacked wiring, The first stacked wiring and the second stacked wiring at least partially overlap, At least a portion of the first anode is triple-stacked with the capacitor, and A first portion of the second anode overlaps the first overlapped wiring and the second overlapped wiring.

2. The light-emitting display device according to claim 1, characterized in that ； The plurality of conductive layers, the at least one semiconductor layer and the plurality of insulating layers include: A first semiconductor layer, located on the substrate; A first gate insulating layer, located on the first semiconductor layer; A first gate conductive layer, located on the first gate insulating layer; a second gate insulating layer, located on the first gate conductive layer; A second gate conductive layer, located on the second gate insulating layer; A first interlayer insulating layer, located on the second gate conductive layer; an auxiliary conductive layer, located on the first interlayer insulating layer; A second interlayer insulating layer, located on the auxiliary conductive layer; an oxide semiconductor layer, located on the second interlayer insulating layer; a third gate insulating layer, located on the oxide semiconductor layer; A third gate conductive layer, located on the third gate insulating layer; A third interlayer insulating layer, located on the third gate conductive layer; A first data conductive layer, located on the third interlayer insulating layer; A first organic layer, located on the first data conductive layer; a second data conductive layer, located on the first organic layer; and a second organic layer, located on the second data conductive layer, and Wherein, the three layers of the capacitor include: A driving gate electrode, included in the first gate conductive layer; a second storage electrode included in the second gate conductive layer; and a first holding electrode included in the auxiliary conductive layer, and At least a portion of the driving gate electrode, at least a portion of the second storage electrode, and at least a portion of the first sustaining electrode overlap one another.

3. The light-emitting display device according to claim 2, characterized in that: The first anode and the second anode overlap the second data conductive layer, and The first anode and the second anode overlap a driving voltage line located in the second data conductive layer.

4. The light-emitting display device according to claim 3, characterized in that: The first stacked wiring is located in one conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, The second stacked wiring is located in a different conductive layer from the first stacked wiring which is one conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, The plurality of conductive layers further include a third stacked wiring, the third stacked wiring at least partially overlaps the first stacked wiring and the second stacked wiring, The third stacked wiring is a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and is located in a conductive layer different from the first stacked wiring and the second stacked wiring.

5. The light-emitting display device according to claim 4, characterized in that: The first stacked wiring is a repair line located in the second gate conductive layer, The second stacked wiring is a lower second initialization voltage line located in the auxiliary conductive layer, The third stacked wiring is an upper second initialization voltage line located in the third gate conductive layer, The plurality of conductive layers further include a fourth stacked wiring, a fifth stacked wiring, and a sixth stacked wiring, The fourth stacked wiring, the fifth stacked wiring, and the sixth stacked wiring at least partially overlap one another, a second portion of the second anode overlaps the fourth overlapped wiring, the fifth overlapped wiring, and the sixth overlapped wiring, The fourth stacked wiring is a third scan line located in the first gate conductive layer, The fifth stacked wiring is a first initialization voltage line located in the second gate conductive layer, and The sixth stacked wiring is a first scan line located in the third gate conductive layer.

6. The light-emitting display device according to claim 4, characterized in that: The first stacked wiring is a third scan line located in the first gate conductive layer, The second stacked wiring is a first initialization voltage line located in the second gate conductive layer, and The third stacked wiring is a first scan line located in the third gate conductive layer.

7. A light-emitting display device, characterized in that: The light emitting display device comprises: substrate; a first anode disposed on the substrate; and A plurality of conductive layers, at least one semiconductor layer and a plurality of insulating layers are located between the substrate and the first anode, wherein the plurality of conductive layers include three capacitor layers, a first stacked wiring, and a second stacked wiring, The first stacked wiring and the second stacked wiring at least partially overlap, The first portion of the first anode is triple stacked with the capacitor, and A second portion of the first anode overlaps the first overlapped wiring and the second overlapped wiring.

8. The light-emitting display device according to claim 7, characterized in that: The plurality of conductive layers, the at least one semiconductor layer and the plurality of insulating layers include: A first semiconductor layer, located on the substrate; A first gate insulating layer, located on the first semiconductor layer; A first gate conductive layer, located on the first gate insulating layer; a second gate insulating layer, located on the first gate conductive layer; A second gate conductive layer, located on the second gate insulating layer; A first interlayer insulating layer, located on the second gate conductive layer; an auxiliary conductive layer, located on the first interlayer insulating layer; A second interlayer insulating layer, located on the auxiliary conductive layer; an oxide semiconductor layer, located on the second interlayer insulating layer; a third gate insulating layer, located on the oxide semiconductor layer; A third gate conductive layer, located on the third gate insulating layer; A third interlayer insulating layer, located on the third gate conductive layer; A first data conductive layer, located on the third interlayer insulating layer; A first organic layer, located on the first data conductive layer; a second data conductive layer, located on the first organic layer; and a second organic layer, located on the second data conductive layer, and Wherein, the three layers of the capacitor include: A driving gate electrode, included in the first gate conductive layer; a second storage electrode included in the second gate conductive layer; and a first holding electrode, included in said auxiliary conductive layer, Wherein, at least a portion of the driving gate electrode, at least a portion of the second storage electrode, and at least a portion of the first holding electrode overlap each other.

9. The light-emitting display device according to claim 8, characterized in that: The entire first anode is overlapped with the second data conductive layer, and The entire first anode electrode overlaps the driving voltage line positioned in the second data conductive layer.

10. The light-emitting display device according to claim 9, characterized in that: The first stacked wiring is located in a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, The second stacked wiring is a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and is located in a different conductive layer from the first stacked wiring. The plurality of conductive layers further include a third stacked wiring, the third stacked wiring at least partially overlaps the first stacked wiring and the second stacked wiring, The third stacked wiring is a conductive layer among the first gate conductive layer, the second gate conductive layer, the auxiliary conductive layer, the third gate conductive layer and the first data conductive layer, and is located in a different conductive layer from the first stacked wiring and the second stacked wiring, Two of the first stacked wiring, the second stacked wiring, and the third stacked wiring receive the same voltage or signal, The first stacked wiring is a lower first initialization voltage line located in the first gate conductive layer, The second stacked wiring is an upper first initialization voltage line located in the second gate conductive layer, and The third stacked wiring is a second / first scan line located in the third gate conductive layer.

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