A logic control circuit for a phase-changing switch
By controlling the separation and integration of the dynamic and static contacts from the two-way magnetic flux, the existing commutation switch load capacity and current passing capacity are solved, and a wider application range, lower cost and higher practicality are achieved.
Patent Information
- Application Number
- CN202421493511.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-04-08
- Estimated Expiration
- 2034-06-27
AI Technical Summary
The load capacity and current passing capacity of existing commutator switches are limited, with high cost, large size, and low practicality and compatibility.
Bidirectional flux controls the separation and integration of dynamic and static contacts, and provides reverse current through logic control circuits and driving circuits to realize phase commutation operation.
It improves load and current throughput, has a wider range of applications, is small in size, low in cost, has stronger practicality and compatibility, and reduces line losses.
Smart Images
Figure CN222736140U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of phase-changing switches, in particular to a logic control circuit of a phase-changing switch. Background Art
[0002] In the prior art, regarding the phase-changing switch mode and control mode, the market mostly adopts power electronic semiconductor control, such as IGBT, thyristor, etc. However, due to the limitations of materials and processes, this method greatly limits the load capacity of such products, has high costs, is large in size, and has limited actual on-site installation space, and is not practical and compatible. Utility Model Content
[0003] The purpose of the utility model is to overcome the shortcomings of the prior art and provide a logic control circuit for a phase-changing switch, which achieves the purpose of phase changing by controlling the separation and combination of moving and static contacts through bidirectional magnetic flux when used, has higher load and current passing capacity, wider application range, small size and low cost.
[0004] The purpose of the utility model is mainly achieved through the following technical solutions:
[0005] A logic control circuit for a phase-changing switch comprises a control circuit, a drive circuit, a magnetic flux and moving and stationary contacts connected in sequence, wherein the control circuit is used to provide a control signal to the drive circuit; the drive circuit is used to receive the control signal from the control circuit and provide two reverse currents for the magnetic flux according to the control signal; the magnetic flux is used to receive the two reverse currents from the drive circuit and control the opening and closing of the moving and stationary contacts according to the two reverse currents.
[0006] In a possible implementation, the control circuit includes a single-chip microcomputer, a first photocoupler E1 and a second photocoupler E2, the first photocoupler E1 includes a first light-emitting diode and a first phototransistor, the second photocoupler E2 includes a second light-emitting diode and a second phototransistor, the anode and cathode of the first light-emitting diode are respectively connected to a first resistor R12 and a second resistor R14, the first resistor R12 is connected to the other end of the first light-emitting diode connected to the single-chip microcomputer, the second resistor R14 is connected to the other end of the first light-emitting diode connected to the single-chip microcomputer, the collector of the first phototransistor is connected to a power supply, and the emitter of the first phototransistor is connected to a first R C filtering circuit and a first current limiting resistor R13, the first current limiting resistor R13 is connected to the other end of the first phototransistor and connected to the input end of the driving circuit; the anode and cathode of the second light-emitting diode are respectively connected to the third resistor R19 and the fourth resistor R27, the third resistor R19 is connected to the other end of the second light-emitting diode and connected to the single-chip microcomputer, the fourth resistor R27 is connected to the other end of the second light-emitting diode and connected to the single-chip microcomputer, the collector of the second phototransistor is connected to the power supply, the emitter of the second phototransistor is connected to the second RC filtering circuit and the second current limiting resistor R26, the second current limiting resistor R26 is connected to the other end of the second phototransistor and connected to the input end of the driving circuit.
[0007] In a possible implementation, the driving circuit includes an upper half-bridge driving module and a lower half-bridge driving module, and the upper half-bridge driving module and the lower half-bridge driving module are used to provide two reverse currents for the magnetic flux.
[0008] In a possible implementation, the upper half-bridge driving module includes an upper half-bridge driving circuit and a first driving chip U1; the upper half-bridge driving circuit includes a first NMOS tube Q1, a second NMOS tube Q2, a first diode D1, a second diode D5, a third diode D3, a fourth diode D4, a fifth resistor R4, a sixth resistor R7, a seventh resistor R9 and an eighth resistor R11, the drain of the first NMOS tube Q1 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end of the first driving chip U1 through the fifth resistor R4; the two ends of the sixth resistor R7 are respectively connected to the gate and source of the first NMOS tube Q1; the anode of the first diode D1 is connected to the gate of the first NMOS tube Q1, and the cathode is connected to the high-side output end of the first driving chip U1; the anode of the third diode D3 is connected to the source of the first NMOS tube Q1, The cathode is connected to the drain of the first NMOS tube Q1; the drain of the second NMOS tube Q2 is connected to the source of the first NMOS tube Q1, the source is grounded, and the gate is connected to the low-side output end of the first driver chip U1 through the seventh resistor R9; the two ends of the eighth resistor R11 are respectively connected to the gate and source of the second NMOS tube Q2; the anode of the second diode D5 is connected to the gate of the second NMOS tube Q2, and the cathode is connected to the low-side output of the first driver chip U1; the anode of the fourth diode D4 is connected to the source of the second NMOS tube Q2, and the cathode is connected to the drain of the second NMOS tube Q2; the voltage input end of the first driver chip U1 is connected to the power supply, the signal input end is connected to the output end of the control circuit, a first bootstrap circuit is connected between the high-side power input end and the high-side power return end, and the high-side power return end is connected to the source of the first NMOS tube Q1, and the low-side return end is grounded.
[0009] In a possible implementation, the lower half-bridge driving module includes a lower half-bridge driving circuit and a second driving chip U3; the lower half-bridge driving circuit includes a third NMOS tube Q3, a fourth NMOS tube Q4, a fifth diode D6, a sixth diode D10, a seventh diode D8, an eighth diode D9, a ninth resistor R16, a tenth resistor R17, an eleventh resistor R18 and a twelfth resistor R20; the drain of the third NMOS tube Q3 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end of the second driving chip U3 through the ninth resistor R16; the two ends of the tenth resistor R17 are respectively connected to the gate and source of the third NMOS tube Q3; the anode of the fifth diode D6 is connected to the gate of the third NMOS tube Q3, and the cathode is connected to the high-side output end of the second driving chip U3; the anode of the seventh diode D8 is connected to the source of the third NMOS tube Q3 The cathode is connected to the drain of the third NMOS tube Q3; the drain of the fourth NMOS tube Q4 is connected to the source of the third NMOS tube Q3, the source is grounded, and the gate is connected to the low-side output end of the second driving chip U3 through the eleventh resistor R18; the two ends of the twelfth resistor R20 are respectively connected to the gate and source of the fourth NMOS tube Q4; the anode of the sixth diode D10 is connected to the gate of the fourth NMOS tube Q4, and the cathode is connected to the low-side output of the second driving chip U3; the anode of the eighth diode D9 is connected to the source of the fourth NMOS tube Q4, and the cathode is connected to the drain of the fourth NMOS tube Q4; the voltage input end of the second driving chip U3 is connected to the power supply, the signal input end is connected to the output end of the control circuit, a second bootstrap circuit is connected between the high-side power input end and the high-side power return end, and the high-side power return end is connected to the source of the third NMOS tube Q3, and the low-side return end is grounded.
[0010] In a possible implementation, the upper half-bridge driving module includes a first PMOS tube Q5, a fifth NMOS tube Q6, a ninth diode D11, a tenth diode D12, an eleventh diode D13, a twelfth diode D14, a thirteenth resistor R21, a fourteenth resistor R22, a fifteenth resistor R23 and a sixteenth resistor R24; the source of the first PMOS tube Q5 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the thirteenth resistor R21; the two ends of the fourteenth resistor R22 are respectively connected to the gate and source of the first PMOS tube Q5; the anode of the ninth diode D11 is connected to the drain of the first PMOS tube Q5, and the cathode The anode of the eleventh diode D13 is connected to the gate of the first PMOS tube Q5, and the cathode is connected to the output end of the control circuit; the drain of the fifth NMOS tube Q6 is connected to the drain of the first PMOS tube Q5, the source is grounded, and the gate is connected to the output end of the control circuit through the fifteenth resistor R23; the two ends of the sixteenth resistor R24 are respectively connected to the gate and source of the fifth NMOS tube Q6; the anode of the tenth diode D12 is connected to the source of the fifth NMOS tube Q6, and the cathode is connected to the drain of the fifth NMOS tube Q6; the anode of the twelfth diode D14 is connected to the gate of the fifth NMOS tube Q6, and the cathode is connected to the output end of the control circuit.
[0011] In a possible implementation, the lower half-bridge driving module includes a second PMOS tube Q7, a sixth NMOS tube Q8, a thirteenth diode D15, a fourteenth diode D16, a fifteenth diode D17, a sixteenth diode D18, a seventeenth resistor R25, an eighteenth resistor R26, a nineteenth resistor R27 and a twentieth resistor R28; the source of the second PMOS tube Q7 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the seventeenth resistor R25; the two ends of the eighteenth resistor R26 are respectively connected to the gate and the source of the second PMOS tube Q7; the anode of the thirteenth diode D15 is connected to the drain of the second PMOS tube Q7, and the cathode is connected to the drain of the second PMOS tube Q7. The anode of the fifteenth diode D17 is connected to the gate of the second PMOS tube Q7, and the cathode is connected to the output end of the control circuit; the drain of the sixth NMOS tube Q8 is connected to the drain of the second PMOS tube Q7, the source is grounded, and the gate is connected to the output end of the control circuit through a nineteenth resistor R27; the two ends of the twentieth resistor R28 are respectively connected to the gate and source of the sixth NMOS tube Q8; the anode of the fourteenth diode D16 is connected to the source of the sixth NMOS tube Q8, and the cathode is connected to the drain of the sixth NMOS tube Q8; the anode of the sixteenth diode D18 is connected to the gate of the sixth NMOS tube Q8, and the cathode is connected to the output end of the control circuit.
[0012] To sum up, compared with the prior art, the utility model has the following beneficial effects: when the utility model is used, the purpose of phase change is achieved by controlling the separation and combination of the moving and static contacts through bidirectional magnetic flux. Compared with the phase-changing switch in the prior art, it has a higher load and a higher current passing capacity, and a wider range of applications; compared with the control method using power electronic semiconductors (IGBT, thyristor, etc.), the utility model has fewer electronic components and a smaller size, which effectively reduces the installation space, has stronger practicality and compatibility, and has a lower cost; when the utility model is used, it only needs to supply power when changing phases, and there is no need to supply power all the time, which reduces line losses. At the same time, the phase-changing interval time can be customized by the single-chip microcomputer. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The drawings described herein are used to provide a further understanding of the embodiments of the present utility model, constitute a part of this application, and do not constitute a limitation of the embodiments of the present utility model. In the drawings:
[0014] Figure 1 This is a schematic diagram of a control circuit according to an embodiment of the utility model;
[0015] Figure 2 This is a schematic diagram of a driving circuit according to an embodiment of the utility model;
[0016] Figure 3 This is another schematic diagram of the driving circuit according to an embodiment of the utility model. DETAILED DESCRIPTION
[0017] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments and drawings. The schematic implementation manner of the utility model and its description are only used to explain the utility model and are not intended to limit the utility model.
[0018] Embodiment 1:
[0019] A logic control circuit for a phase-changing switch comprises a control circuit, a drive circuit, a magnetic flux and moving and stationary contacts connected in sequence, wherein the control circuit is used to provide a control signal to the drive circuit; the drive circuit is used to receive the control signal from the control circuit and provide two reverse currents for the magnetic flux according to the control signal; the magnetic flux is used to receive the two reverse currents from the drive circuit and control the opening and closing of the moving and stationary contacts according to the two reverse currents.
[0020] In this embodiment, the magnetic flux is the opening and closing electromagnet, the output end of the driving circuit is connected to the opening and closing coil of the opening and closing electromagnet, and the armature of the opening and closing electromagnet is connected to the moving contact. When phase switching operation is required, the control circuit controls the driving circuit so that the driving circuit provides two reverse currents to the opening and closing electromagnet, thereby changing the power supply polarity of the opening and closing electromagnet to make the armature move up and down to control the opening and closing of the moving and static contacts, thereby achieving the purpose of phase switching.
[0021] like Figure 1 As shown, in a possible implementation, the control circuit includes a single-chip microcomputer, a first photocoupler E1 and a second photocoupler E2, the first photocoupler E1 includes a first light-emitting diode and a first phototransistor, the second photocoupler E2 includes a second light-emitting diode and a second phototransistor, the anode and cathode of the first light-emitting diode are respectively connected to a first resistor R12 and a second resistor R14, the first resistor R12 is connected to the other end of the first light-emitting diode connected to the single-chip microcomputer, the second resistor R14 is connected to the other end of the first light-emitting diode connected to the single-chip microcomputer, the collector of the first phototransistor is connected to a power supply, and the emitter of the first phototransistor is connected to the first resistor R12. An RC filter circuit and a first current limiting resistor R13, the first current limiting resistor R13 is connected to the other end of the first phototransistor and connected to the input end of the driving circuit; the anode and cathode of the second light-emitting diode are respectively connected to the third resistor R19 and the fourth resistor R27, the third resistor R19 is connected to the other end of the second light-emitting diode and connected to the single-chip computer, the fourth resistor R27 is connected to the other end of the second light-emitting diode and connected to the single-chip computer, the collector of the second phototransistor is connected to the power supply, the emitter of the second phototransistor is connected to the second RC filter circuit and the second current limiting resistor R26, the second current limiting resistor R26 is connected to the other end of the second phototransistor and connected to the input end of the driving circuit. Specifically, the first RC filter circuit includes a first filter resistor R15 and a first filter capacitor C8 in parallel, one end of the first filter resistor R15 is connected to the emitter of the first phototransistor, and the other end of the first filter resistor R15 is grounded; the second RC filter circuit includes a second filter resistor R30 and a second filter capacitor C13 in parallel, one end of the second filter resistor R30 is connected to the emitter of the second phototransistor, and the other end of the second filter resistor R30 is grounded.
[0022] In a possible implementation, the driving circuit includes an upper half-bridge driving module and a lower half-bridge driving module, and the upper half-bridge driving module and the lower half-bridge driving module are used to provide two reverse currents for the magnetic flux.
[0023] In a possible implementation, the upper half-bridge driving module includes an upper half-bridge driving circuit and a first driving chip U1; the upper half-bridge driving circuit includes a first NMOS tube Q1, a second NMOS tube Q2, a first diode D1, a second diode D5, a third diode D3, a fourth diode D4, a fifth resistor R4, a sixth resistor R7, a seventh resistor R9 and an eighth resistor R11, the drain of the first NMOS tube Q1 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end HO of the first driving chip U1 through the fifth resistor R4; the two ends of the sixth resistor R7 are respectively connected to the gate and source of the first NMOS tube Q1; the anode of the first diode D1 is connected to the gate of the first NMOS tube Q1, and the cathode is connected to the high-side output end HO of the first driving chip U1; the anode of the third diode D3 is connected to the source of the first NMOS tube Q1, and the cathode is connected to the first NM The drain of the OS transistor Q1; the drain of the second NMOS transistor Q2 is connected to the source of the first NMOS transistor Q1, the source is grounded, and the gate is connected to the low-side output terminal LO of the first driver chip U1 through the seventh resistor R9; the two ends of the eighth resistor R11 are respectively connected to the gate and source of the second NMOS transistor Q2; the anode of the second diode D5 is connected to the gate of the second NMOS transistor Q2, and the cathode is connected to the low-side output terminal LO of the first driver chip U1; the anode of the fourth diode D4 is connected to the source of the second NMOS transistor Q2, and the cathode is connected to the drain of the second NMOS transistor Q2; the voltage input terminal VCC of the first driver chip U1 is connected to the power supply, the signal input terminal IN is connected to the output terminal of the control circuit, a first bootstrap circuit is connected between the high-side power input terminal VB and the high-side power return terminal VS, and the high-side power return terminal VS is connected to the source of the first NMOS transistor Q1, and the low-side return terminal COM is grounded. Specifically, the first bootstrap circuit includes a first bootstrap boost capacitor C2 and a first bootstrap boost diode D2, which are used to increase the output voltage of the high-side output terminal of the first driver chip U1, so that the Vgs voltage is greater than the conduction voltage of the first NMOS tube Q1, so that the first NMOS tube Q1 can be normally turned on, and the two ends of the first bootstrap boost capacitor C2 are respectively connected to the high-side power input terminal VB and the high-side power return terminal VS of the first driver chip U1; the anode of the first bootstrap boost diode D2 is connected to the power supply, and the cathode is connected between the high-side power input terminal VB of the first driver chip U1 and the first bootstrap boost capacitor C2. Preferably, the model of the first driver chip U1 is IR2104STRPBF.
[0024] In a possible implementation, the lower half-bridge driving module includes a lower half-bridge driving circuit and a second driving chip U3; the lower half-bridge driving circuit includes a third NMOS tube Q3, a fourth NMOS tube Q4, a fifth diode D6, a sixth diode D10, a seventh diode D8, an eighth diode D9, a ninth resistor R16, a tenth resistor R17, an eleventh resistor R18 and a twelfth resistor R20; the drain of the third NMOS tube Q3 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end HO of the second driving chip U3 through the ninth resistor R16; the two ends of the tenth resistor R17 are respectively connected to the gate and source of the third NMOS tube Q3; the anode of the fifth diode D6 is connected to the gate of the third NMOS tube Q3, and the cathode is connected to the high-side output end HO of the second driving chip U3; the anode of the seventh diode D8 is connected to the source of the third NMOS tube Q3, and the cathode is connected to the third The drain of the NMOS tube Q3; the drain of the fourth NMOS tube Q4 is connected to the source of the third NMOS tube Q3, the source is grounded, and the gate is connected to the low-side output terminal LO of the second driving chip U3 through the eleventh resistor R18; the two ends of the twelfth resistor R20 are respectively connected to the gate and source of the fourth NMOS tube Q4; the anode of the sixth diode D10 is connected to the gate of the fourth NMOS tube Q4, and the cathode is connected to the low-side output terminal LO of the second driving chip U3; the anode of the eighth diode D9 is connected to the source of the fourth NMOS tube Q4, and the cathode is connected to the drain of the fourth NMOS tube Q4; the voltage input terminal VCC of the second driving chip U3 is connected to the power supply, the signal input terminal IN is connected to the output terminal of the control circuit, a second bootstrap circuit is connected between the high-side power input terminal VB and the high-side power return terminal VS, and the high-side power return terminal VS is connected to the source of the third NMOS tube Q3, and the low-side return terminal COM is grounded. Specifically, the second bootstrap circuit includes a second bootstrap boost capacitor C9 and a second bootstrap boost diode D7, which are used to increase the output voltage of the high-side output terminal of the second driver chip U3, so that the Vgs voltage is greater than the conduction voltage of the third NMOS tube Q3, so that the third NMOS tube Q3 can be normally turned on, and the two ends of the second bootstrap boost capacitor C9 are respectively connected to the high-side power input terminal VB and the high-side power return terminal VS of the second driver chip U3; the anode of the second bootstrap boost diode D7 is connected to the power supply, and the cathode is connected to the high-side power input terminal VB of the second driver chip U3 and between the second bootstrap boost capacitor C9. Preferably, the model of the second driver chip U3 is IR2104STRPBF.
[0025] Specifically, in actual application of this embodiment, when the single chip microcomputer inputs a high level to the first photocoupler E1 and inputs a low level to the second photocoupler E2, the first photocoupler E1 outputs a low level, and the second photocoupler E2 outputs a high level. At this time, the signal input terminal IN of the first driver chip U1 receives the low level signal output from the first photocoupler E1, the high side output terminal HO of the first driver chip U1 outputs a low level, and the low side output terminal LO outputs a high level. The signal input terminal IN of the second driver chip U3 receives the high level signal output from the second photocoupler E2, the high side output terminal HO of the second driver chip U3 outputs a high level, and the low side output terminal LO outputs a low level. At this time, the first NMOS tube Q1 is closed, the second NMOS tube Q2 is turned on, the third NMOS tube Q3 is turned on, and the fourth NMOS tube Q4 is closed. The power supply VCC_coil supplies power to the magnetic flux through the third NMOS tube Q3, the magnetic flux, and the second NMOS tube Q2, and the direction of the current at this time is defined as the positive direction; when the single chip microcomputer inputs a low level to the first photocoupler E1 , when a high level is input to the second photocoupler E2, the first photocoupler E1 outputs a high level, and the second photocoupler E2 outputs a low level. At this time, the signal input terminal IN of the first driver chip U1 receives the high level signal output from the first photocoupler E1, the high-side output terminal HO of the first driver chip U1 outputs a high level, and the low-side output terminal LO outputs a low level. The signal input terminal IN of the second driver chip U3 receives the low level signal output from the second photocoupler E2, the high-side output terminal HO of the second driver chip U3 outputs a low level, and the low-side output terminal LO outputs a high level. At this time, the first NMOS tube Q1 is turned on, the second NMOS tube Q2 is closed, the third NMOS tube Q3 is closed, and the fourth NMOS tube Q4 is turned on. The power supply VCC_coil supplies power to the magnetic flux through the first NMOS tube Q1, the magnetic flux, and the fourth NMOS tube Q4, and the direction of the current at this time is defined as the opposite direction; therefore, in this embodiment, different control signals are sent to the two photocouplers by the single-chip microcomputer to supply currents in opposite directions to the magnetic flux, thereby controlling the separation and closing of the moving and static contacts.
[0026] Embodiment 2:
[0027] Based on Example 1, this embodiment deletes the first driver chip U1 and the second driver chip U3, thereby further reducing the cost. At the same time, in order to realize the control of the subsequent circuit, the first NMOS transistor Q1 and the third NMOS transistor Q3 in Example 1 are replaced by two PMOS transistors.
[0028] like Figure 3As shown, in a possible implementation, the upper half-bridge driving module includes a first PMOS tube Q5, a fifth NMOS tube Q6, a ninth diode D11, a tenth diode D12, an eleventh diode D13, a twelfth diode D14, a thirteenth resistor R21, a fourteenth resistor R22, a fifteenth resistor R23 and a sixteenth resistor R24; the source of the first PMOS tube Q5 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the thirteenth resistor R21; the two ends of the fourteenth resistor R22 are respectively connected to the gate and the source of the first PMOS tube Q5; the anode of the ninth diode D11 is connected to the drain of the first PMOS tube Q5, and the cathode is connected to the drain of the first PMOS tube Q5. The anode of the eleventh diode D13 is connected to the gate of the first PMOS tube Q5, and the cathode is connected to the output end of the control circuit; the drain of the fifth NMOS tube Q6 is connected to the drain of the first PMOS tube Q5, the source is grounded, and the gate is connected to the output end of the control circuit through a fifteenth resistor R23; the two ends of the sixteenth resistor R24 are respectively connected to the gate and source of the fifth NMOS tube Q6; the anode of the tenth diode D12 is connected to the source of the fifth NMOS tube Q6, and the cathode is connected to the drain of the fifth NMOS tube Q6; the anode of the twelfth diode D14 is connected to the gate of the fifth NMOS tube Q6, and the cathode is connected to the output end of the control circuit.
[0029] In a possible implementation, the lower half-bridge driving module includes a second PMOS tube Q7, a sixth NMOS tube Q8, a thirteenth diode D15, a fourteenth diode D16, a fifteenth diode D17, a sixteenth diode D18, a seventeenth resistor R25, an eighteenth resistor R26, a nineteenth resistor R27 and a twentieth resistor R28; the source of the second PMOS tube Q7 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the seventeenth resistor R25; the two ends of the eighteenth resistor R26 are respectively connected to the gate and the source of the second PMOS tube Q7; the anode of the thirteenth diode D15 is connected to the drain of the second PMOS tube Q7, and the cathode is connected to the drain of the second PMOS tube Q7. The anode of the fifteenth diode D17 is connected to the gate of the second PMOS tube Q7, and the cathode is connected to the output end of the control circuit; the drain of the sixth NMOS tube Q8 is connected to the drain of the second PMOS tube Q7, the source is grounded, and the gate is connected to the output end of the control circuit through a nineteenth resistor R27; the two ends of the twentieth resistor R28 are respectively connected to the gate and source of the sixth NMOS tube Q8; the anode of the fourteenth diode D16 is connected to the source of the sixth NMOS tube Q8, and the cathode is connected to the drain of the sixth NMOS tube Q8; the anode of the sixteenth diode D18 is connected to the gate of the sixth NMOS tube Q8, and the cathode is connected to the output end of the control circuit.
[0030] Specifically, in actual application of this embodiment, when the single chip microcomputer inputs a high level to the first photocoupler E1 and a low level to the second photocoupler E2, the first photocoupler E1 outputs a low level, and the second photocoupler E2 outputs a high level. At this time, the first PMOS tube Q5 is turned on, the fifth NMOS tube Q6 is closed, the second PMOS tube Q7 is closed, the sixth NMOS tube Q8 is turned on, and the power supply VCC_coil supplies reverse electricity to the magnetic flux through the first PMOS tube Q5, the magnetic flux, and the sixth NMOS tube Q8; when the single chip microcomputer inputs a low level to the first photocoupler E1 and a high level to the second photocoupler E2, the first photocoupler E1 outputs a high level, and the second photocoupler E2 outputs a low level. At this time, the first PMOS tube Q5 is closed, the fifth NMOS tube Q6 is turned on, the second PMOS tube Q7 is turned on, the sixth NMOS tube Q8 is closed, and the power supply VCC_coil supplies forward electricity to the magnetic flux through the second PMOS tube Q7, the magnetic flux, and the fifth NMOS tube Q6.
[0031] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.
Claims
1. A logic control circuit for a phase-changing switch, characterized in that: It includes a control circuit, a drive circuit, a magnetic flux and moving and static contacts connected in sequence, wherein the control circuit is used to provide a control signal to the drive circuit; the drive circuit is used to receive the control signal from the control circuit, and provide two reverse currents for the magnetic flux according to the control signal; the magnetic flux is used to receive the two reverse currents from the drive circuit, and control the opening and closing of the moving and static contacts according to the two reverse currents.
2. A logic control circuit for a phase-changing switch according to claim 1, characterized in that: The control circuit includes a single chip microcomputer, a first photocoupler E1 and a second photocoupler E2, the first photocoupler E1 includes a first light emitting diode and a first phototransistor, the second photocoupler E2 includes a second light emitting diode and a second phototransistor, the anode and cathode of the first light emitting diode are respectively connected to a first resistor R12 and a second resistor R14, the first resistor R12 is connected to the other end of the first light emitting diode connected to the single chip microcomputer, the second resistor R14 is connected to the other end of the first light emitting diode connected to the single chip microcomputer, the collector of the first phototransistor is connected to a power supply, and the emitter of the first phototransistor is connected to a first RC filter circuit and A first current limiting resistor R13, the first current limiting resistor R13 is connected to the other end of the first phototransistor and connected to the input end of the driving circuit; the anode and cathode of the second light-emitting diode are respectively connected to the third resistor R19 and the fourth resistor R27, the third resistor R19 is connected to the other end of the second light-emitting diode and connected to the single-chip microcomputer, the fourth resistor R27 is connected to the other end of the second light-emitting diode and connected to the single-chip microcomputer, the collector of the second phototransistor is connected to the power supply, the emitter of the second phototransistor is connected to the second RC filter circuit and the second current limiting resistor R26, the second current limiting resistor R26 is connected to the other end of the second phototransistor and connected to the input end of the driving circuit.
3. The logic control circuit of a phase-changing switch according to claim 1, characterized in that: The driving circuit comprises an upper half-bridge driving module and a lower half-bridge driving module, and the upper half-bridge driving module and the lower half-bridge driving module are used to provide two reverse currents for the magnetic flux.
4. A logic control circuit for a phase-changing switch according to claim 3, characterized in that: The upper half-bridge driving module includes an upper half-bridge driving circuit and a first driving chip U1; the upper half-bridge driving circuit includes a first NMOS tube Q1, a second NMOS tube Q2, a first diode D1, a second diode D5, a third diode D3, a fourth diode D4, a fifth resistor R4, a sixth resistor R7, a seventh resistor R9 and an eighth resistor R11, the drain of the first NMOS tube Q1 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end of the first driving chip U1 through the fifth resistor R4; the two ends of the sixth resistor R7 are respectively connected to the gate and source of the first NMOS tube Q1; the anode of the first diode D1 is connected to the gate of the first NMOS tube Q1, and the cathode is connected to the high-side output end of the first driving chip U1; the anode of the third diode D3 is connected to the source of the first NMOS tube Q1, and the cathode is connected to the first The drain of the NMOS tube Q1; the drain of the second NMOS tube Q2 is connected to the source of the first NMOS tube Q1, the source is grounded, and the gate is connected to the low-side output end of the first driver chip U1 through the seventh resistor R9; the two ends of the eighth resistor R11 are respectively connected to the gate and source of the second NMOS tube Q2; the anode of the second diode D5 is connected to the gate of the second NMOS tube Q2, and the cathode is connected to the low-side output of the first driver chip U1; the anode of the fourth diode D4 is connected to the source of the second NMOS tube Q2, and the cathode is connected to the drain of the second NMOS tube Q2; the voltage input end of the first driver chip U1 is connected to the power supply, the signal input end is connected to the output end of the control circuit, a first bootstrap circuit is connected between the high-side power input end and the high-side power return end, and the high-side power return end is connected to the source of the first NMOS tube Q1, and the low-side return end is grounded.
5. The logic control circuit of a phase-changing switch according to claim 4, characterized in that: The lower half-bridge driving module includes a lower half-bridge driving circuit and a second driving chip U3; the lower half-bridge driving circuit includes a third NMOS tube Q3, a fourth NMOS tube Q4, a fifth diode D6, a sixth diode D10, a seventh diode D8, an eighth diode D9, a ninth resistor R16, a tenth resistor R17, an eleventh resistor R18 and a twelfth resistor R20; the drain of the third NMOS tube Q3 is connected to the power supply, the source is connected to the input end of the magnetic flux, and the gate is connected to the high-side output end of the second driving chip U3 through the ninth resistor R16; the two ends of the tenth resistor R17 are respectively connected to the gate and source of the third NMOS tube Q3; the anode of the fifth diode D6 is connected to the gate of the third NMOS tube Q3, and the cathode is connected to the high-side output end of the second driving chip U3; the anode of the seventh diode D8 is connected to the source of the third NMOS tube Q3, and the cathode is connected the drain of the third NMOS tube Q3; the drain of the fourth NMOS tube Q4 is connected to the source of the third NMOS tube Q3, the source is grounded, and the gate is connected to the low-side output end of the second driving chip U3 through the eleventh resistor R18; the two ends of the twelfth resistor R20 are respectively connected to the gate and source of the fourth NMOS tube Q4; the anode of the sixth diode D10 is connected to the gate of the fourth NMOS tube Q4, and the cathode is connected to the low-side output of the second driving chip U3; the anode of the eighth diode D9 is connected to the source of the fourth NMOS tube Q4, and the cathode is connected to the drain of the fourth NMOS tube Q4; the voltage input end of the second driving chip U3 is connected to the power supply, the signal input end is connected to the output end of the control circuit, a second bootstrap circuit is connected between the high-side power input end and the high-side power return end, and the high-side power return end is connected to the source of the third NMOS tube Q3, and the low-side return end is grounded.
6. The logic control circuit of a phase-changing switch according to claim 3, characterized in that: The upper half-bridge driving module includes a first PMOS tube Q5, a fifth NMOS tube Q6, a ninth diode D11, a tenth diode D12, an eleventh diode D13, a twelfth diode D14, a thirteenth resistor R21, a fourteenth resistor R22, a fifteenth resistor R23 and a sixteenth resistor R24; the source of the first PMOS tube Q5 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the thirteenth resistor R21; the two ends of the fourteenth resistor R22 are respectively connected to the gate and the source of the first PMOS tube Q5; the anode of the ninth diode D11 is connected to the drain of the first PMOS tube Q5, and the cathode is connected to the first PM The anode of the eleventh diode D13 is connected to the gate of the first PMOS tube Q5, and the cathode is connected to the output end of the control circuit; the drain of the fifth NMOS tube Q6 is connected to the drain of the first PMOS tube Q5, the source is grounded, and the gate is connected to the output end of the control circuit through the fifteenth resistor R23; the two ends of the sixteenth resistor R24 are respectively connected to the gate and source of the fifth NMOS tube Q6; the anode of the tenth diode D12 is connected to the source of the fifth NMOS tube Q6, and the cathode is connected to the drain of the fifth NMOS tube Q6; the anode of the twelfth diode D14 is connected to the gate of the fifth NMOS tube Q6, and the cathode is connected to the output end of the control circuit.
7. A logic control circuit for a phase-changing switch according to claim 6, characterized in that: The lower half-bridge driving module includes a second PMOS tube Q7, a sixth NMOS tube Q8, a thirteenth diode D15, a fourteenth diode D16, a fifteenth diode D17, a sixteenth diode D18, a seventeenth resistor R25, an eighteenth resistor R26, a nineteenth resistor R27 and a twentieth resistor R28; the source of the second PMOS tube Q7 is connected to the power supply, the drain is connected to the input end of the magnetic flux, and the gate is connected to the output end of the control circuit through the seventeenth resistor R25; the two ends of the eighteenth resistor R26 are respectively connected to the gate and the source of the second PMOS tube Q7; the anode of the thirteenth diode D15 is connected to the drain of the second PMOS tube Q7, and the cathode is connected to the second PMOS tube Q7. The anode of the fifteenth diode D17 is connected to the gate of the second PMOS tube Q7, and the cathode is connected to the output end of the control circuit; the drain of the sixth NMOS tube Q8 is connected to the drain of the second PMOS tube Q7, the source is grounded, and the gate is connected to the output end of the control circuit through the nineteenth resistor R27; the two ends of the twentieth resistor R28 are respectively connected to the gate and source of the sixth NMOS tube Q8; the anode of the fourteenth diode D16 is connected to the source of the sixth NMOS tube Q8, and the cathode is connected to the drain of the sixth NMOS tube Q8; the anode of the sixteenth diode D18 is connected to the gate of the sixth NMOS tube Q8, and the cathode is connected to the output end of the control circuit.