A voltage detection circuit for an embedded motherboard

Abstract

The utility model provides a voltage detection circuit of an embedded mainboard, comprising a power management integrated circuit PMIC, a micro control unit MCU, a watchdog circuit and a micro processing unit MPU. The power management integrated circuit PMIC is connected with the micro control unit MCU and the micro processing unit MPU to send the voltage generated after startup to the micro control unit MCU and the micro processing unit MPU. An IO port of the micro control unit MCU is connected to the watchdog circuit, and an output end of the watchdog circuit is connected to the micro processing unit MPU. When the micro control unit MCU detects various voltages generated by the PMIC, the IO port connected to the watchdog outputs a low level, the watchdog circuit is in a reset state and controls the micro processing unit MPU to be in a reset state; when the micro control unit MUC completes the detection of all voltages and the detection is normal, the IO port connected to the watchdog outputs a high level to drive the micro processing unit MPU to start normally, thereby ensuring the effectiveness and consistency of the normal startup of the embedded system CPU.

Description

Technical Field

[0001] The utility model relates to the field of circuits, in particular to a voltage detection circuit for an embedded mainboard. Background Art

[0002] An embedded board is an electronic motherboard specially designed for embedded systems. An embedded system is a computer system that is integrated into other devices or systems to perform specific functions. Embedded motherboards are usually small, low power, and highly reliable, and can meet the needs of various embedded applications. The CPU is the core component of an embedded motherboard. The CPU usually requires a certain power supply voltage to work properly and perform computing tasks. How to effectively ensure the normal operation of the CPU and avoid the failure of the embedded system due to unstable power supply voltage of the CPU chip is a topic that hardware engineers need to study in depth.

[0003] The conventional solution uses the power domain voltages generated by the power management integrated circuit PMIC to power the CPU. After all the power domain voltages are powered on, the reset is released and the CPU starts. Of course, there are also solutions that will design a watchdog circuit. During the power-on startup process, the PMIC sends a CPU reset signal and a watchdog power-on reset signal to reset the CPU simultaneously through the AND gate. At this time, the reset effective level takes the longest time of the two as the CPU reset time. If the CPU starts abnormally due to the instantaneous value of the power supply of the power domain at this time, it is necessary to measure and monitor the voltage generated by each PMIC at the same time, which greatly increases the workload of troubleshooting. In addition, not all power networks generated by the PMIC are abnormal, which causes the problem of CPU startup abnormality consistency. Utility Model Content

[0004] The utility model aims to provide a voltage detection circuit for an embedded mainboard, which introduces an MCU to detect the voltages of various channels after a PMIC is started, and an IO port of the MCU is connected to a watchdog pin / MR pin, thereby ensuring the effectiveness and consistency of normal startup of the embedded system CPU, and greatly reducing the troubleshooting time invested in abnormal CPU startup.

[0005] To achieve the above objectives, the present technical solution provides a voltage detection circuit for an embedded motherboard, comprising:

[0006] A power management integrated circuit PMIC, a microcontroller unit MCU, a watchdog circuit and a microprocessing unit MPU. The power management integrated circuit PMIC is connected with the microcontroller unit MCU and the microprocessing unit MPU to send the voltage generated after startup to the microcontroller unit MCU and the microprocessing unit MPU. The IO port of the microcontroller unit MCU is connected to the watchdog circuit, and the output end of the watchdog circuit is connected to the microprocessing unit MPU. When the microcontroller unit MCU detects the various voltages generated by the power management integrated circuit PMIC, the IO port connected to the watchdog outputs a low level, the watchdog circuit is in a reset state and controls the microprocessing unit MPU to be in a reset state; when the microcontroller unit MUC completes the detection of all voltages and the detection is normal, the IO port connected to the watchdog outputs a high level to drive the microprocessing unit MPU to start normally.

[0007] Compared with the prior art, the technical solution has the following characteristics and beneficial effects: the solution introduces MCU into the circuit structure of the traditional power management integrated circuit PMIC controlling MPU, and detects the voltage of each channel of the power management integrated circuit PMIC through the MCU. When the MCU detects the voltage, the control watchdog circuit is always reset and effective, thereby ensuring that the MPU is in a reset state. When the MCU detects that all voltages are normal, the watchdog circuit triggers the normal operation of the MPU. The solution can ensure the effectiveness and consistency of the normal startup of the embedded system CPU, and greatly reduce the troubleshooting time invested in abnormal CPU startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a circuit diagram of a voltage detection circuit of an embedded motherboard according to an embodiment of the present solution. DETAILED DESCRIPTION

[0009] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the utility model.

[0010] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0011] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0012] In order to facilitate the understanding of this plan, the professional terms involved in this plan are first explained:

[0013] PMIC: Power Management Integrated Circuit, also known as power management chip or power management IC, is a chip that integrates multiple power management functions and is used to manage and regulate the power supply and power conversion of electronic devices.

[0014] MCU: Microcontroller Unit is a single-chip computer system that integrates a processor core, memory, input / output interface and other functional modules. It is used in embedded systems to control and execute specific tasks.

[0015] Watchdog pin: used to connect the output signal of the watchdog circuit to monitor the operating status of the system. When the system is operating normally, the watchdog circuit will periodically reset the state of the watchdog pin to indicate that the system is operating normally. If the system fails or stops responding, the watchdog circuit will no longer reset the pin, triggering a watchdog reset or other recovery action.

[0016] MR pin: used to perform the master reset operation of the system. When this pin is pulled low, the system will perform a master reset, restore the various components and registers of the system to the initial state, and restart the system.

[0017] The traditional solution is to use the power domains generated by PMIC to power the CPU in the embedded system. In the traditional solution, if the CPU startup is abnormal due to the instantaneous value of the power domain power supply, it is necessary to monitor the voltage generated by each PMIC at the same time, which will greatly increase the workload of troubleshooting and also cause the problem of CPU startup abnormality consistency. This solution provides a voltage detection circuit for an embedded motherboard, including:

[0018] A power management integrated circuit PMIC, a microcontroller unit MCU, a watchdog circuit and a microprocessing unit MPU. The power management integrated circuit PMIC is connected with the microcontroller unit MCU and the microprocessing unit MPU to send the voltage generated after startup to the microcontroller unit MCU and the microprocessing unit MPU. The IO port of the microcontroller unit MCU is connected to the watchdog circuit, and the output end of the watchdog circuit is connected to the microprocessing unit MPU. When the microcontroller unit MCU detects the various voltages generated by the power management integrated circuit PMIC, the IO port connected to the watchdog outputs a low level, the watchdog circuit is in a reset state and controls the microprocessing unit MPU to be in a reset state; when the microcontroller unit MUC completes the detection of all voltages and the detection is normal, the IO port connected to the watchdog outputs a high level to drive the microprocessing unit MPU to start normally.

[0019] This solution introduces a microcontroller unit MCU to detect the voltages generated by the power management reset circuit PMIC, thereby ensuring the startup consistency of the microprocessor unit MPU without having to detect each circuit at the same time.

[0020] Specifically, the voltage generated after the power management integrated circuit PMIC is started is sent to the analog-to-digital converter in the microcontroller unit MCU. The analog-to-digital converter ADC is used to convert the continuous analog signal into a corresponding discrete digital signal. Then the microcontroller unit MCU detects the voltage generated in each channel. When the microcontroller unit MCU is in the detection state, the IO pin of the microcontroller unit MCU connected to the watchdog circuit outputs a low level.

[0021] In some embodiments, the watchdog circuit includes a first AND gate, a second AND gate, a first buffer, a reset monitor, and a third AND gate connected in sequence, wherein the input end of the first AND gate is connected to the IO port of the microcontroller unit MCU, the two input ends of the second AND gate are respectively connected to the output signal of the first AND gate and the ground signal, the output signal of the second AND gate is input to the first buffer, the output signal of the first buffer is connected to the MR interface of the reset monitor, the three input ends of the third AND gate are respectively connected to the output signal of the reset monitor, the reset signal of the power management integrated circuit PMIC and the interface reset signal, and the output end of the third AND gate is connected to the POR interface of the microprocessing unit MPU.

[0022] Specifically, the microprocessing unit MPU is a computer processor including a CPU, a cache, a register and a bus interface, and is an integrated circuit that can be used to perform computing tasks. The microcontrol unit MCU communicates with the microprocessing unit MPU, and the nRst_REQ interface of the microprocessing unit MPU is used to send a reset request signal to the microcontrol unit MCU. When the nRst_REQ interface of the microprocessing unit MPU does not send a reset request signal to the microcontrol unit MCU, the ground signal connected to the second AND gate input terminal is a high level signal. When the MCU of the microcontrol unit detects the voltage of the power management integrated circuit PMIC, the level signal of the input terminal of the first AND gate of the watchdog circuit is low level, and the first AND gate outputs a low level signal; the signals of the two input terminals of the second AND gate are a high level signal and a low level signal, so the second AND gate still outputs a low level signal; the signal output by the second AND gate is input to the reset monitor after passing through the first buffer, so that the reset monitor still outputs a low level signal and a reset signal, and the reset signal is sent to the microprocessing unit MPU so that the microprocessing unit MPU is always in a reset state.

[0023] It should be noted that when the microprocessing unit MPU sends a reset request signal to the microcontroller unit MCU, at least one of the input ends of the second AND gate of the watchdog circuit is at a low level, which causes the watchdog circuit to remain in a low-level reset valid state, and the corresponding microprocessing unit MPU is in a reset state.

[0024] Once the microcontroller unit MCU completes the detection of all voltages and the results of all voltage detections are normal, the IO pins connected to the watchdog circuit are all input with a high level, and the first AND gate outputs a high level signal; the signals at the two input ends of the second AND gate are both high level signals, so the second AND gate also outputs a high level signal; the signal output by the second AND gate passes through the first buffer and is input into the reset monitor, so that the reset monitor outputs a working signal of a high level signal, and the working signal is sent to the microprocessing unit MPU so that the MPU can start normally.

[0025] In some embodiments, the microcontroller unit MCU sends a power management integrated circuit power standby signal and a power management integrated circuit power on signal to the power management integrated circuit PMIC, and the power management integrated circuit PMIC sends a power management integrated circuit power normal signal and a power management integrated circuit error warning signal to the microcontroller unit MCU.

[0026] The voltage detection circuit of the embedded motherboard of this solution can detect the instantaneous value problem of the power supply that causes the CPU startup abnormality, and ensure the effectiveness and consistency of each CPU startup.

[0027] The present utility model is not limited to the above-mentioned optimal implementation mode. Anyone can derive other various forms of products under the inspiration of the present utility model. However, no matter what changes are made in the shape or structure, all those having the same or similar technical solutions as the present application fall within the protection scope of the present utility model.

Claims

1. A voltage detection circuit for an embedded motherboard, characterized in that: include: A power management integrated circuit PMIC, a microcontroller unit MCU, a watchdog circuit and a microprocessing unit MPU. The power management integrated circuit PMIC is connected with the microcontroller unit MCU and the microprocessing unit MPU to send the voltage generated after startup to the microcontroller unit MCU and the microprocessing unit MPU. The IO port of the microcontroller unit MCU is connected to the watchdog circuit, and the output end of the watchdog circuit is connected to the microprocessing unit MPU. When the microcontroller unit MCU detects the various voltages generated by the power management integrated circuit PMIC, the IO port connected to the watchdog outputs a low level, the watchdog circuit is in a reset state and controls the microprocessing unit MPU to be in a reset state; when the microcontroller unit MUC completes the detection of all voltages and the detection is normal, the IO port connected to the watchdog outputs a high level to drive the microprocessing unit MPU to start normally.

2. The voltage detection circuit of the embedded motherboard according to claim 1, characterized in that: The watchdog circuit includes a first AND gate, a second AND gate, a first buffer, a reset monitor, and a third AND gate which are connected in sequence, wherein the input end of the first AND gate is connected to the IO port of the microcontroller unit MCU, the two input ends of the second AND gate are respectively connected to the output signal of the first AND gate and the ground signal, the output signal of the first buffer is connected to the MR interface of the reset monitor, the three input ends of the third AND gate are respectively connected to the output signal of the reset monitor, the reset signal of the power management integrated circuit PMIC, and the interface reset signal, and the output end of the third AND gate is connected to the POR interface of the microprocessing unit MPU.

3. The voltage detection circuit of the embedded motherboard according to claim 2, characterized in that: When the MCU of the microcontroller unit detects the voltage of the power management integrated circuit PMIC, the level signal of the input end of the first AND gate of the watchdog circuit is low level, and the first AND gate outputs a low level signal. The signals at the two input terminals of the second AND gate are a high level signal and a low level signal. The second AND gate outputs a low level signal, and the signal output by the second AND gate is input into the reset monitor after passing through the first buffer. The reset monitor outputs a low level signal and a reset signal, and the reset signal is sent to the microprocessing unit MPU so that the microprocessing unit MPU is always in a reset state.

4. The voltage detection circuit of the embedded motherboard according to claim 2, characterized in that: Once the microcontroller unit MCU completes the detection of all voltages and the results of all voltage detections are normal, the IO pins connected to the watchdog circuit are all input with a high level, the first AND gate outputs a high level signal, the signals at the two input ends of the second AND gate are both high level signals, the second AND gate also outputs a high level signal, and the signal output by the second AND gate passes through the first buffer and then input into the reset monitor, so that the reset monitor outputs a working signal of a high level signal, and the working signal is sent to the microprocessing unit MPU so that the MPU can start normally.

5. The voltage detection circuit of the embedded motherboard according to claim 2, characterized in that: The nRst_REQ interface of the microprocessing unit MPU sends a reset request signal to the microcontroller unit MCU. When the nRst_REQ interface of the microprocessing unit MPU does not send a reset request signal to the microcontroller unit MCU, the ground signal connected to the input terminal of the second AND gate is a high level signal.

6. The voltage detection circuit of the embedded motherboard according to claim 1, characterized in that: The microcontroller unit MCU sends a power management integrated circuit power standby signal and a power management integrated circuit power start signal to the power management integrated circuit PMIC, and the power management integrated circuit PMIC sends a power management integrated circuit power normal signal and a power management integrated circuit error warning signal to the microcontroller unit MCU.

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