Comprehensive control device of radar transmitting and receiving system
By designing a comprehensive control device for radar transceiver system including central processing module, differential conversion module and crystal oscillator conversion module, the complex and dispersed radar transceiver system testing problem is solved, and the comprehensive control and testing efficiency of the system are improved.
Patent Information
- Application Number
- CN202420645307.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-04-15
- Estimated Expiration
- 2034-03-29
AI Technical Summary
The radar transmission and reception system is huge in size, and the functional tests of each sub-system are scattered. The replacement of test ports and cables is frequent and complex, which is very easy to omission and confuse.
A comprehensive control device for radar transceiver system is designed, including a central processing module, a differential conversion module and a crystal oscillator conversion module. The timing signals and control signals are generated through the FPGA chip, and the signal anti-interference ability is improved through the differential conversion module, and flexible clock switching is provided through the crystal oscillator conversion module.
The comprehensive control of the radar transmission and reception system is realized, the convenience and efficiency of testing are improved, the consumption of testing resources is reduced, and omissions and confusion are avoided.
Smart Images
Figure CN222762264U_ABST
Abstract
Description
Technical Field
[0001] The disclosed embodiments relate to the technical field of integrated signal control, and in particular to an integrated control device for a radar transceiver system. Background Art
[0002] At present, the timing signals required for the functional debugging of subsystems such as frequency synthesizers, receivers and transmitters in radar transceiver systems need to be collected from the signal processing system and transmitted over long distances through test cables. The process is complicated, time-consuming and labor-intensive, and the signal distortion rate is high. At the same time, the control signals based on the communication protocol are scattered, and it is impossible to centrally and automatically control the transmission and reception efficiently.
[0003] However, the transceiver system is large in size, the functional tests of each subsystem are scattered, and the replacement of test ports and cables is frequent and complicated, which is very easy to cause omissions and confusion. Utility Model Content
[0004] In order to avoid the shortcomings of the prior art, the present invention provides a radar transceiver system integrated control device to solve the problems in the prior art such as the bulky size of the transceiver system, the scattered functional tests of each subsystem, the frequent and complicated replacement of test ports and cables, and easy omissions and confusion.
[0005] According to an embodiment of the present disclosure, a radar transceiver system integrated control device is provided, the device comprising:
[0006] A shell is provided with a central processing module, a differential conversion module and a crystal oscillator conversion module, and a first blind-mate connector and a second blind-mate connector are provided on the side wall of the shell. The central processing module is electrically connected to the differential conversion module, and the differential conversion module is electrically connected to the crystal oscillator conversion module, the first blind-mate connector and the second blind-mate connector respectively, and the crystal oscillator conversion module is electrically connected to the second blind-mate connector.
[0007] Furthermore, the central processing module includes:
[0008] FPGA chip, RS232 driver chip, voltage controller, crystal oscillator and storage chip;
[0009] Wherein, the FPGA chip is electrically connected to the RS232 driver chip, the voltage controller, the crystal oscillator and the storage chip respectively.
[0010] Furthermore, the differential conversion module includes:
[0011] Quad-channel digital isolators, quad low-power differential line drivers, and isolated gate drivers;
[0012] Among them, the four-channel digital isolator is electrically connected to the FPGA chip respectively; the four-channel digital isolator, the four-way low-power differential line driver and the isolated gate driver are electrically connected in sequence, and the isolated gate driver is electrically connected to the first blind-mate connector.
[0013] Furthermore, the crystal oscillator conversion module includes:
[0014] Beyond-the-rail comparators, frequency dividers, digital signal isolation modules and logic gate chips;
[0015] Among them, the beyond-swing comparator, the frequency divider, the digital signal isolation module, and the logic gate chip are electrically connected in sequence, the beyond-swing comparator is electrically connected to the second blind-mate connector, and the logic gate chip is electrically connected to the FPGA chip.
[0016] Furthermore, a frequency synthesizer SMA test interface is also provided on the side wall of the housing, and the frequency synthesizer SMA test interface includes a 10MHz coherent signal port, a 32MHz timing reference signal port and a 60MHz phase detection signal port;
[0017] Among them, the 10MHz coherent signal port, the 32MHz timing reference signal port and the 60MHz phase detection signal port are all connected to the second blind mate connector, and the 10MHz coherent signal port, the 32MHz timing reference signal port and the 60MHz phase detection signal port are all used to connect to the frequency synthesizer.
[0018] Furthermore, a receiver BNC test interface is also provided on the side wall of the housing, and the receiver BNC test interface includes an I-way working port, a Q-way working port, an I-way test port and a Q-way test port;
[0019] Among them, the I-way working port, the Q-way working port, the I-way test port and the Q-way test port are connected to the first blind-mate connector, and the I-way working port, the Q-way working port, the I-way test port and the Q-way test port are all used to connect to a receiver.
[0020] Furthermore, a transmission trigger pulse TR test port is provided on the side wall of the shell, and the transmission trigger pulse TR test port is used to be electrically connected to the FPGA chip.
[0021] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:
[0022] In the embodiment of the present disclosure, through the above-mentioned radar transceiver system integrated control device, on the one hand, the embedded design of the FPGA chip is realized through the central processing module, and the FPGA chip can generate five types of timing signals, namely, the transmission trigger pulse TR, the transmission trigger pulse, the modulation pulse, the STC trigger pulse and the wave speed dwell pulse, and send the frequency code and the tracking / search mode switching control signal to the frequency synthesizer and the receiver. The differential conversion module realizes the differential form conversion of the signal generated by the central processing module, improves the signal anti-interference ability, and reduces the common mode suppression phenomenon of the signal; the crystal oscillator conversion module provides the flexible switching of different clocks required for the operation of each device of the central processing module. On the other hand, the device uses the FPGA chip to generate the timing signal required by the transceiver system and the control signal sent to the frequency synthesizer and the receiver, and transmits the transceiver system working mode and control command through the host computer serial port. At the same time, the test interface of the frequency synthesizer and the receiver is provided, which greatly improves the convenience of the test, realizes the comprehensive control between the frequency synthesizer, the receiver and the transmitter of the transceiver system, thereby saving test resources and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0024] Figure 1 A front view of a radar transceiver system integrated control device in an exemplary embodiment of the present disclosure is shown;
[0025] Figure 2 A side view showing a radar transceiver system integrated control device in an exemplary embodiment of the present disclosure;
[0026] Figure 3 A schematic diagram showing the basic principle of a radar transceiver system integrated control device in an exemplary embodiment of the present disclosure is shown;
[0027] Figure 4 A connection diagram of a central processing module in an exemplary embodiment of the present disclosure is shown;
[0028] Figure 5 A connection diagram of a differential conversion module in an exemplary embodiment of the present disclosure is shown;
[0029] Figure 6 A connection diagram of a crystal oscillator conversion module in an exemplary embodiment of the present disclosure is shown.
[0030] In the figure, 100, housing; 200, frequency synthesizer SMA test interface; 201, 10MHz coherent signal port; 202, 32MHz timing reference signal port; 203, 60MHz phase detection signal port; 300, receiver BNC test interface; 301, I-way working port; 302, Q-way working port; 303, I-way test port; 304, Q-way test port; 400, TR interface; 500, first blind-mate connector; 600, second blind-mate connector; 700, spare interface. DETAILED DESCRIPTION
[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0032] In addition, the accompanying drawings are only schematic illustrations of the embodiments of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities.
[0033] This example embodiment provides a radar transceiver system integrated control device. Figure 1 and Figure 2 As shown in , the radar transceiver system integrated control device may include:
[0034] The shell 100 is provided with a central processing module, a differential conversion module and a crystal oscillator conversion module. A first blind-mate connector 500 and a second blind-mate connector 600 are provided on the side wall of the shell 100. The central processing module is electrically connected to the differential conversion module. The differential conversion module is electrically connected to the crystal oscillator conversion module, the first blind-mate connector 500 and the second blind-mate connector 600 respectively. The crystal oscillator conversion module is electrically connected to the second blind-mate connector 600.
[0035] Specifically, Figure 1 and Figure 2As shown, a frequency synthesizer SMA test interface 200 is also provided on the side wall of the shell 100, and the frequency synthesizer SMA test interface 200 includes a 10MHz coherent signal port 201, a 32MHz timing reference signal port 202 and a 60MHz phase detection signal port 203; wherein, the 10MHz coherent signal port 201, the 32MHz timing reference signal port 202 and the 60MHz phase detection signal port 203 are all connected to the second blind-mate connector 600, and the 10MHz coherent signal port 201, the 32MHz timing reference signal port 202 and the 60MHz phase detection signal port 203 are all used to connect to the frequency synthesizer. A receiver BNC test interface 300 is also provided on the side wall of the housing 100, and the receiver BNC test interface 300 includes an I-way working port 301, a Q-way working port 302, an I-way test port 303 and a Q-way test port 304; wherein the I-way working port 301, the Q-way working port 302, the I-way test port 303 and the Q-way test port 304 are connected to the first blind-mate connector 500, and the I-way working port 301, the Q-way working port 302, the I-way test port 303 and the Q-way test port 304 are all used to connect to the receiver.
[0036] Through the above radar transceiver system integrated control device, on the one hand, the embedded design of FPGA chip is realized through the central processing module, and the FPGA chip can generate five types of timing signals, namely, transmission trigger pulse TR, transmission trigger pulse, modulation pulse, STC trigger pulse and wave speed dwell pulse, and send the frequency code and tracking / search mode switching control signal to the frequency synthesizer and receiver. The differential conversion module realizes the differential form conversion of the signal generated by the central processing module, improves the signal anti-interference ability, and reduces the common mode suppression phenomenon of the signal; the crystal oscillator conversion module provides the flexible switching of different clocks required for the operation of each device of the central processing module. On the other hand, the device uses the FPGA chip to generate the timing signal required by the transceiver system and the control signal sent to the frequency synthesizer and receiver, and transmits the transceiver system working mode and control command through the host computer serial port. At the same time, the test interface of the frequency synthesizer and the receiver is provided, which greatly improves the convenience of the test, realizes the comprehensive control between the frequency synthesizer, receiver and transmitter of the transceiver system, thereby saving test resources and improving test efficiency.
[0037] Next, we will refer to Figures 1 to 6 Each part of the above-mentioned radar transceiver system integrated control device in this exemplary embodiment is described in more detail.
[0038] In one embodiment, Figure 3As shown, the central processing module and the differential conversion module complete signal exchange through a small rectangular electrical connector; the differential conversion module and the crystal oscillator conversion module complete signal exchange through a small rectangular electrical connector. The differential conversion module is electrically connected to the first blind mate connector 500 (i.e., blind mate connector A) and the second blind mate connector 600 (i.e., blind mate connector B), respectively, and the crystal oscillator conversion module is electrically connected to the second blind mate connector 600.
[0039] The central processing module communicates with the host computer by converting the serial interface to a blind-mate connector to realize the working mode control. The central processing module takes the FPGA chip as the core and uses the module instantiation method to form a data communication system. With the help of the host computer sending the frequency and bandwidth data packets of the 5 types of timing signals to be generated and the data format of the control signal, the data packet received by the lower computer FPGA is parsed. At the same time, the valid data is extracted as the input of the signal generation module, and 5 types of timing signals and the frequency matching code and tracking / search mode switching control signal sent to the frequency synthesizer and receiver are generated, and finally output at the IO pin of the FPGA. In addition, the FPGA starts the counter counting after receiving the valid data, and sends the count value to the host computer in real time in the form of a data packet to realize the data communication between the host computer and the lower computer.
[0040] The differential conversion module is connected to the central processing module through a plug-in small rectangular electrical connector. The five types of timing signals generated by the central processing module and the frequency code and tracking / search mode switching control signal sent to the frequency synthesizer and receiver are transferred to the differential conversion module through a small rectangular electrical connector. The noise interference is isolated by a four-channel digital isolator, and then converted into differential signals by a four-way differential line driver, and then transferred to the rectangular electrical connector for output through an RS232 interface chip. At the same time, the differential conversion module improves the signal's anti-interference ability and common-mode suppression.
[0041] The crystal oscillator conversion module divides the 10MHz coherent signal, 32MHz timing reference signal and 60MHz phase detection signal input by the frequency synthesizer through the frequency division circuit, and sends them to the central processing module through the differential conversion module via a small rectangular electrical connector, thereby realizing the conversion between the internal clock of each counting module and the external clock.
[0042] In one embodiment, the central processing module includes: an FPGA chip, an RS232 driver chip, a voltage controller, a crystal oscillator and a storage chip; wherein the FPGA chip is electrically connected to the RS232 driver chip, the voltage controller, the crystal oscillator and the storage chip respectively.
[0043] Specifically, the central processing module includes FPGA chip, RS232 driver chip, voltage controller, crystal oscillator, storage chip and peripheral circuits, etc. The host computer control command is input into the central processing module through the USB port, and the serial port communication is realized through the RS232 driver chip data conversion. The serial port I / O data is sent to the corresponding pin of the FPGA chip to realize the data transmission between the FPGA chip and the host computer; the voltage controller is essentially a voltage conversion circuit, which converts the +5V power connected to the USB port into +3.3V and 1.2V and then connects to the corresponding pin of the FPGA chip to power the FPGA chip: the 50MHz crystal oscillator is connected to the corresponding pin of the FPGA chip to provide a clock reference for the FPGA chip.
[0044] In one embodiment, the differential conversion module includes: a four-channel digital isolator, a four-way low-power differential line driver and an isolated gate driver; wherein the four-channel digital isolator is electrically connected to the FPGA chip respectively; the four-channel digital isolator, the four-way low-power differential line driver and the isolated gate driver are electrically connected in sequence, and the isolated gate driver is electrically connected to the first blind-mate connector 500.
[0045] Specifically, the timing / control signals generated by the central processing module FPGA chip, including the four-channel digital isolator, four-way low-power differential line driver, isolated gate driver and peripheral circuit, are transferred to the differential conversion module through the rectangular electrical connector. The signal is first isolated from noise interference by the four-channel digital isolator. Then, the signal is converted into differential form by the four-way low-power differential line driver and isolated gate driver.
[0046] In one embodiment, the crystal oscillator conversion module includes: an over-swing comparator, a frequency divider, a digital signal isolation module and a logic gate chip; wherein the over-swing comparator, the frequency divider, the digital signal isolation module and the logic gate chip are electrically connected in sequence, the over-swing comparator is electrically connected to the second blind-mate connector 600, and the logic gate chip is electrically connected to the FPGA chip.
[0047] Specifically, it includes an over-swing comparator, a frequency divider, a digital signal isolation module, a logic gate chip, and peripheral circuits, etc. The second blind-mate connector 600 sends the 10MHz, 32MHz, and 60MHz reference signals from the frequency synthesizer to the crystal oscillator conversion module, divides the three reference signals through the over-swing comparator and the frequency divider, and then passes through the digital signal isolation module, the logic gate chip, and the peripheral circuits through the rectangular connector and finally sends them to the clock access pin of the central processing module FPGA chip, providing different clock references for each functional module in the FPGA chip.
[0048] In a specific embodiment, three frequency synthesizer SMA test interfaces 200 for a 10MHz coherent signal, a 32MHz timing reference signal, and a 60MHz phase detection signal are provided on the front panel of the housing 100; a transmission trigger pulse TR test interface XS01 (i.e., a TR interface 400) is provided; receiver I and Q two-way noise working signal test interfaces XS02 and XS03 (i.e., an I-way working port 301 and a Q-way working port 302) are provided; and receiver I and Q two-way noise test signal test interfaces XS04 and XS05 (i.e., an I-way test port 303 and a Q-way test port 304) are provided.
[0049] In addition, a spare interface 700 is provided on the front panel of the housing 100 .
[0050] In a specific embodiment, a 32-pin blind-mate connector socket XS09A (i.e., the first blind-mate connector 500) is provided on the rear panel of the shell 100, which is used to transfer DC ±5V power supply, I / Q two-way working / test noise signals, serial port working mode commands, modulated differential pulses and wave speed dwell pulses.
[0051] In a specific embodiment, the DC ±5V power supply of the blind-mate connector socket XS09A is derived from the frequency synthesizer and receiver power supply; the I / Q two-way working / test noise signals are generated by the receiver; the serial port working mode control is derived from the host computer; the modulated differential pulse is provided to the frequency synthesizer, which is used for the frequency synthesizer to complete the pulse modulation of the excitation signal; the wave speed dwell pulse is used for the frequency synthesizer frequency hopping.
[0052] In a specific embodiment, a 32-pin blind-mate connector socket XS09B (i.e., the second blind-mate connector 600) is provided on the rear panel of the shell 100, which is used to transfer the frequency matching code and tracking / search enable signal, the transmission trigger pulse TR, the STC trigger differential signal, the 60MHz phase detection signal, the 10MHz coherent signal and the 32MHz timing reference signal.
[0053] In a specific embodiment, the frequency matching code and tracking / search enable signal transferred by the blind-mate connector socket XS09B are sent by the integrated control device to the frequency synthesizer and the receiver respectively; the transmission trigger differential pulse is provided to the transmitter control module for internal timing synchronization of the transmitter and the modulated pulse transmitted by the excitation signal amplification; the STC trigger differential signal is provided to the high-frequency part of the receiver for completing the receiver noise short-range gain control; the 60MHz phase detection signal, 10MHz coherent signal and 32MHz timing reference signal are introduced by the frequency synthesizer.
[0054] In a specific embodiment, the differential conversion module is located in the middle layer, and is connected to the central processing module of the upper layer and the crystal oscillator conversion module of the lower layer through a small rectangular electrical connector. The central processing module uses a serial communication interface to transfer data to the first blind mate connector 500; the data finally generated by the differential conversion module is transferred to the first blind mate connector 500 and the second blind mate connector 600 through the DB15-pin and DB25-pin rectangular electrical connectors, and sent to different subsystems of the receiving system respectively; the crystal oscillator conversion module receives the 10MHz coherent signal, 32MHz timing reference signal and 60MHz phase detection signal input by the frequency synthesizer through the second blind mate connector 600 to the frequency synthesizer SMA test interface 200, and the signal is divided and finally sent to the central processing module through the small rectangular electrical connector through the middle layer differential conversion module to participate in the calculation. In this embodiment, the upper computer control line is connected to the first blind mate connector 500, and the lower computer FPGA chip is pre-programmed and then written into the chip through the simulator.
[0055] Specifically, the central processing module of this embodiment uses the FPGA chip as the core, and utilizes the module instantiation method to form a data communication system. With the help of the host computer, the frequency, bandwidth data packets and data formats of the control signals of the five types of timing signals to be generated are sent, and the data packets received by the lower computer FPGA are used to parse the data. At the same time, valid data is extracted as the input of the signal generation module, and five types of timing signals and frequency matching codes and tracking / search mode switching control signals sent to the frequency synthesizer and receiver are generated, and finally output at the IO pin of the FPGA. In addition, the FPGA starts counting the counter after receiving valid data, and sends the count value to the host computer in real time in the form of a data packet, thereby realizing data communication between the host computer and the lower computer. The specific implementation principle is as follows: Figure 4 shown.
[0056] Specifically, in this embodiment, the differential conversion module transfers the five types of timing signals generated by the central processing module and the frequency matching code and tracking / search mode switching control signal sent to the frequency synthesizer and receiver to the differential conversion module through a small rectangular electrical connector, isolates noise interference through a four-channel digital isolator, and then converts it into a differential signal through a four-way differential line driver, and then transfers it to the rectangular electrical connector for output through an RS232 interface chip. At the same time, the differential conversion module improves the signal's anti-interference ability and common-mode suppression. The specific implementation principle is as follows: Figure 5 shown.
[0057] Specifically, in this embodiment, the crystal oscillator conversion module divides the 10MHz coherent signal, 32MHz timing reference signal and 60MHz phase detection signal input by the frequency synthesizer through the frequency division circuit, and sends them to the central processing module through the small rectangular electrical connector and the differential conversion module to realize the switching between the internal clock and the external clock of each counting module. The specific implementation principle is as follows Figure 6 shown.
[0058] Specifically, Figure 1 and Figure 2 The central processing module, differential conversion module and crystal oscillator conversion module are all installed in the housing 100. The housing 100 is provided with a frequency synthesizer SMA test port on the front panel, including: 10MHz coherent signal port 201, 32MHz timing reference signal port 202, 60MHz phase detection signal port 203, which are directly introduced by the frequency synthesizer through a blind-mate connector; the housing 100 is provided with a receiver BNC test port on the front panel, including: I-way working port 301, Q-way working port 302, I-way test port 303 and Q-way test port 304, which are directly introduced by the receiver through a blind-mate connector; the housing 100 is provided with a transmission trigger pulse TR test port, which is generated by the central processing module.
[0059] Specifically, Figure 1 and Figure 2 As shown, in order to ensure the stability of the signal reception and transmission of the integrated control device, a blind-mate connector port is provided on the rear panel, and a first blind-mate connector 500 is embedded, which is used to access the power supply of the frequency synthesizer and the receiver, communicate with the host computer, and is used for pulse modulation and frequency hopping of the frequency synthesizer excitation signal; a second blind-mate connector 600 is embedded, which is used to send frequency matching codes and tracking / search mode switching control commands to the frequency synthesizer and the receiver, and at the same time receive the 10MHz coherent signal, 32MHz timing reference signal and 60MHz phase detection signal input by the frequency synthesizer.
[0060] The control of this embodiment is carried out in a combination of an upper computer and a lower computer. The upper computer control interface presets the working mode of the integrated control device, and sends the frequency and bandwidth data packets of the types of timing signals to be generated, as well as the data format of the control signal. The lower computer FPGA receives the data packets and parses the data to complete the embedded offline programming. The central processing module completes the generation of various types of timing signals and sends the frequency code and tracking / search mode switching control signals to the frequency synthesizer and the receiver; the generated timing signal and the control signal to be sent are converted into differential form through the differential conversion module, while improving the signal's anti-interference ability and common mode suppression; the crystal oscillator conversion module sends the clock signal to the central processing module through the frequency division circuit to realize the switching between the internal clock and the external clock of each counting module.
[0061] The five types of timing signals generated by the device save the trouble of collecting timing signals from the signal processing system during system debugging; the frequency matching code and tracking / search mode switching control signal sent by the device to the frequency synthesizer and receiver realizes the automatic control of the enable signal, eliminating the need for manual field operation switching. The test port introduced through the panel of the device realizes the convenient testing of frequency synthesizer and receiver test items, greatly improving the test efficiency.
[0062] Through the above radar transceiver system integrated control device, on the one hand, the embedded design of FPGA chip is realized through the central processing module, and the FPGA chip can generate five types of timing signals, namely, transmission trigger pulse TR, transmission trigger pulse, modulation pulse, STC trigger pulse and wave speed dwell pulse, and send the frequency code and tracking / search mode switching control signal to the frequency synthesizer and receiver. The differential conversion module realizes the differential form conversion of the signal generated by the central processing module, improves the signal anti-interference ability, and reduces the common mode suppression phenomenon of the signal; the crystal oscillator conversion module provides the flexible switching of different clocks required for the operation of each device of the central processing module. On the other hand, the device uses the FPGA chip to generate the timing signal required by the transceiver system and the control signal sent to the frequency synthesizer and receiver, and transmits the transceiver system working mode and control command through the host computer serial port. At the same time, the test interface of the frequency synthesizer and the receiver is provided, which greatly improves the convenience of the test, realizes the comprehensive control between the frequency synthesizer, receiver and transmitter of the transceiver system, thereby saving test resources and improving test efficiency.
[0063] It should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like in the above description indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.
[0064] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0065] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0066] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0067] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.
[0068] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A radar transceiver system integrated control device, characterized in that: The device includes: A shell is provided with a central processing module, a differential conversion module and a crystal oscillator conversion module, and a first blind-mate connector and a second blind-mate connector are provided on the side wall of the shell. The central processing module is electrically connected to the differential conversion module, and the differential conversion module is electrically connected to the crystal oscillator conversion module, the first blind-mate connector and the second blind-mate connector respectively, and the crystal oscillator conversion module is electrically connected to the second blind-mate connector.
2. The radar transceiver system integrated control device according to claim 1, characterized in that: The central processing module comprises: FPGA chip, RS232 driver chip, voltage controller, crystal oscillator and storage chip; Wherein, the FPGA chip is electrically connected to the RS232 driver chip, the voltage controller, the crystal oscillator and the storage chip respectively.
3. The radar transceiver system integrated control device according to claim 2, characterized in that: The differential conversion module comprises: Quad-channel digital isolators, quad low-power differential line drivers, and isolated gate drivers; Among them, the four-channel digital isolator is electrically connected to the FPGA chip respectively; the four-channel digital isolator, the four-way low-power differential line driver and the isolated gate driver are electrically connected in sequence, and the isolated gate driver is electrically connected to the first blind-mate connector.
4. The radar transceiver system integrated control device according to claim 3, characterized in that: The crystal oscillator conversion module comprises: Beyond-the-rail comparators, frequency dividers, digital signal isolation modules and logic gate chips; Among them, the beyond-swing comparator, the frequency divider, the digital signal isolation module, and the logic gate chip are electrically connected in sequence, the beyond-swing comparator is electrically connected to the second blind-mate connector, and the logic gate chip is electrically connected to the FPGA chip.
5. The radar transceiver system integrated control device according to claim 4, characterized in that: A frequency synthesizer SMA test interface is also provided on the side wall of the housing, and the frequency synthesizer SMA test interface includes a 10MHz coherent signal port, a 32MHz timing reference signal port and a 60MHz phase detection signal port; Among them, the 10MHz coherent signal port, the 32MHz timing reference signal port and the 60MHz phase detection signal port are all connected to the second blind mate connector, and the 10MHz coherent signal port, the 32MHz timing reference signal port and the 60MHz phase detection signal port are all used to connect to the frequency synthesizer.
6. The radar transceiver system integrated control device according to claim 5, characterized in that: A receiver BNC test interface is also provided on the side wall of the housing, and the receiver BNC test interface includes an I-way working port, a Q-way working port, an I-way test port and a Q-way test port; Among them, the I-way working port, the Q-way working port, the I-way test port and the Q-way test port are connected to the first blind-mate connector, and the I-way working port, the Q-way working port, the I-way test port and the Q-way test port are all used to connect to a receiver.
7. The radar transceiver system integrated control device according to claim 6, characterized in that: A transmission trigger pulse TR test port is also provided on the side wall of the shell, and the transmission trigger pulse TR test port is used to be electrically connected to the FPGA chip.