Microprocessor monitoring circuit and electronic equipment

Abstract

The utility model provides a microprocessor monitoring circuit and an electronic device, the microprocessor monitoring circuit comprises: a D trigger and a time delay circuit, the D trigger is configured to release a reset state when a first input end receives a wake-up waiting signal output by a microprocessor, and to release the reset state when a second input end receives a wake-up signal; outputting a second potential signal opposite to the first potential signal through a trigger signal output end; and the delay circuit is configured to execute timing when the trigger signal input end receives a second potential signal, and output a reset signal through the delay signal output end after the timing time exceeds a delay time interval, so that the microprocessor is reset or restarted. The microprocessor monitoring circuit can be applied to low-power-consumption application scenes.

Description

Technical Field

[0001] The utility model relates to the technical field of microprocessors, in particular to a microprocessor monitoring circuit and electronic equipment. Background Art

[0002] Generally, electronic devices are equipped with a microprocessor (English: Microprocessor, abbreviated as μP or uP), which usually refers to a programmable special integrated circuit, all of which are miniaturized into one or several integrated circuits. Among them, electronic devices use batteries to power the microprocessor.

[0003] In the related art, when the microprocessor is in a low-power scenario such as not working, it is put into a sleep state to minimize its power consumption and extend the battery life. When a wake-up signal to the microprocessor is detected, the microprocessor is awakened from the sleep state and starts to work normally.

[0004] However, the microprocessor may be disturbed due to various reasons when it wakes up from the sleep state and returns to the normal working state, resulting in a wake-up failure and causing the microprocessor to freeze, which is unacceptable for some application scenarios with high reliability requirements.

[0005] Therefore, the prior art proposes a microprocessor monitoring circuit based on a watchdog chip. The microprocessor feeds the watchdog regularly. When the microprocessor is stuck and cannot be fed in time, the watchdog chip times out, triggering the microprocessor to reset or power off and restart to ensure its normal operation.

[0006] However, this method cannot be implemented in low-power application scenarios, because the microprocessor enters a sleep state and the watchdog cannot be fed, which will mistakenly trigger the reset of the watchdog, causing the low-power scenario to fail.

[0007] Therefore, the use scenarios of microprocessor monitoring circuits based on watchdog chips are limited.

[0008] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Utility Model Content

[0009] In view of the problems in the prior art, the purpose of the present invention is to provide a microprocessor monitoring circuit, which overcomes the technical problem of limited usage scenarios of the microprocessor monitoring circuit in the related art.

[0010] The embodiment of the present disclosure provides a microprocessor monitoring circuit, which includes: a D flip-flop and a delay circuit;

[0011] The D flip-flop has a first input terminal, a second input terminal and a trigger signal output terminal, the delay circuit has a trigger signal input terminal and a delay signal output terminal, the trigger signal output terminal is coupled to the trigger signal input terminal, the first input terminal is configured to couple to the microprocessor, the second input terminal is configured to receive a wake-up signal to the microprocessor, and the delay signal output terminal is configured to couple to a reset pin of the microprocessor;

[0012] The D flip-flop is configured as:

[0013] When the first input terminal receives the wake-up state signal output by the microprocessor, the reset state is maintained, and the first potential signal is output through the trigger signal output terminal;

[0014] When the first input terminal receives a wake-up waiting signal output by the microprocessor, the reset state is released, and when the second input terminal receives a wake-up signal, a second potential signal which is inverted with the first potential signal is output through the trigger signal output terminal;

[0015] The delay circuit is configured as:

[0016] When the trigger signal input terminal receives the first potential signal, the delay signal output terminal outputs a holding signal to control the microprocessor to maintain the current state;

[0017] When the trigger signal input terminal receives the second potential signal, timing is performed, and after the timing time exceeds the delay time interval, a reset signal is output through the delay signal output terminal to reset or restart the microprocessor.

[0018] Optionally, the trigger signal output terminal is a reverse output terminal;

[0019] The delay circuit includes a resistor, a first capacitor and a diode. The resistor is connected in parallel with the diode. The positive electrode of the diode is configured as a trigger signal input terminal, the negative electrode of the diode is configured as a delay signal output terminal, and the first capacitor is coupled between the delay signal output terminal and the ground terminal.

[0020] Optionally, the first output terminal is a unidirectional output terminal;

[0021] The delay circuit includes a first power supply monitoring reset chip and a second capacitor:

[0022] The first power supply monitoring reset chip has a reset input pin, a capacitor pin and a reset pin. The reset input pin is configured as a trigger signal input terminal, the reset pin is used as a delay signal output terminal, and the second capacitor is coupled between the capacitor pin and the ground terminal.

[0023] Optionally, the first capacitor is an adjustable capacitor.

[0024] Optionally, the microprocessor monitoring circuit further comprises:

[0025] An inverter having a phase input terminal and a phase output terminal, the phase input terminal is connected to the delay signal output terminal, and the phase output terminal is configured to be coupled to a reset pin of the microprocessor;

[0026] The delay circuit is configured to couple the delay signal output terminal to a reset pin of the microprocessor through the inverter, so as to output the holding signal or the control signal through the phase output terminal of the inverter.

[0027] Optionally, the microprocessor monitoring circuit further comprises: a voltage monitoring circuit having a voltage sensing pin and a reset signal output terminal;

[0028] The voltage monitoring circuit is configured as:

[0029] The power supply of the microprocessor is connected through the voltage sensing pin to sense the power supply voltage, and when the power supply voltage is abnormal, a reset signal or a power cut-off signal is output to the microprocessor through the reset signal output terminal.

[0030] Optionally, the voltage monitoring circuit further has a reset input terminal, and the reset input terminal is connected to the delay signal output terminal;

[0031] The voltage monitoring circuit is configured as:

[0032] The hold signal and reset signal are output through the reset signal output terminal.

[0033] Optionally, the voltage monitoring circuit includes a second power supply monitoring reset chip, a reset input pin of the second power supply monitoring reset chip is configured as a delay signal input terminal, and a reset pin is configured as a reset signal output terminal.

[0034] Optionally, the first input terminal is a clock signal pin, and the second input terminal is a reset pin.

[0035] The disclosed embodiment also provides an electronic device, including a microprocessor and the microprocessor monitoring circuit of any one of the above embodiments.

[0036] The microprocessor monitoring circuit and electronic equipment of the utility model have the following advantages:

[0037] The microprocessor monitoring circuit includes: a D trigger and a delay circuit, the D trigger is configured to: maintain a reset state when the first input terminal receives a wake-up state signal output by the microprocessor, and output a first potential signal through a trigger signal output terminal; release the reset state when the first input terminal receives a wake-up wait signal output by the microprocessor, and when the second input terminal receives a wake-up signal, output a second potential signal that is inverted with the first potential signal through the trigger signal output terminal; the delay circuit is configured to: when the trigger signal input terminal receives the first potential signal, output a hold signal through the delay signal output terminal to control the microprocessor to maintain the current state; when the trigger signal input terminal receives the second potential signal, execute timing, and after the timing time exceeds the delay time interval, output a reset signal through the delay signal output terminal to reset or restart the microprocessor. The microprocessor monitoring circuit of this embodiment can cope with the reset or restart of the microprocessor stuck state, so as to ensure that the microprocessor enters the normal working state in time and avoid the failure of the electronic equipment for a long time. In particular, compared to the monitoring circuit in watchdog mode, even in low-power application scenarios, the monitoring circuit of this embodiment will not mistakenly trigger the microprocessor to switch to working state, thereby enabling the microprocessor to maintain a low-power state. Therefore, the microprocessor monitoring circuit of this embodiment has a wide range of applicable scenarios and can ensure the normal implementation of the microprocessor low-power scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objectives and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0039] Figure 1 A circuit structure diagram showing a microprocessor monitoring circuit according to an embodiment of the present disclosure.

[0040] Figure 2 exhibit Figure 1 The specific circuit diagram of the microprocessor monitoring circuit is shown.

[0041] Figure 3 A specific circuit diagram of another microprocessor monitoring circuit provided by an embodiment of the present disclosure is shown.

[0042] Figure 4 A circuit structure diagram of another microprocessor monitoring circuit provided by an embodiment of the present disclosure is shown.

[0043] Figure 5 exhibit Figure 4 The specific circuit diagram of the microprocessor monitoring circuit is shown.

[0044] Figure 6 A specific circuit diagram of another microprocessor monitoring circuit provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] In addition, the accompanying drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0047] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined. Therefore, the actual execution order may be changed according to the actual situation.

[0048] Figure 1 The circuit structure diagram of the microprocessor monitoring circuit provided by the embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the microprocessor monitoring circuit includes: a D trigger 1 and a delay circuit 2;

[0049] The D trigger 1 has a first input terminal 11, a second input terminal 12 and a trigger signal output terminal 13, the delay circuit 2 has a trigger signal input terminal 21 and a delay signal output terminal 22, the trigger signal output terminal 13 is coupled to the trigger signal input terminal 21, the first input terminal 11 is configured to connect to a microprocessor, the second input terminal 12 is configured to receive a wake-up signal to the microprocessor, and the delay signal output terminal 22 is configured to couple to a reset pin of the microprocessor;

[0050] D flip-flop 1 is configured as:

[0051] When the first input terminal 11 receives the wake-up state signal output by the microprocessor, the reset state is maintained, and the first potential signal is output through the trigger signal output terminal 13;

[0052] When the first input terminal 11 receives a wake-up waiting signal output by the microprocessor, the reset state is released, and when the second input terminal 12 receives a wake-up signal, a second potential signal which is inverted with the first potential signal is output through the trigger signal output terminal 13;

[0053] Delay circuit 2 is configured as:

[0054] When the trigger signal input terminal 21 receives the first potential signal, the delay signal output terminal 22 outputs a holding signal to control the microprocessor 3 to maintain the current state;

[0055] When the trigger signal input terminal 21 receives the second potential signal, timing is performed, and after the timing time exceeds the delay time interval, a reset signal is output through the delay signal output terminal 22 to reset or restart the microprocessor.

[0056] Using the microprocessor monitoring circuit of this embodiment, when the current state of the microprocessor is a normal working state, it outputs a wake-up state signal to the D trigger 1, and the D trigger 1 is configured to be in a reset state. At this time, it is not affected by the wake-up signal, that is, regardless of whether the second input terminal 12 receives a wake-up signal, it always remains in a reset state. At this time, the trigger signal output terminal 22 maintains a first potential signal, so that the delay circuit 2 outputs a hold signal, and the microprocessor remains in a normal working state.

[0057] When the microprocessor enters the low power consumption mode of the sleep state, it outputs a wake-up waiting signal with an inverse potential to the above-mentioned wake-up state signal to the D flip-flop 1, and the D flip-flop 1 is released from the reset state. At this time, if the second input terminal 12 has not received the wake-up signal, the trigger signal output terminal 13 of the D flip-flop 1 maintains the first potential signal, the delay signal output terminal 22 of the delay circuit 2 maintains the current hold signal, and the microprocessor maintains the current sleep state.

[0058] When the D flip-flop 1 receives the wake-up signal, the trigger signal output terminal 13 of the D flip-flop 1 reverses its potential and outputs a second potential signal, triggering the delay circuit 2 to start timing;

[0059] When the microprocessor 3 is awakened within the delay time interval of the delay circuit 2 and enters the working state, it outputs a wake-up state signal to the first input terminal 11 of the D-type flip-flop 1, so that the D-type flip-flop 1 re-enters the reset state. Then, the trigger signal output terminal 13 is reset and the potential is inverted to output the first potential signal, so that the delay signal output terminal 22 of the delay circuit 2 does not undergo a potential conversion, and the hold signal is maintained, and the microprocessor maintains a normal working state.

[0060] When the timing time of the delay circuit 2 exceeds the delay time interval, and the microprocessor has not been awakened, it is considered that the microprocessor is stuck, and then the delay signal output terminal 22 reverses the potential and outputs a reset signal to control the microprocessor to reset or restart. If the microprocessor can work normally after resetting or restarting, referring to the above process, the monitoring circuit of this embodiment can keep the microprocessor working normally.

[0061] As can be seen from the above, the microprocessor monitoring circuit of this embodiment can cope with the reset or restart of the microprocessor stuck state, so as to ensure that the microprocessor enters the normal working state in time and avoid the failure of the electronic equipment for a long time. In particular, compared with the monitoring circuit of the watchdog mode, even in the low-power application scenario, the monitoring circuit of this embodiment will not mistakenly trigger the microprocessor to switch to the working state, so that the microprocessor can maintain the low-power state. Therefore, the microprocessor monitoring circuit of this embodiment has a wide range of applicable scenarios and can ensure the normal implementation of the low-power scenario of the microprocessor.

[0062] The specific implementation of the microprocessor monitoring circuit is described below in conjunction with the specific circuit structure.

[0063] like Figure 2 As shown, the D flip-flop U1 specifically includes: a D terminal, a clock terminal CLK (CLOCK), a reset terminal (CLEAR), the same-direction output terminal Q and the reverse output terminal

[0064] The D terminal always maintains a high potential, so that the D flip-flop U1 is in working state;

[0065] Clear to zero As a first input terminal 11, configured to be coupled to a microprocessor;

[0066] The clock terminal CLK is used as the second input terminal 12 and is configured as a receiving terminal of a wake-up signal WAKE of the microprocessor;

[0067] Reverse output terminal Can be used as trigger signal output terminal 13.

[0068] In this embodiment, when the reset terminal When receiving the low level corresponding to the wake-up state signal D_CLEAR, the D flip-flop U1 is cleared and is in the reset state. The terminal outputs high level;

[0069] On the contrary, when the reset terminal When the D flip-flop U1 receives the high level corresponding to the wake-up wait signal, the D flip-flop U1 is released from the reset state. At this time, when the clock terminal CLK receives the wake-up signal WAKE, the reverse output terminal Output low level.

[0070] In an optional implementation, the delay circuit 2 includes:

[0071] Resistor R1, first capacitor C1 and diode D1, resistor R1 and diode D1 are connected in parallel, the positive electrode P of diode D1 is configured as trigger signal input terminal 21, the negative electrode N of diode D1 is configured as delay signal output terminal 22, and the first capacitor C1 is coupled between the delay signal output terminal 22 and the ground terminal GND.

[0072] The working principle of the microprocessor monitoring circuit of this embodiment is described as follows:

[0073] When the microprocessor is working normally, the wake-up state signal D_CLEAR output by it is low level, the D flip-flop 1 is cleared, and the reverse output terminal Output high level (corresponding to the first potential signal above) WAKEUP_TRIG_N, quickly charge the first capacitor C1 through the diode D1, the reset signal UVLO (corresponding to the hold signal above) output by the delay signal output terminal 22 is high level, and the microprocessor works normally;

[0074] When the microprocessor enters sleep mode, its output wake-up state signal D_CLEAR becomes high level, so that the D flip-flop U1 is released from the reset state. At this time, the D input of the D flip-flop U1 is high, and its reverse output terminal Still maintaining the previous working state, that is, outputting a high level, the D flip-flop U1 waits for the wake-up signal WAKE.

[0075] When the wake-up signal WAKE is input to the D flip-flop U1, the inverting output terminal of the D flip-flop U1 Outputting a low level (corresponding to the second potential signal above), the first capacitor C1 is slowly discharged through the resistor R1, so that the output UVLO voltage of the delay circuit 2 is gradually reduced;

[0076] When the microprocessor wakes up abnormally, that is, the wake-up status signal D_CLEAR output by the microprocessor cannot be pulled down within the set delay time interval, the voltage on the first capacitor C1 will be released to a level lower than the reset threshold of the microprocessor through the resistor R1 (that is, for the microprocessor, UVLO becomes a low level (corresponding to the reset signal above)), thereby triggering the microprocessor to reset or power off and restart.

[0077] If the microprocessor wakes up successfully within the delay time interval, the wake-up status signal D_CLEAR output by it is pulled low, the D flip-flop U1 is cleared, and the D flip-flop U1 is configured to the reset state, and the reverse output terminal The output potential becomes high, and the first capacitor C1 is quickly charged through the diode D1, and the voltage of the first capacitor C1 increases rapidly, that is, for the microprocessor, the reset signal UVLO is always at a high level, and the microprocessor keeps working normally.

[0078] In this embodiment, the delay circuit 2 includes a first capacitor C1, a resistor R1 and a diode D1, and can be used in electronic devices with high cost restrictions and which do not need to monitor the microprocessor power supply, thereby reducing the cost.

[0079] The delay time interval of the delay circuit 2 is related to the first capacitor C1 and the resistor R1, and the capacitance value of the first capacitor C1 and the resistance value of the resistor R1 determine the range of the delay time interval. Therefore, by adjusting the first capacitor C1 and the resistor R1, the discharge speed of the first capacitor C1 can be adjusted, that is, the time delay from the triggering of the wake-up signal WAKE to the voltage of the first capacitor C1 being lower than the reset threshold of the microprocessor.

[0080] In an optional implementation manner, the first capacitor C1 may be an adjustable capacitor to set the capacitance value according to actual conditions, thereby ultimately adjusting the delay time interval.

[0081] In an optional implementation manner, the first capacitor C1 is a fixed capacitor, and the delay time interval can be adjusted by replacing the first capacitor C1 with a different capacitance value.

[0082] For example, in the above embodiment, the microprocessor is reset or restarted when triggered by a low level. In other embodiments, if the microprocessor is reset or restarted when triggered by a high level, an inverter can be connected after the delay circuit to invert the output signal of the delay circuit.

[0083] Figure 3 A microprocessor monitoring circuit according to another embodiment of the present disclosure is shown. Figure 2 The differences between the microprocessor monitoring circuit shown are:

[0084] The same-direction output terminal Q of the D flip-flop U1a serves as a trigger signal output terminal 13 and is configured to output a same-direction trigger signal WAKEUP_TRIG;

[0085] The delay circuit 2a includes a first power supply monitoring reset chip U2 and a second capacitor C2;

[0086] The first power supply monitoring reset chip U2 has a reset input pin Capacitor pin CT and reset pin Clear input pin Configured as trigger signal input 21, reset pin As the delay signal output terminal 22 , the second capacitor C2 is coupled between the capacitor pin CT and the ground terminal GND.

[0087] The microprocessor monitoring circuit also includes an inverter U3, which has a phase input terminal 1A and a phase output terminal 1Y. The phase input terminal 1A is connected to the delay signal output terminal 22, that is, the reset pin The phase output terminal 1Y is configured to be coupled to a reset pin of a microprocessor;

[0088] The delay circuit 2a is configured to couple the delay signal output terminal 22 to the reset pin of the microprocessor through the inverter U3, so as to output a hold signal or a reset signal through the phase output terminal 1Y of the inverter U3.

[0089] Figure 3 The microprocessor monitoring circuit shown operates as follows:

[0090] When the microprocessor works normally, the trigger signal WAKEUP_TRIG outputted by the same-direction output terminal Q of the D flip-flop U1a is at a low level (corresponding to the first potential signal mentioned above);

[0091] When the microprocessor is in sleep mode and the wake-up signal WAKE is input, the trigger signal WAKEUP_TRIG of the D flip-flop U1a becomes a high level (corresponding to the second potential signal above). At this time, the second capacitor C2 is charged. After exceeding the charging time of the second capacitor C2 (i.e. corresponding to the delay time interval), the reset output TIMEOUT_N of U2 will become a high level after a set time (i.e. charging time), and will become a low level after passing through the inverter U3, i.e. the reset signal UVLO, thereby resetting the microprocessor.

[0092] If the microprocessor is successfully awakened before the second capacitor C2 is fully charged (i.e. within the set delay time), it will pull D_CLEAR low, thereby resetting the output WAKEUP_TRIG of the D flip-flop U1a to a low level. At this time, TIMEOUT_N of U2 will remain at a low level, and will be high after passing through the inverter U3, i.e., UVLO still remains at a high level and will not reset the microprocessor.

[0093] In this embodiment, the first power monitoring reset chip U2 and the second capacitor C2 jointly realize the delay function. The charging time of the second capacitor C2 determines the range of the delay time interval. Therefore, the delay time can be adjusted by adjusting the size of the second capacitor C2.

[0094] In this embodiment, the inverter U3 performs an inversion conversion on the output signal of the delay signal output terminal, so that the UVLO is suitable for a microprocessor based on low potential reset. In another embodiment, if the microprocessor is based on high potential reset, the inverter may not be provided.

[0095] Figure 4 A circuit diagram showing a microprocessor monitoring circuit according to another embodiment of the present disclosure is shown. Figure 1 compared to, Figure 4 The microprocessor monitoring circuit shown also includes:

[0096] A voltage monitoring circuit 4 having a voltage sensing pin SENSE and a reset signal output terminal 41;

[0097] The voltage monitoring circuit 4 is configured as follows:

[0098] The voltage sensing pin SENSE is connected to the power supply VCC_BAT of the microprocessor to sense the power supply voltage, and when the power supply voltage is abnormal, a reset signal or a power cut-off signal is output to the microprocessor through the reset signal output terminal 41 .

[0099] When the microprocessor power supply voltage is too low or too high, the voltage monitoring circuit 4 will output a reset signal to reset the microprocessor or cut off the power supply of the microprocessor, thereby ensuring that the abnormal voltage will not affect the normal operation of the microprocessor. When there is no need to monitor the power supply of the microprocessor, the voltage monitoring circuit 4 can be omitted.

[0100] In an optional embodiment, the voltage monitoring circuit 4 further has a reset input terminal 42, and the reset input terminal 42 is connected to the delay signal output terminal 22a;

[0101] The voltage monitoring circuit 4 is configured as follows:

[0102] The hold signal and the reset signal are output through the reset signal output terminal 41 .

[0103] In this embodiment, the voltage monitoring circuit 4 is also connected to the microprocessor monitoring circuit. If the microprocessor fails to wake up, after the delay time interval set by the delay circuit 2b, the output of the delay circuit 2 will become a high level and input to the reset input terminal 42, so that the voltage monitoring circuit 4 outputs a reset signal to reset the microprocessor or power off and restart the microprocessor.

[0104] As a way to achieve this, Figure 5 As shown, the voltage monitoring circuit 4 includes:

[0105] The second power supply monitoring reset chip U4, the reset input pin of the second power supply monitoring reset chip U4 is configured as reset input 42, the reset pin Configured as a reset signal output terminal 41.

[0106] Figure 5 The microprocessor monitoring circuit shown is Figure 2 Compared with the above, the voltage monitoring circuit 4 is added, combined with Figure 1 The text content of the , its working principle is:

[0107] When the microprocessor is working normally, the delay circuit 2b outputs WAKEUP_TIMEOUT as a high level, and the input pin is cleared. In the invalid state, its output UVLO keeps high level, no reset signal is output, and the microprocessor works normally;

[0108] When the microprocessor is in sleep mode, the D-type flip-flop U1b outputs WAKEUP_TRIG_N as high level, the delay circuit 2b outputs WAKEUP_TIMEOUT as high level, and the microprocessor remains in sleep mode;

[0109] When the D flip-flop U1b inputs the wake-up signal WAKE, its inverted output terminal The output becomes a low level signal WAKEUP_TRIG_N which is opposite to the D terminal;

[0110] When the microprocessor fails to wake up, that is, D_CLEAR cannot be pulled low within the delay time interval, the first capacitor C1a continues to discharge through the resistor R1a until WAKEUP_TIMEOUT is lower than the clear input pin The reset threshold makes becomes a low level, thereby triggering the second power supply monitoring reset chip U4 to output UVLO as a low level to reset the microprocessor;

[0111] When the microprocessor is awakened within the delay time interval, the wake-up status signal D_CLEAR output by it is pulled low, the D flip-flop U1 is cleared, and the reverse output terminal The output WAKEUP_TRIG_N becomes high level, and the first capacitor C1a is quickly charged through the diode D1a. The voltage of the first capacitor C1a rises rapidly, that is, for the second power supply monitoring reset chip U4, the input pin is reset. It is always at a high level, the second power supply monitoring reset chip U4 does not output the reset signal UVLO, and the microprocessor keeps working normally.

[0112] In this embodiment, the second power monitoring reset chip U4 simultaneously monitors the power supply of the microprocessor and generates a reset signal when the microprocessor fails. As an option, the second power monitoring reset chip can be connected to the microprocessor power supply or coupled to the delay signal output end of the delay circuit, which is not limited here.

[0113] As an optional implementation, Figure 5 The second power supply monitoring reset chip shown can also be used in Figure 3 The microprocessor monitors the circuit shown to obtain Figure 6 The microprocessor monitoring circuit shown in FIG. Among them, the second power supply monitors the reset input pin of the reset chip U4a. Connect to the second inverting output terminal 1Y of the inverter U3a. Its working principle is referenced Figure 5 The contents shown will not be elaborated here.

[0114] By using the microprocessor monitoring circuit of each of the above embodiments, the microprocessor can be reset in time when the microprocessor fails to wake up, thereby ensuring the normal operation of the microprocessor and greatly improving the reliability of the system. In particular, even if it is used in a low-power scenario or a low-power electronic device, the microprocessor monitoring circuit provided in this embodiment can still provide a reset and maintain the low-power operation of the device, and the circuit structure is simple, low-cost, and high-reliability.

[0115] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A microprocessor monitoring circuit, characterized in that: include: D flip-flop and delay circuit; The D flip-flop has a first input terminal, a second input terminal and a trigger signal output terminal, the delay circuit has a trigger signal input terminal and a delay signal output terminal, the trigger signal output terminal is coupled to the trigger signal input terminal, the first input terminal is configured to be coupled to the microprocessor, the second input terminal is configured to receive a wake-up signal to the microprocessor, and the delay signal output terminal is configured to be coupled to a reset pin of the microprocessor; The D flip-flop is configured as: When the first input terminal receives the wake-up state signal output by the microprocessor, the first input terminal maintains the reset state and outputs the first potential signal through the trigger signal output terminal; When the first input terminal receives the wake-up waiting signal output by the microprocessor, the reset state is released, and when the second input terminal receives the wake-up signal, a second potential signal which is inverted with the first potential signal is output through the trigger signal output terminal; The delay circuit is configured as follows: When the trigger signal input terminal receives the first potential signal, a holding signal is output through the delay signal output terminal to control the microprocessor to maintain a current state; When the trigger signal input terminal receives the second potential signal, timing is performed, and after the timing time exceeds the delay time interval, a reset signal is output through the delay signal output terminal to reset or restart the microprocessor.

2. The microprocessor monitoring circuit according to claim 1, characterized in that: The trigger signal output terminal is a reverse output terminal; The delay circuit includes a resistor, a first capacitor and a diode, the resistor is connected in parallel with the diode, the positive electrode of the diode is configured as the trigger signal input terminal, the negative electrode of the diode is configured as the delay signal output terminal, and the first capacitor is coupled between the delay signal output terminal and the ground terminal.

3. The microprocessor monitoring circuit according to claim 1, characterized in that: The trigger signal output terminal is a same-direction output terminal; The delay circuit includes a first power supply monitoring reset chip and a second capacitor: The first power supply monitoring reset chip has a clear input pin, a capacitor pin and a reset pin, the clear input pin is configured as the trigger signal input terminal, the reset pin serves as the delay signal output terminal, and the second capacitor is coupled between the capacitor pin and the ground terminal.

4. The microprocessor monitoring circuit according to claim 2, characterized in that: The first capacitor is an adjustable capacitor.

5. The microprocessor monitoring circuit according to claim 1, characterized in that: The microprocessor monitoring circuit also includes: An inverter having a phase input terminal and a phase output terminal, wherein the phase input terminal is connected to the delay signal output terminal, and the phase output terminal is configured to be coupled to a reset pin of the microprocessor; The delay circuit is configured to couple the delay signal output terminal to a reset pin of the microprocessor through the inverter, so as to output the holding signal or the reset signal through the phase output terminal of the inverter.

6. The microprocessor monitoring circuit according to claim 1, characterized in that: The microprocessor monitoring circuit also includes: a voltage monitoring circuit having a voltage sensing pin and a reset signal output terminal; The voltage monitoring circuit is configured as: The power supply of the microprocessor is connected via the voltage sensing pin to sense the power supply voltage, and when the power supply voltage is abnormal, a reset signal or a power cut-off signal is output to the microprocessor via the reset signal output terminal.

7. The microprocessor monitoring circuit according to claim 6, characterized in that: The voltage monitoring circuit also has a reset input terminal, and the reset input terminal is connected to the delay signal output terminal; The voltage monitoring circuit is configured as: The hold signal and the reset signal are output through the reset signal output terminal.

8. The microprocessor monitoring circuit according to claim 7, characterized in that: The voltage monitoring circuit includes a second power supply monitoring reset chip, a reset input pin of the second power supply monitoring reset chip is configured as the delay signal input end, and the reset pin is configured as the reset signal output end.

9. The microprocessor monitoring circuit according to claim 1, characterized in that: The first input terminal is a clock signal pin, and the second input terminal is a reset pin.

10. An electronic device comprising a microprocessor and the microprocessor monitoring circuit according to any one of claims 1 to 9.

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