Clock distribution circuit, BBU device and network device
By designing a clock distribution circuit, using the RF front-end processing module, clock processing module and interface module, selecting appropriate timing signals for distribution, the problems of high timing cost and reduced synchronization accuracy of base station Beidou in the prior art are solved, and low-cost and high-precision timing support is achieved.
Patent Information
- Application Number
- CN202421470672.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-25
- Publication Date
- 2025-04-15
- Estimated Expiration
- 2034-06-25
AI Technical Summary
The existing technology is difficult to support Beidou timing at the base station at low cost while taking into account the timing accuracy. Especially in ultra-long-distance application scenarios, the synchronization error will increase step by step, resulting in a decrease in synchronization accuracy.
A clock distribution circuit is designed, including a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module and an interface module. The first timing signal is generated by the first clock processing module, the second clock processing module generates the second timing signal, and the clock distribution module selects a target timing signal, and finally sends it to the downstream network device through the interface module.
It realizes the low-cost support for Beidou timing on the base station while taking into account the timing accuracy, reducing the base station transformation cost and construction difficulty, and is suitable for ultra-long-distance application scenarios.
Smart Images
Figure CN222763890U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of wireless communications, and in particular to a clock distribution circuit, a BBU device and a network device. Background Art
[0002] At present, with the full completion of the Beidou-3 satellite system, the demand for communication base stations to support the Beidou system timing standard is becoming more and more urgent, and it is urgent to carry out construction and transformation of base stations that do not support Beidou timing. There are two main existing solutions: signal receiver transformation, that is, replacing the satellite signal receiver supporting the Global Positioning System (GPS) with a satellite signal receiver supporting Beidou to achieve the conversion between the two satellite systems, but there are problems of high cost and difficulty in construction and transformation. Alternatively, based on the 1588V2 timing transformation, the 1588V2 high-precision time synchronization server is used to obtain time and frequency from the satellite in the air, and then transmit it to each base station through the transmission bearer network, and provide time synchronization for the base station through the local mobile backhaul network, but the 1588V2 timing can only guarantee a good time synchronization accuracy within a limited distance. For ultra-long distance application scenarios, the synchronization error will increase step by step, resulting in a decrease in synchronization accuracy. Therefore, how to support the Beidou timing of base stations at a low cost while taking into account the timing accuracy has become a technical problem that needs to be solved urgently. Summary of the invention
[0003] In view of this, embodiments of the present invention are intended to provide a clock distribution circuit, a BBU device, and a network device.
[0004] The technical solution of the utility model embodiment is achieved as follows:
[0005] The present utility model embodiment provides a clock distribution circuit, the clock distribution circuit comprising: a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module, and an interface module; the input end of the radio frequency front-end processing module is connected to a satellite antenna, the output end of the radio frequency front-end processing module is connected to the input end of the first clock processing module, the output end of the first clock processing module and the output end of the second clock processing module are simultaneously connected to the input end of the clock distribution module; the output end of the clock distribution module is connected to the input end of the interface module;
[0006] in,
[0007] The radio frequency front-end processing module is used to obtain the radio frequency signal transmitted by the Beidou satellite through the satellite antenna;
[0008] The first clock processing module is used to determine first time information based on the radio frequency signal; and generate a first timing signal based on the first time information;
[0009] The second clock processing module is used to obtain second time information from a time server; based on the second time information, generate a second timing signal; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite, and is determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal;
[0010] The clock distribution module is used to select one of the first timing signal and the second timing signal as a target timing signal;
[0011] The interface module is used to output the target timing signal to multiple downstream network devices through multiple types of physical interfaces; the target timing signal is used for the network devices to perform time synchronization.
[0012] In addition, according to at least one embodiment of the present utility model, the clock distribution module includes a first switch;
[0013] Among them, the first switch is used to respond to a first instruction and output the first timing signal as the target timing signal to the output end of the clock distribution module; respond to a second instruction and output the second timing signal as the target timing signal to the output end of the clock distribution module; the second instruction is different from the first instruction.
[0014] In addition, according to at least one embodiment of the present utility model, the first switch is a multi-way selection switch.
[0015] In addition, according to at least one embodiment of the present utility model, the clock distribution circuit is arranged in a baseband processing unit (BBU, Building Base band Uuit) device; the clock distribution circuit further includes: a management module;
[0016] in,
[0017] The management module is used to obtain the first instruction from the main control board of the BBU device and send the first instruction to the clock distribution module in the clock distribution circuit; the first instruction is used to instruct to use the first timing signal as the target timing signal.
[0018] Furthermore, according to at least one embodiment of the present invention,
[0019] The management module is also used to obtain the second instruction from the main control board of the BBU device and send the second instruction to the clock distribution module in the clock distribution circuit; the second instruction is used to indicate that the second timing signal is used as the target timing signal.
[0020] In addition, according to at least one embodiment of the present utility model, the management module is further used to send the first data to the main control board;
[0021] in,
[0022] The first data includes at least one of the following:
[0023] Ephemeris information of the Beidou satellite;
[0024] Warning information;
[0025] Working status.
[0026] In addition, according to at least one embodiment of the present utility model, the management module is further used to enable the main control board to perform at least one of the following operations:
[0027] Configure the working mode;
[0028] Query working mode;
[0029] Version upgrade management.
[0030] In addition, according to at least one embodiment of the present utility model, the management module is further used to send second data to the network manager;
[0031] in,
[0032] The second data includes at least one of the following:
[0033] Clock source;
[0034] Warning information.
[0035] An embodiment of the utility model provides a BBU device, comprising any one of the clock distribution circuits described above.
[0036] An embodiment of the utility model provides a network device, including the BBU device described above.
[0037] The utility model embodiment provides a clock distribution circuit, BBU equipment and network equipment, the clock distribution circuit includes: a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module, and an interface module; the input end of the radio frequency front-end processing module is connected to the satellite antenna, the output end of the radio frequency front-end processing module is connected to the input end of the first clock processing module, the output end of the first clock processing module and the output end of the second clock processing module are simultaneously connected to the input end of the clock distribution module; the output end of the clock distribution module is connected to the input end of the interface module; wherein the radio frequency front-end processing module is used to obtain the radio frequency signal transmitted by the Beidou satellite through the satellite antenna; the first clock processing module is used to determine based on the radio frequency signal First time information; based on the first time information, generate a first timing signal; the second clock processing module is used to obtain second time information from a time server; based on the second time information, generate a second timing signal; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite and determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal; the clock distribution module is used to select one of the first timing signal and the second timing signal as a target timing signal; the interface module is used to output the target timing signal to multiple downstream network devices through multiple types of physical interfaces; the target timing signal is used for time synchronization of the network devices.
[0038] By adopting the technical solution provided by the embodiment of the utility model, a first timing signal is generated by a first clock processing module, a second timing signal is generated by a second clock processing module, and a clock distribution module selects one of the first timing signal and the second timing signal as a target timing signal, and finally sends it to multiple downstream network devices through an interface module, wherein the first timing signal and the second timing signal are both obtained based on the radio frequency signal transmitted by the Beidou satellite. In this way, low-cost support for Beidou timing can be achieved while taking into account the timing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 is a schematic diagram of a satellite signal receiver in the related art;
[0040] Figure 2 It is a schematic diagram of a framework for implementing time synchronization using a time server in the related art;
[0041] Figure 3 It is a schematic diagram of the composition structure of the clock distribution circuit of the embodiment of the utility model;
[0042] Figure 4This is a schematic diagram of the system architecture of the clock distribution circuit application of the utility model embodiment Figure 1 ;
[0043] Figure 5 The specific structure diagram of the clock distribution circuit of the utility model is shown in FIG. Figure 1 ;
[0044] Figure 6 The specific structure diagram of the clock distribution circuit of the utility model is shown in FIG. Figure 2 ;
[0045] Figure 7 This is a schematic diagram of the internal structure of the BBU device of the embodiment of the utility model;
[0046] Figure 8 This is a schematic diagram of the implementation process of the clock distribution board and the main control board exchanging first data in an embodiment of the utility model;
[0047] Fig. 9 It is a schematic diagram of the implementation process of the main control board managing the clock distribution board in the embodiment of the utility model;
[0048] Fig.10 This is a schematic diagram of the system architecture of the clock distribution circuit application of the utility model embodiment Figure 2 . DETAILED DESCRIPTION
[0049] Before introducing the technical solution of the embodiment of the utility model, the related technology is first introduced.
[0050] At present, satellite navigation positioning and timing systems are extremely important infrastructure for modernized countries. The precise timing provided by satellite navigation systems has extensive and important applications in a country's industry, defense, communications and other fields. The current satellite navigation systems mainly include the United States' Global Satellite Positioning System GPS, Russia's Global Satellite Navigation System GLONASS, Europe's Global Navigation Positioning System Galileo and China's Beidou Navigation Positioning System.
[0051] At present, the early 4G base stations deployed in China do not support Beidou and mainly use GPS for timing, accounting for about 75% of the total number of 4G base stations. With the full completion of the Beidou-3 satellite system, the demand for communication base stations to support Beidou system timing is becoming more and more urgent, and it is urgent to carry out construction and transformation of base stations that do not support Beidou.
[0052] There are two main existing solutions:
[0053] The first one is the transformation of satellite signal receiver
[0054] See also Figure 1 , Figure 1is a schematic diagram of a satellite signal receiver in the related art, such as Figure 1 As shown in the figure, the satellite signal receiver supporting GPS (GPS receiver) is replaced with the satellite signal receiver supporting Beidou (Beidou receiver) to realize the conversion between the two satellite systems. Beidou and GPS are two different satellite positioning systems, and their signal standards and technical specifications are completely incompatible, so the satellite signal receiver needs to be replaced.
[0055] The second method is based on 1588V2 timing modification
[0056] See also Figure 2 , Figure 2 It is a schematic diagram of a framework for implementing time synchronization using a time server in related technologies, such as Figure 2 As shown, a 1588v2 high-precision time server is used to obtain time and frequency from aerial satellites, and then transmit them to each communication base station through the transmission bearer network (aggregation network and access network), providing time synchronization for the communication base stations through the local mobile backhaul network.
[0057] However, the above solution has the following technical defects:
[0058] For satellite signal reception and transformation: Currently, the satellite signal receiver and the base station main control share the same board. The transformation requires replacing the base station's main control board. A large number of boards are required for all replacements, which has the problems of high cost and difficulty in construction and transformation. For the transformation based on 1588V2 timing: Since each transmission device will introduce errors when transmitting the 1588v2 synchronization signal, 1588V2 timing can only guarantee a good time synchronization accuracy within a limited distance. For ultra-long distance application scenarios, the synchronization error will increase step by step, resulting in a decrease in synchronization accuracy.
[0059] Therefore, how to support Beidou timing of base stations at low cost while taking into account the timing accuracy has become a technical problem that needs to be solved urgently.
[0060] Based on this, in an embodiment of the utility model, the clock distribution circuit includes: a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module, and an interface module; the input end of the radio frequency front-end processing module is connected to the satellite antenna, the output end of the radio frequency front-end processing module is connected to the input end of the first clock processing module, and the output end of the first clock processing module and the output end of the second clock processing module are simultaneously connected to the input end of the clock distribution module; the output end of the clock distribution module is connected to the input end of the interface module; wherein the radio frequency front-end processing module is used to obtain the radio frequency signal transmitted by the Beidou satellite through the satellite antenna; the first clock processing module is used to determine the first time information based on the radio frequency signal; based on Based on the first time information, a first timing signal is generated; the second clock processing module is used to obtain the second time information from the time server; based on the second time information, a second timing signal is generated; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite and determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal; the clock distribution module is used to select one of the first timing signal and the second timing signal as the target timing signal; the interface module is used to output the target timing signal to multiple downstream network devices through multiple types of physical interfaces; the target timing signal is used for the network devices to perform time synchronization.
[0061] See also Figure 3 , Figure 3 Schematic diagram of the clock distribution circuit of the present utility model. Figure 3 As shown, the clock distribution circuit includes: a radio frequency front-end processing module 31, a first clock processing module 32, a second clock processing module 33, a clock distribution module 34, and an interface module 35; the input end of the radio frequency front-end processing module 31 is connected to the satellite antenna, the output end of the radio frequency front-end processing module 31 is connected to the input end of the first clock processing module 32, the output end of the first clock processing module 32 and the output end of the second clock processing module 33 are simultaneously connected to the input end of the clock distribution module 34; the output end of the clock distribution module 34 is connected to the input end of the interface module 35;
[0062] in,
[0063] The RF front-end processing module 31 is used to obtain the RF signal transmitted by the Beidou satellite through the satellite antenna;
[0064] The first clock processing module 32 is used to determine first time information based on the radio frequency signal; and generate a first timing signal based on the first time information;
[0065] The second clock processing module 33 is used to obtain second time information from the time server; based on the second time information, generate a second timing signal; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite, and is determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal;
[0066] The clock distribution module 34 is used to select one of the first timing signal and the second timing signal as a target timing signal;
[0067] The interface module 35 is used to output the target timing signal to multiple downstream network devices through multiple types of physical interfaces; the target timing signal is used for the network devices to perform time synchronization.
[0068] As an example, the clock distribution circuit may be provided in a BBU device.
[0069] As an example, the RF front-end processing module 31 supports receiving RF signals in one of the following formats:
[0070] The radio frequency signal of the B1I frequency point transmitted by the Beidou satellite in the Beidou-2 satellite system;
[0071] A radio frequency signal at one of the B1I, B1C and B2a frequencies transmitted by a BeiDou satellite in the BeiDou-3 satellite system.
[0072] As an example, the first clock processing module 32 is specifically used to amplify, filter and frequency convert the radio frequency signal transmitted by the Beidou satellite output by the radio frequency front-end processing module 31, and perform analog-to-digital conversion (AD) demodulation on the processed signal to obtain the original navigation data; decode the original navigation data, and obtain accurate navigation information (including position, speed and time information) through a series of algorithms such as capture, tracking, positioning and solving, etc., and use the time information in the navigation information as the first time information, and give the first timing signal according to the first time information, that is, 1PPS+TOD signal, wherein 1PPS represents a second pulse signal, that is, one pulse is sent per second, and TOD represents the first time information, such as seconds in a week (indicating the number of seconds in a week), week number, second pulse state, clock source type and working state. Among them, the main parameters included in the original navigation data include Beidou satellite number, frequency, signal-to-noise ratio, altitude, azimuth and other information, and these parameters are decoded and solved to obtain accurate navigation information (position information and time information).
[0073] As an example, the second time information is acquired through an external high-precision time server, and the high-precision time server can send the second time information to the second clock processing module 33 in the clock distribution circuit through a transmission network.
[0074] Here, the input end of the second clock processing module 33 can be connected to an external high-precision time server.
[0075] Here, the second clock processing module 33 is specifically used for: generating a second timing signal, i.e., a 1588V2 synchronization protocol signal, based on the second time information by receiving the second time information input by an external high-precision time server, and outputting the 1588V2 synchronization protocol signal to the outside for the downstream network equipment to calculate the time deviation and adjust its own time, thereby realizing PTP high-precision timing; wherein, the external high-precision time server amplifies, filters and frequency-converts the radio frequency signal transmitted by the acquired Beidou satellite, and performs analog-to-digital conversion (AD) and demodulation on the processed signal to obtain the original navigation data; decoding the original navigation data, and obtaining accurate navigation information (including position, speed, time and other information) through a series of algorithm processing such as capture, tracking, positioning and solving, and the time information in the navigation information is used as the second time information.
[0076] In some embodiments, the clock distribution module 34 includes a first switch;
[0077] Among them, the first switch is used to respond to a first instruction and output the first timing signal as the target timing signal to the output end of the clock distribution module; respond to a second instruction and output the second timing signal as the target timing signal to the output end of the clock distribution module; the second instruction is different from the first instruction.
[0078] In some embodiments, the first switch is a multi-way selection switch.
[0079] As an example, the first switch may be a two-choice-one multi-way selection switch.
[0080] In some embodiments, the clock distribution circuit is arranged in a BBU device; the clock distribution circuit further comprises: a management module;
[0081] in,
[0082] The management module is used to obtain the first instruction from the main control board of the BBU device and send the first instruction to the clock distribution module 34 in the clock distribution circuit; the first instruction is used to instruct to use the first timing signal as the target timing signal.
[0083] In some embodiments, the management module is also used to obtain the second instruction from the main control board of the BBU device and send the second instruction to the clock distribution module 34 in the clock distribution circuit; the second instruction is used to indicate that the second timing signal is used as the target timing signal.
[0084] As an example, the main control board of the BBU device can select the target timing signal according to the requirements of the downstream network device.
[0085] For example, assuming that the downstream network device 1 requires the use of the first timing signal for time synchronization, the main control board of the BBU device can send the first instruction to the clock distribution module 34 in the clock distribution circuit. In this way, the clock distribution module 34 selects the first timing signal as the target timing signal and sends it to the corresponding downstream network device 1 through the interface module 35.
[0086] For another example, assuming that the downstream network device 2 requires the use of a second timing signal for time synchronization, the main control board of the BBU device can send the second instruction to the clock distribution module 34 in the clock distribution circuit. In this way, the clock distribution module 34 selects the second timing signal as the target timing signal and sends it to the corresponding downstream network device 2 through the interface module 35.
[0087] As an example, in actual application, the main control board of the BBU device may also preferentially select the first timing signal as the target timing signal.
[0088] As an example, in actual application, the main control board of the BBU device can select the target timing signal according to the working mode configured for the clock distribution circuit. For example, assuming that the working mode is configured as a single Beidou mode, the first timing signal is selected as the target timing signal. Assuming that the working mode is configured as a Beidou priority mode, the first timing signal is preferentially selected as the target timing signal. If the first timing signal does not meet the requirements such as accuracy, the second timing signal is selected as the target timing signal.
[0089] As an example, the interface module 35 supports the following types of physical interfaces:
[0090] Standard connector for communication networks (RJ45, Registered Jack45).
[0091] High Definition Multimedia Interface (HDMI).
[0092] Universal Serial Bus (USB).
[0093] Here, the interface module is specifically used to output the target timing signal according to the protocol requirements of different types of physical interfaces.
[0094] Here, RJ45, HDMI, USB and other interface types are supported, and different models of base station equipment from different manufacturers can be connected.
[0095] For example, the downstream network devices include network device 1, network device 2, and network device 3, wherein the interface type of network device 1 is RJ45, and the target timing signal is sent to network device 1 through the interface; the interface type of network device 2 is HDMI, and the target timing signal is sent to network device 2 through the interface; and the interface type of network device 3 is USB, and the target timing signal is sent to network device 3 through the interface.
[0096] Here, the downstream receiving base station supports the input of 1PPS+TOD signal or 1588V2 synchronization protocol signal to obtain synchronization timing information, so that the base station meets the air interface and frequency accuracy requirements.
[0097] In some embodiments, the management module is further used to send first data to the main control board;
[0098] in,
[0099] The first data includes at least one of the following:
[0100] Ephemeris information of the Beidou satellite;
[0101] Warning information;
[0102] Working status.
[0103] As an example, the ephemeris information of the Beidou satellite includes satellite number, satellite type, signal-to-noise ratio, etc.
[0104] As an example, the alarm information includes various alarm information such as interface abnormal state detection alarm, clock source loss alarm, antenna open circuit and short circuit alarm, etc.
[0105] As an example, the working status may refer to the timing mode in which the device is working, such as the first clock (1PPS+TOD signal) timing or the second clock (1588V2 synchronization protocol signal) timing; it may also include the satellite antenna status, output interface status, etc.
[0106] As an example, the management module may exchange data with the main control board through the backplane in the BBU device.
[0107] In some embodiments, the management module is further configured to enable the main control board to perform one of the following operations:
[0108] Configure the working mode;
[0109] Query working mode;
[0110] Version upgrade management.
[0111] As an example, the working mode configuration is supported, such as single Beidou mode and Beidou priority mode. In the single Beidou mode, the first timing signal is selected as the target timing signal, and in the Beidou priority mode, the first timing signal is preferentially selected as the target timing signal. If the first timing signal does not meet the requirements of accuracy, the second timing signal is selected as the target timing signal.
[0112] In some embodiments, the management module is further used to send second data to the network manager;
[0113] in,
[0114] The second data includes at least one of the following:
[0115] Clock source;
[0116] Warning information.
[0117] As an example, the clock source includes the Beidou timing clock (first timing signal) and the 1588 timing clock (second timing signal).
[0118] As an example, the alarm information includes various alarm information such as interface abnormal state detection alarm, clock source loss alarm, antenna open circuit and short circuit alarm, etc.
[0119] The embodiment of the utility model has the following advantages:
[0120] (1) A clock distribution circuit (also described as a synchronous timing device) is provided, wherein the clock distribution circuit includes: a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module, and an interface module.
[0121] Specifically, a first timing signal is generated by a first clock processing module, a second timing signal is generated by a second clock processing module, and a clock distribution module selects one of the first timing signal and the second timing signal as a target timing signal, and finally sends it to multiple downstream network devices through an interface module, wherein the first timing signal and the second timing signal are both obtained based on the radio frequency signal transmitted by the Beidou satellite. In this way, low-cost support for Beidou timing can be achieved while taking into account the timing accuracy.
[0122] (2) In the same computer room, only one clock distribution board needs to be inserted into one BBU. The clock distribution board is equipped with a clock distribution circuit to solve the problem of all BBUs in the computer room supporting Beidou timing, which greatly saves investment costs and transformation costs.
[0123] In other words, it can reduce the equipment installation requirements for base station rooms and solve the problem of multiple base stations in the same room not supporting Beidou.
[0124] (3) Supports multiple output interface types (RJ45, HDMI, USB), taking into account compatibility and flexible connection.
[0125] That is, it supports multiple physical output interfaces to solve the problem of inconsistent physical interfaces in different batches and different station types in the computer room.
[0126] See also Figure 4 , Figure 4 Schematic diagram of the system architecture of the clock distribution circuit application of the utility model embodiment. Figure 4 As shown, the system comprises:
[0127] BBU device 1, including a clock distribution circuit;
[0128] Multiple downstream network devices include BBU device 2, BBU device 3, and BBU device 4.
[0129] Here, in the embodiment of the utility model, a clock distribution circuit (which can also be described as a clock distribution device) having multiple output types and multiple output interfaces is added inside the existing BBU device 1.
[0130] Here, the clock distribution circuit is connected to an external satellite antenna, converts the satellite reception signal into a radio frequency signal (electrical signal), and demodulates and processes the radio frequency signal to obtain the corresponding navigation positioning information and timing information. Signal selection (1PPS+TOD, 1588V2) and availability judgment are performed according to the upper-level network (main control board) mode configuration requirements, and signal output is performed according to the interface type requirements (RJ45, HDMI, USB) of the downstream base station. It can connect to multiple base stations of different manufacturers and types. The clock synchronization benchmark of all downstream base stations is the clock distribution circuit. The air interface and frequency accuracy requirements of each base station can be guaranteed by calibrating the network.
[0131] See also Figure 5 , Figure 5 is a schematic diagram of the specific composition structure of the clock distribution circuit of the embodiment of the utility model. The clock distribution circuit can be set in a BBU device, such as Figure 5 As shown, the clock distribution circuit includes:
[0132] RF front-end processing module;
[0133] Beidou timing processing module;
[0134] 1588 timing processing module;
[0135] Synchronous clock distribution module;
[0136] Interface module;
[0137] in,
[0138] The RF front-end processing module is the RF front-end processing module 31, the Beidou timing processing module corresponds to the first clock processing module 32, the 1588 timing processing module corresponds to the second clock processing module 33, the synchronous clock distribution module corresponds to the clock distribution module 34, and the interface module is the interface module 35.
[0139] The RF front-end processing module is used to obtain the RF signal transmitted by the Beidou satellite through the satellite antenna.
[0140] Here, the following RF signals can be received:
[0141] The radio frequency signal of the B1I frequency point transmitted by the Beidou satellite in the Beidou-2 satellite system;
[0142] A radio frequency signal at one of the B1I, B1C and B2a frequencies transmitted by a BeiDou satellite in the BeiDou-3 satellite system.
[0143] The Beidou timing processing module is used to determine the first time information based on the radio frequency signal transmitted by the Beidou satellite; and generate a first timing signal based on the first time information.
[0144] Here, the Beidou clock processing module is specifically used to: amplify, filter and frequency convert the radio frequency signal transmitted by the Beidou satellite output by the radio frequency front-end processing module, and perform analog-to-digital conversion (AD) demodulation on the processed signal to obtain original navigation data; decode the original navigation data, and obtain accurate navigation information (including position, speed, time and other information) through a series of algorithm processing such as capture, tracking, positioning solution, etc., and use the time information in the navigation information as the first time information, and give the first timing signal according to the first time information, that is, 1PPS+TOD signal, wherein 1PPS represents a second pulse signal, that is, one pulse is sent per second, and TOD represents the first time information, such as seconds in the week (indicating the number of seconds in a week), week number, second pulse status, clock source type and working status, etc.
[0145] Table 1 is a schematic diagram of the original navigation data obtained by the Beidou clock processing module through the relevant processing of the radio frequency signal transmitted by the Beidou satellite. As shown in Table 1, the main parameters of the original navigation data include Beidou satellite number, frequency, signal-to-noise ratio, altitude, azimuth and other information. These parameters are decoded and solved to obtain accurate navigation information (position information and time information).
[0146] Table 1
[0147] Number 6 7 23 …… 51 Frequency point B1I B1I B1C …… B2a Signal-to-Noise Ratio (SNR) 35 37 44 …… 42 Height e1 e2 e3 …… e5 Azimuth a1 a2 a3 …… a5
[0148] The 1588 timing processing module is used to obtain second time information from a time server; based on the second time information, a second timing signal is generated; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite and is determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal.
[0149] Here, the second time information is obtained through an external high-precision time server, and the high-precision time server can send the second time information to the 1588 timing processing module in the clock distribution circuit through a transmission network.
[0150] Here, the input end of the 1588 timing processing module can be connected to an external high-precision time server.
[0151] Here, the 1588 clock processing module is specifically used to: generate a second timing signal, i.e., a 1588V2 synchronization protocol signal, based on the second time information received from an external high-precision time server, and output the 1588V2 synchronization protocol signal to the outside for downstream network devices to calculate the time deviation and adjust their own time, thereby realizing PTP high-precision timing; wherein, the external high-precision time server amplifies, filters, and frequency-converts the radio frequency signal transmitted by the acquired Beidou satellite, and performs analog-to-digital conversion (AD) and demodulation on the processed signal to obtain the original navigation data; the original navigation data is decoded, and after a series of algorithm processing such as capture, tracking, positioning and solution, accurate navigation information (including position, speed, time and other information) is obtained, and the time information in the navigation information is used as the second time information.
[0152] The synchronous clock distribution module is used to select one of the first timing signal and the second timing signal as a target timing signal.
[0153] Here, the synchronous clock distribution module is specifically used to: receive the first timing signal (1PPS+TOD signal) output by the Beidou timing processing module and the second timing signal (1588V2 synchronization protocol signal) output by the 1588V2 timing processing module as two parallel signals at the same time, and select one of the first timing signal and the second timing signal as the target timing signal, and synchronize them through the calibration algorithm so that the two signal transmissions are consistent and without deviation, ensuring the accuracy and stability of signal transmission. Among them, calibration is to ensure the accuracy and stability of the clock. For example, the base station can monitor the deviation and error of the clock in real time and feed it back to the system. When a problem occurs in one of the clocks, it can quickly switch to another backup clock to ensure the normal operation of the base station.
[0154] Here, the synchronous clock distribution module may include a first switch; wherein the first switch is used to respond to a first instruction and output the first timing signal as the target timing signal to the output end of the synchronous clock distribution module; and is also used to respond to a second instruction and output the second timing signal as the target timing signal to the output end of the synchronous clock distribution module.
[0155] Here, the first switch may specifically be a multi-way selection switch, such as a two-to-one multi-way selection switch.
[0156] Here, the following working modes can be realized:
[0157] In the first working mode, the first timing signal output by the Beidou timing processing module is used as the target timing signal.
[0158] In other words, it supports the "single Beidou" working mode, that is, only Beidou satellites are used for timing.
[0159] In the second working mode, the second timing signal output by the 1588 timing processing module is used as the target timing signal.
[0160] That is to say, it supports the "Beidou priority" working mode. When the Beidou satellite system is available, only the first timing signal (1PPS+TOD signal) obtained based on the radio frequency signal transmitted by the Beidou satellite is used for timing; when the Beidou satellite system does not meet the receiver's positioning solution requirements, the second timing signal (1588V2 synchronization protocol signal) obtained based on the second time information sent by an external high-precision time server is used for timing.
[0161] Here, the target timing signal output in the following formats is supported:
[0162] The first format, that is, the first timing signal (1PPS+TOD) output by the Beidou timing processing module is used as the output target timing signal.
[0163] Among them, 1PPS (1 Pulse Per Second) refers to a second pulse, which is used to send a reference clock, i.e., the first timing signal, between network devices such as base station devices, and uses the rising edge as the reference edge; TOD (Time of Day) is a clock counter based on the Universal Coordinated Time (UTC), which is used to indicate the current time. TOD can also be used to transmit time information, status information, etc. related to the satellite system.
[0164] The second format, that is, the second timing signal (1588V2 synchronization protocol signal) output by the 1588 timing processing module is used as the output target timing signal.
[0165] Among them, 1588V2 refers to the Precision Time Protocol (PTP) that meets the standard networked measurement and control system, and periodically corrects the clocks of all nodes in the network through a second timing signal to achieve time synchronization.
[0166] The interface module is used to output the target timing signal to multiple downstream network devices such as multiple base stations through multiple types of physical interfaces.
[0167] Here, the following types of physical interfaces are supported:
[0168] Standard connector for communication networks (RJ45, Registered Jack45).
[0169] High Definition Multimedia Interface (HDMI).
[0170] Universal Serial Bus (USB).
[0171] Here, the interface module is specifically used to output the target timing signal according to the protocol requirements of different types of physical interfaces.
[0172] Here, interface types such as RJ45 (indicated by BBU-typeA), HDMI (indicated by BBU-typeB), and USB (indicated by BBU-typeC) are supported, and different models of base station equipment from different manufacturers can be connected.
[0173] For example, the downstream network devices include network device 1, network device 2, and network device 3, wherein the interface type of network device 1 is RJ45, and the target timing signal is sent to network device 1 through the interface; the interface type of network device 2 is HDMI, and the target timing signal is sent to network device 2 through the interface; and the interface type of network device 3 is USB, and the target timing signal is sent to network device 3 through the interface.
[0174] Here, the downstream receiving base station supports the input of 1PPS+TOD signal or 1588V2 synchronization protocol signal to obtain synchronization timing information so that the base station meets the air interface and frequency accuracy requirements.
[0175] In this example, the following advantages are achieved:
[0176] (1)Support 1PPS+TOD synchronization signal output and 1588 synchronization signal output.
[0177] That is, Beidou timing can be performed for the BBU of this chassis and the BBUs of other chassis at the same time.
[0178] (2) The output interface has multiple types (RJ45, HDMI, USB), which can adapt to different types of downstream network devices from multiple manufacturers.
[0179] That is, it has multiple output interfaces, flexible 1-band multiple connections, and can simplify networking.
[0180] See also Figure 6 , Figure 6 is a schematic diagram of the specific composition structure of the clock distribution circuit of the embodiment of the utility model. The clock distribution circuit can be set in a BBU device, such as Figure 6 As shown, the clock distribution circuit includes:
[0181] RF front-end processing module;
[0182] Beidou timing processing module;
[0183] 1588 timing processing module;
[0184] Synchronous clock distribution module;
[0185] Interface module;
[0186] Management module;
[0187] in,
[0188] The RF front-end processing module is the RF front-end processing module 31, the Beidou timing processing module corresponds to the first clock processing module 32, the 1588 timing processing module corresponds to the second clock processing module 33, the synchronous clock distribution module corresponds to the clock distribution module 34, the interface module is the interface module 35, and the management module is the management module.
[0189] Here, the clock distribution circuit mainly includes: RF front-end processing module, Beidou timing processing module, 1588 timing processing module, synchronous clock distribution module, interface module, management module and other core modules, and may also include a power module.
[0190] It should be noted that the implementation functions of the RF front-end processing module, Beidou timing processing module, 1588 timing processing module, synchronous clock distribution module and interface module have been described above and will not be repeated here.
[0191] The management module is used to obtain the first instruction from the main control board of the BBU device and send the first instruction to the synchronous clock distribution module in the clock distribution circuit; the first instruction is used to instruct to use the first timing signal as the target timing signal.
[0192] Here, the management module is also used to obtain the second instruction from the main control board of the BBU device and send the second instruction to the synchronous clock distribution module in the clock distribution circuit; the second instruction is used to indicate that the second timing signal is used as the target timing signal.
[0193] As an example, the main control board of the BBU device can select the target timing signal according to the requirements of the downstream network device.
[0194] For example, assuming that the downstream network device 1 requires the use of the first timing signal for time synchronization, the main control board of the BBU device can send the first instruction to the synchronous clock distribution module in the clock distribution circuit. In this way, the synchronous clock distribution module selects the first timing signal as the target timing signal and sends it to the corresponding downstream network device 1 through the interface module.
[0195] For another example, assuming that the downstream network device 2 requires the use of a second timing signal for time synchronization, the main control board of the BBU device can send the second instruction to the synchronous clock distribution module in the clock distribution circuit. In this way, the synchronous clock distribution module selects the second timing signal as the target timing signal and sends it to the corresponding downstream network device 2 through the interface module.
[0196] As an example, in actual application, the main control board of the BBU device may also preferentially select the first timing signal as the target timing signal.
[0197] The management module is also used to control and manage the operation of the entire clock distribution board, including system monitoring, information configuration, query, fault diagnosis and alarm functions. It also has the ability to communicate with the main control board.
[0198] The power module is used to connect, change and adjust the input power voltage, convert it into the output voltage required by each module inside the board, supply power to each module, and ensure the normal operation of the equipment.
[0199] In actual application, when all or part of the BBU equipment in the machine room does not support Beidou timing, a clock distribution board is inserted into one of the BBU frames. The clock distribution board has a built-in RF front-end processing module (which can be understood as a satellite signal receiver), Beidou timing processing module, 1588 timing processing module, synchronous clock distribution module, and interface module, which are used to output the first timing signal (1PPS+TOD signal) or the second timing signal (1588V2 synchronization protocol signal). It can not only perform synchronous timing for the local frame, but also perform synchronous timing for other frames (downstream base stations) according to application requirements, solving the problem that all BBUs in a machine room do not support Beidou.
[0200] See also Figure 7 , Figure 7 Schematic diagram of the internal structure of the BBU device of the utility model embodiment. Figure 7 As shown, the BBU device includes:
[0201] Back panel;
[0202] A clock distribution board, connected to the backplane, and provided with a clock distribution circuit;
[0203] Main control board, connected to the backplane.
[0204] in,
[0205] The clock distribution board is used to send the first data collected by the management module in the clock distribution circuit to the main control board through the backplane.
[0206] Here, the clock distribution board is built into the BBU frame and does not require a separate power supply. It interacts with the main control board through the backplane.
[0207] The main control board is used to receive the first data sent by the management module in the clock distribution circuit through the backplane.
[0208] The first data includes at least one of the following:
[0209] Ephemeris information of the Beidou satellite;
[0210] Warning information;
[0211] Working status.
[0212] Here, the alarm information includes various alarm information such as interface abnormal state detection alarm, clock source loss alarm, antenna open circuit and short circuit alarm, etc.
[0213] Here, the working status may refer to the timing mode in which the working state is, such as the first clock (1PPS+TOD signal) timing or the second clock (1588V2 synchronization protocol signal) timing; it may also include the satellite antenna status, output interface status, etc.
[0214] Figure 8 Schematic diagram of the implementation process of the clock distribution board and the main control board exchanging the first data in the embodiment of the utility model, such as Figure 8 As shown, including:
[0215] Step 801: The clock distribution board sends the ephemeris information of the Beidou satellite to the main control board.
[0216] Here, the Beidou satellite ephemeris information reporting is supported, including satellite number, satellite type, signal-to-noise ratio, etc.
[0217] Here, the 1PPS status can also be reported.
[0218] Step 802: The clock distribution board sends an alarm message to the main control board.
[0219] Here, alarm information reporting is supported; the alarm information includes various alarm information such as interface abnormal state detection alarm, clock source loss alarm, antenna open circuit and short circuit alarm, etc.
[0220] Step 803: The clock distribution board sends the working status to the main control board.
[0221] Here, working status query is supported. The working status may refer to the timing mode in which the system is working, such as the first clock (1PPS+TOD signal) timing or the second clock (1588V2 synchronization protocol signal) timing; it may also include satellite antenna status, output interface status, etc.
[0222] Fig. 9 This is a schematic diagram of the implementation process of the main control board managing the clock distribution board in the embodiment of the utility model, such as Fig. 9 As shown, including:
[0223] Step 901: The main control board configures the working mode for the clock distribution board.
[0224] Here, working mode configuration is supported, such as single Beidou mode and Beidou priority mode;
[0225] Step 902: The main control board queries the clock distribution board for the working mode.
[0226] Here, working mode query is supported.
[0227] Step 903: The main control board performs version upgrade management on the clock distribution board.
[0228] Here, version upgrade management is supported. The software version of the system means that the software provides a mechanism for the new version to maintain compatibility with the old version, and the software has the ability to automatically check for updates; if there is a problem, it can be rolled back to the previous version.
[0229] Fig.10 Schematic diagram of the system architecture of the clock distribution circuit application of the utility model embodiment. Fig.10 As shown, the system includes:
[0230] network management;
[0231] The BBU equipment of manufacturer A has a built-in clock distribution board, which includes a clock distribution circuit;
[0232] BBU equipment from downstream manufacturers A and B.
[0233] in,
[0234] The network management is used to receive second data sent by the management module in the clock distribution circuit;
[0235] The BBU device of manufacturer A is used to send the second data to the network management through the management module in the clock distribution circuit.
[0236] in,
[0237] The second data includes at least one of the following:
[0238] Clock source;
[0239] Warning information.
[0240] Among them, the clock sources include Beidou timing clock and 1588 timing clock.
[0241] Here, the alarm information includes various alarm information such as interface abnormal state detection alarm, clock source loss alarm, antenna open circuit and short circuit alarm, etc.
[0242] Here, since the clock distribution board is built into the BBU chassis of manufacturer A and supports interoperability between manufacturers, the clock distribution board needs to be managed and configured to confirm the location, status and connection status of the clock distribution device in the network.
[0243] Based on the above requirements, it is considered to issue the working mode configuration information of the clock distribution circuit through the large network management, and integrate the management function corresponding to the clock distribution circuit (set on the BBU board of manufacturer A) into the network management of this manufacturer (manufacturer A). The network management of this manufacturer (manufacturer A) uniformly monitors all BBUs connected to the clock distribution circuit, monitors the alarms sent by all BBUs and reports them. When problems are found, such as unauthorized tampering, replay attacks, link unavailability, etc., the configuration of the BBU within the controllable range can be modified and maintained in time to ensure business continuity and enhance security protection.
Claims
1. A clock distribution circuit, characterized in that: The clock distribution circuit includes: a radio frequency front-end processing module, a first clock processing module, a second clock processing module, a clock distribution module, and an interface module; the input end of the radio frequency front-end processing module is connected to the satellite antenna, the output end of the radio frequency front-end processing module is connected to the input end of the first clock processing module, the output end of the first clock processing module and the output end of the second clock processing module are simultaneously connected to the input end of the clock distribution module; the output end of the clock distribution module is connected to the input end of the interface module; in, The radio frequency front-end processing module is used to obtain the radio frequency signal transmitted by the Beidou satellite through the satellite antenna; The first clock processing module is used to determine first time information based on the radio frequency signal; and generate a first timing signal based on the first time information; The second clock processing module is used to obtain second time information from a time server; based on the second time information, generate a second timing signal; the second time information is obtained by the time server from the radio frequency signal transmitted by the Beidou satellite, and is determined based on the radio frequency signal; the second time information is different from the first time information, and the second timing signal is different from the first timing signal; The clock distribution module is used to select one of the first timing signal and the second timing signal as a target timing signal; The interface module is used to output the target timing signal to multiple downstream network devices through multiple types of physical interfaces; the target timing signal is used for the network devices to perform time synchronization.
2. The clock distribution circuit according to claim 1, characterized in that: The clock distribution module includes a first switch; Among them, the first switch is used to respond to a first instruction and output the first timing signal as the target timing signal to the output end of the clock distribution module; respond to a second instruction and output the second timing signal as the target timing signal to the output end of the clock distribution module; the second instruction is different from the first instruction.
3. The clock distribution circuit according to claim 2, characterized in that: The first switch is a multi-way selection switch.
4. The clock distribution circuit according to claim 2, characterized in that: The clock distribution circuit is arranged in a baseband processing unit BBU device; The clock distribution circuit further includes: a management module; in, The management module is used to obtain the first instruction from the main control board of the BBU device and send the first instruction to the clock distribution module in the clock distribution circuit; the first instruction is used to instruct to use the first timing signal as the target timing signal.
5. The clock distribution circuit according to claim 4, characterized in that: The management module is also used to obtain the second instruction from the main control board of the BBU device and send the second instruction to the clock distribution module in the clock distribution circuit; the second instruction is used to indicate that the second timing signal is used as the target timing signal.
6. The clock distribution circuit according to claim 5, characterized in that: The management module is further used to send first data to the main control board; in, The first data includes at least one of the following: Ephemeris information of the Beidou satellite; Warning information; Working status.
7. The clock distribution circuit according to claim 5, characterized in that: The management module is further configured to enable the main control board to perform at least one of the following operations: Configure the working mode; Query working mode; Version upgrade management.
8. The clock distribution circuit according to claim 5, characterized in that: The management module is further used to send second data to the network manager; in, The second data includes at least one of the following: Clock source; Warning information.
9. A BBU device, characterized in that: The method comprises the clock distribution circuit as claimed in any one of claims 1 to 8.
10. A network device, characterized in that: Includes the BBU device as claimed in claim 9.