Heterojunction battery piece and photovoltaic module

Abstract

The embodiment of the utility model provides a heterojunction battery piece and a photovoltaic module. The heterojunction battery piece comprises a first quantum dot layer; the first quantum dot layer is arranged between the front anti-reflection layer and the front conductive layer; the front anti-reflection layer is an anti-reflection layer facing the sunshine side, and the front conductive layer is a conductive layer facing the sunshine side; and the front anti-reflection layer is positioned on the outer side of the front conductive layer in the heterojunction battery piece. According to the technical scheme, the spectral response range can be widened, the stability is enhanced, the photon reflection loss is reduced, and the photoelectric conversion efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a heterojunction cell and a photovoltaic module. Background Art

[0002] Among solar cells, silicon-based heterojunction cells (HJT) have the advantages of high conversion efficiency and good temperature characteristics, and have received increasing attention in the industry in recent years.

[0003] Existing heterojunction cells have a limited light absorption range and photon reflection, which makes it impossible to fully utilize the energy in the solar spectrum, resulting in some photons not being absorbed. They have poor stability and are easily affected by external environmental factors. The photoelectric conversion efficiency of the cells is low.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Utility Model Content

[0005] The embodiments of the present application provide a heterojunction cell and a photovoltaic module to solve or alleviate one or more of the technical problems mentioned above.

[0006] According to a first aspect of an embodiment of the present application, a heterojunction cell is provided, comprising:

[0007] The first quantum dot layer; the first quantum dot layer is arranged between the front anti-reflection layer and the front conductive layer; the front anti-reflection layer is the anti-reflection layer facing the sunlight side, and the front conductive layer is the conductive layer facing the sunlight side; the front anti-reflection layer is located on the sunlight side of the front conductive layer in the heterojunction cell.

[0008] Optionally, a side of the front conductive layer facing the front anti-reflection layer includes a first reserved area for printing a first main grid, and the first reserved area is reserved by configuring a mask plate matched with the first reserved area.

[0009] Optionally, the first quantum dot layer is spin-coated on an area outside the first reserved area on a side of the front conductive layer facing the front anti-reflection layer.

[0010] Optionally, the heterojunction cell further includes a first electrode, which is electrically connected to the first main grid and then passes through the front anti-reflection layer.

[0011] Optionally, the first quantum dot layer is made based on at least one or more materials of cadmium selenide, copper indium gallium sulfide, zinc selenide (and perovskite quantum dots).

[0012] Optionally, the thickness of the first quantum dot layer is 50-150 nm.

[0013] Optionally, it also includes a second quantum dot layer, which is arranged between the back anti-reflection layer and the back conductive layer; the back anti-reflection layer is the anti-reflection layer on the side facing away from the sunlight, and the back conductive layer is the conductive layer on the side facing away from the sunlight; the back anti-reflection layer is located on the side of the back conductive layer facing away from the sunlight in the heterojunction cell.

[0014] Optionally, a first functionalized film is formed on the side of the front conductive layer facing the front anti-reflection layer, so that the first quantum dot layer is attached to the side of the front conductive layer facing the front anti-reflection layer through the first functionalized film.

[0015] Optionally, the first functionalized film is formed by modifying the front conductive layer.

[0016] According to a second aspect of the embodiments of the present application, a photovoltaic module is provided, comprising: a plurality of cells, wherein the cells comprise the heterojunction cells as described above.

[0017] The above technical solution adopted in the embodiment of the present application may have the following advantages:

[0018] By introducing the first quantum dot layer, the spectral response range of the front side of the heterojunction cell can be broadened, thereby improving the photoelectric conversion efficiency of the heterojunction cell. In addition, quantum dots have excellent chemical stability and optical stability, which can protect the heterojunction cell from the influence and damage of the external environment, thereby improving the stability of the heterojunction cell and extending the life of the heterojunction cell. In addition, by arranging the first quantum dot layer between the front anti-reflection layer and the front conductive layer, the influence of the first quantum dot layer on the carrier transmission can be avoided, thereby improving the photoelectric conversion efficiency of the heterojunction cell. At the same time, quantum dots have good anti-reflection properties. After being superimposed with the front anti-reflection layer, they can effectively reduce the reflection loss of photons on the surface of the heterojunction cell, which is conducive to improving the utilization rate of light, thereby improving the photoelectric conversion efficiency of the heterojunction cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0020] Figure 1 It is a schematic diagram of the structure of the heterojunction battery cell provided in the embodiment of the present application. DETAILED DESCRIPTION

[0021] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0022] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0023] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0024] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0025] It should be noted that the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0026] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings.

[0027] The present application embodiment provides a heterojunction cell. Figure 1 As shown, the heterojunction cell comprises: a first quantum dot layer 51 , a front anti-reflection layer 61 and a front conductive layer 41 .

[0028] Quantum dots are a type of low-dimensional semiconductor nanostructure, also known as semiconductor nanocrystals. They are generally spherical or quasi-spherical, with diameters between 2 and 20 nanometers (10 to 50 atoms). Quantum dots are semiconductor nanostructures that bind conduction band electrons, valence band holes, and excitons (electron-hole pairs) in three spatial dimensions. Due to their superior optical properties, quantum dots have many potential applications in solar energy conversion, luminescence and display devices, photoelectric detection, catalysis, molecular and cell labeling, and ultrasensitive detection.

[0029] In the embodiment of the present application, a first quantum dot layer 51 is added to the original heterojunction cell, and the first quantum dot layer 51 is disposed between the front anti-reflection layer 61 and the front conductive layer 41 .

[0030] The first quantum dot layer 51 is a stacked layer formed by laying out quantum dot materials, and is stacked between the front anti-reflection layer 61 and the front conductive layer 41 .

[0031] The front anti-reflection layer 61 is an anti-reflection layer facing the sunlight side. The anti-reflection layer is made of a material with anti-reflection properties. The setting of the anti-reflection layer can reduce the reflection of photons, thereby reducing the loss of photons and improving the light absorption performance.

[0032] The front conductive layer 41 is a conductive layer facing the sunlight side; the conductive layer is used to conduct carriers to the main grid on one side of the conductive layer, and the electrode transmits current by being electrically connected to the main grid. The conductive layer is paved with transparent conductive oxide materials, and the transparent conductive oxides include indium tin oxide (ITO) and zinc oxide (ZnO).

[0033] The above-mentioned laying can be a layer laid by spin coating, vacuum evaporation, magnetron sputtering, atomic layer deposition and other methods.

[0034] like Figure 1 As shown, the front anti-reflection layer 61 is located on the side of the front conductive layer 41 facing the sunlight in the heterojunction cell. The first quantum dot layer 51 is disposed between the front anti-reflection layer 61 and the front conductive layer 41. Light irradiates the front anti-reflection layer 61, passes through the front anti-reflection layer 61 and the first quantum dot layer 51 to the front conductive layer 41, and the electrons in the first quantum dot layer 51 and the front conductive layer 41 are excited by photons and transition to the conduction band to form electron-hole pairs.

[0035] Light passes through the front anti-reflection layer 61 and the first quantum dot layer 51 to the front conductive layer 41. The front anti-reflection layer 61 can reduce the reflection of light and improve the absorption of photons. The first quantum dot layer 51 also has good anti-reflection properties, which can further reduce the reflection loss of photons, improve the utilization rate of light, and enhance the photoelectric conversion efficiency.

[0036] Due to the small size of the quantum dots in the first quantum dot layer 51 , electrons do not need to move as they would on larger particles, resulting in faster carrier transmission.

[0037] Based on the small size of the quantum dots in the first quantum dot layer 51, the first quantum dot layer 51 arranged close to the front anti-reflection layer 61 can achieve spectral absorption of a wider band, which allows the heterojunction battery to cover a wider spectral range, including visible light, near-infrared light, etc., thereby improving the performance of the battery under different lighting conditions.

[0038] Quantum dots also have excellent chemical stability and optical stability, which can protect the surface of the conductive layer from being affected and damaged by the external environment and extend the service life and stability of heterojunction batteries.

[0039] In the embodiment of the present application, the first quantum dot layer 51 is arranged between the front anti-reflection layer 61 and the front conductive layer 41, so that the original basic structure of the heterojunction battery does not need to be changed too much, and has good carrier transport characteristics, while being able to broaden the response range of the battery spectrum.

[0040] In the embodiment of the present application, since the quantum dot material has an anti-reflection effect, the light utilization efficiency can be further improved, thereby improving the battery conversion efficiency.

[0041] In this technical field, there are also explorations of applying quantum dots to heterojunction batteries based on other considerations. For example, quantum dots are doped with silicon nitride and then directly deposited on a textured silicon substrate. However, such improvements do not significantly change the carrier transport of the battery structure, and the photoelectric conversion efficiency is not much different from that of the original heterojunction battery.

[0042] In the embodiment of the present application, by setting the first quantum dot layer 51 between the front anti-reflection layer 61 and the front conductive layer 41, the quantum dots in the first quantum dot layer 51 can act on both light and electrons, so that such a heterojunction battery can have a higher carrier transmission speed, a wider spectral response range, less photon reflection loss, and a higher photoelectric conversion efficiency compared to the original heterojunction battery.

[0043] In one example, the first quantum dot layer 51 can be made by spin coating, vacuum evaporation, magnetron sputtering, atomic layer deposition, etc. Preferably, the first quantum dot layer 51 can be made by spin coating.

[0044] In one embodiment, a side of the front conductive layer 41 facing the front anti-reflection layer 61 includes a first reserved area for printing a first main grid, and the first reserved area is reserved by configuring a mask plate adapted to the first reserved area.

[0045] In the process of preparing the heterojunction battery, it is necessary to print the first main grid on the front conductive layer 41 to collect the charges generated by the photoelectric conversion and output the current.

[0046] In the embodiment of the present application, since the first quantum dot layer 51 and the front anti-reflection layer 61 need to be coated on the side of the front conductive layer 41 facing the sunlight, a first reserved area for printing the first main grid can be reserved on the side of the front conductive layer 41 facing the sunlight, so that the silver paste of the first main grid can be printed in the first reserved area, and then the first quantum dot layer 51 and the front anti-reflection layer 61 are coated in the area outside the first reserved area. The specific preparation of the first main grid may include the following steps:

[0047] In a specific implementation, a mask plate adapted to the first reserved area can be customized and covered on the first reserved area of ​​the front conductive layer 41; then, a first quantum dot layer 51 and a front anti-reflection layer 61 are sequentially prepared on the area outside the first reserved area of ​​the front conductive layer 41; then, the mask plate is removed to expose the covered first reserved area; finally, silver paste is filled on the first reserved area to print the first main grid.

[0048] In the embodiment of the present application, by retaining the first reserved area on the side of the front conductive layer 41 facing the sunlight, it is convenient to prepare the first main grid and the first quantum dot layer 51 on the side of the front conductive layer 41 facing the sunlight when preparing the heterojunction battery.

[0049] In one embodiment, the first quantum dot layer 51 is spin-coated on a region outside the first reserved region on a side of the front conductive layer 41 facing the front anti-reflection layer 61 .

[0050] In an embodiment of the present application, the first quantum dot layer 51 is spin-coated on an area outside the first reserved area, so that after the first quantum dot layer 51 is spin-coated, the first main grid can be conveniently printed on the side of the front conductive layer 41 facing the front anti-reflection layer 61, thereby collecting the electrons of the front conductive layer 41 to the electrode through the first main grid.

[0051] In the embodiment of the present application, the step of coating the first quantum dot layer 51 on the side of the front conductive layer 41 facing the sunlight may include the following:

[0052] Step 1: Disperse the quantum dot material in a suitable solvent, which may be toluene, dimethylformamide (DMF), etc. The concentration of the solvent may be 0.1-1 M / L.

[0053] Step 2: Pre-spin coating at 700 rpm for 9 s;

[0054] Step 3: Spin coating at 3000 rpm for 20 s;

[0055] Step 4: Place the spin-coated battery substrate under a nitrogen flow for drying to remove the solvent and solidify the quantum dot coating;

[0056] Step 5: In a nitrogen atmosphere, the battery substrate is annealed at a temperature of 200° C. to solidify and form a first quantum dot layer 51 .

[0057] In one implementation, the heterojunction cell may further include: a first electrode 71 , which is electrically connected to the first main grid and then passes through the front anti-reflection layer 61 .

[0058] In the embodiment of the present application, the first electrode 71 is electrically connected to the first main grid and thus electrically connected to the front conductive layer 41 to collect carriers conducted from the front conductive layer 41. The first electrode 71 can be a metal electrode, such as metallic silver. The first electrode 71 can be made by screen printing or laser transfer.

[0059] In the embodiment of the present application, after the first electrode 71 passes through the front anti-reflection layer 61 , it is electrically connected to the external circuit to form a complete circuit loop, thereby generating a photocurrent.

[0060] In one embodiment, the first quantum dot layer 51 is made based on at least one or more materials of cadmium selenide (CdSe), copper indium gallium sulfide (CIGS), zinc selenide (ZnSe), and perovskite quantum dots.

[0061] In the embodiment of the present application, a combination of one or more of the above materials can be dispersed in a suitable solvent, such as toluene, dimethylformamide (DMF), etc., and the first quantum dot layer 51 can be deposited by spin coating. Preferably, a cadmium selenide quantum dot material with a small band gap can be used. The material can absorb photons in the range of ultraviolet light to visible light, has good transparency, and can improve the photon absorption rate of the heterojunction cell. In one embodiment, the thickness of the first quantum dot layer 51 is 50-150nm.

[0062] In the embodiment of the present application, a film layer is added on the basis of a traditional heterojunction cell, which will have a certain impact on the light transmittance of the heterojunction cell. By setting the thickness of the first quantum dot to 50-150nm, it is possible to ensure that the spectral response range of the heterojunction cell is broadened while reducing the impact of an overly thick film layer on the light transmittance of the heterojunction cell. Preferably, the thickness of the first quantum dot layer 51 can be: 50, 51, 52, 53, 54, ..., 99, 100, 101, 102, 103, ..., 146, 147, 148, 149, 150nm and other endpoint values.

[0063] In one embodiment, the heterojunction cell may further include: a second quantum dot layer, a back anti-reflection layer 62 and a back conductive layer 42 .

[0064] The second quantum dot layer is arranged between the back anti-reflection layer 62 and the back conductive layer 42; the back anti-reflection layer 62 is the anti-reflection layer on the side facing away from the sunlight, and the back conductive layer 42 is the conductive layer on the side facing away from the sunlight; the back anti-reflection layer 62 is located on the outside of the back conductive layer 42 in the heterojunction cell.

[0065] In the embodiment of the present application, there is also a certain amount of light absorption on the side of the heterojunction cell that is away from the sunlight. Through the second quantum dot layer and the back anti-reflection layer 62, and setting the second quantum dot layer between the back anti-reflection layer 62 and the back conductive layer 42, the spectral response range of the heterojunction cell can be further broadened, the stability of the heterojunction cell can be further increased, and the loss caused by light reflection can be further reduced together with the back anti-reflection layer 62, and the influence of the second quantum dot layer on carrier transmission can be avoided, thereby improving the photoelectric conversion efficiency of the heterojunction cell.

[0066] In an optional embodiment, the side of the back conductive layer 42 facing the back anti-reflection layer 62 includes a second reserved area for printing the second main grid, and the second reserved area is reserved by configuring a mask plate adapted to the second reserved area.

[0067] In the embodiment of the present application, since it is necessary to coat the second quantum dot layer and the back anti-reflection layer 62 on the side of the back conductive layer 42 facing away from the sunlight, a second reserved area can be first set on the side of the back conductive layer 42 facing away from the sunlight to facilitate printing the silver paste of the second main grid in the second reserved area, and then coating the second quantum dot layer in the area outside the second reserved area.

[0068] In the embodiment of the present application, by setting the second reserved area, it is convenient to prepare the second main grid and the second quantum dot layer on the side of the back conductive layer 42 facing away from the sunlight when preparing the heterojunction battery.

[0069] In an alternative embodiment, the second quantum dot layer is spin-coated on a region outside the second reserved region on a side of the back conductive layer 42 facing the back anti-reflection layer 62 .

[0070] In the embodiment of the present application, the second quantum dot layer is spin-coated on the area outside the second reserved area, which can effectively prevent the second quantum electric layer from contacting the second main gate, thereby avoiding affecting the electrical connection between the second electrode 72 and the second main gate in subsequent processes.

[0071] In the embodiment of the present application, the second quantum dot layer can be prepared by a method similar to that of the first quantum dot layer 51 .

[0072] In an optional embodiment, the heterojunction cell may further include: a second electrode 72 , which is electrically connected to the second main grid and then passes through the back anti-reflection layer 62 .

[0073] In the embodiment of the present application, the second electrode 72 is similar to the first electrode 71 and can be a metal electrode, such as metal silver. The second electrode 72 can be made by screen printing or laser transfer. The second electrode 72 is electrically connected to the second main grid and thus electrically connected to the back conductive layer 42 to collect carriers conducted by the back conductive layer 42.

[0074] In an optional embodiment, the thickness of the second quantum dot layer is 50-150 nm.

[0075] In one embodiment, a first functionalized film is formed on the side of the front conductive layer 41 facing the front anti-reflection layer 61 so that the first quantum dot layer 51 is attached to the side of the front conductive layer 41 facing the front anti-reflection layer 61 through the first functionalized film.

[0076] Considering that the first quantum dot layer 51 is deposited on the front conductive layer 41, poor adhesion or defects at the interface may occur due to the interface matching problem between the first quantum dot layer 51 and the front conductive layer 41. In the embodiment of the present application, by forming a first functionalized conductive layer on the front conductive layer 41 to adjust the wettability and adhesion of the surface of the front conductive layer 41, the adhesion of the front conductive layer 41 can be improved and the interface defects between the front conductive layer 41 and the first quantum dot layer 51 can be reduced.

[0077] In one embodiment, the first functionalized film is formed by modifying the front conductive layer 41 .

[0078] In the embodiment of the present application, the first functionalized conductive layer can be prepared by the following steps:

[0079] ① Dissolve an appropriate amount of sodium dodecyl sulfate (SDS) powder in water to form an SDS solution with a concentration of 0.1 to 10 mg / mL;

[0080] ② Under room temperature, immerse the battery substrate with the front conductive layer 41 deposited thereon in an SDS solution for 5-30 minutes;

[0081] ③ Take out the battery substrate after immersion, rinse it with anhydrous ethanol, and then rinse it thoroughly with 60-80℃ ultrapure water to completely remove the SDS on the surface;

[0082] ④ Use nitrogen to blow dry the battery substrate.

[0083] The above steps are all carried out in a clean room.

[0084] In an optional embodiment, a second functionalized film is formed on the side of the back conductive layer 42 facing the back anti-reflection layer 62, so that the second quantum dot layer is attached to the side of the back conductive layer 42 facing the back anti-reflection layer 62 through the second functionalized film. The second functionalized film can improve the adhesion of the back conductive layer 42 and reduce the interface defects between the back conductive layer 42 and the second quantum dot layer.

[0085] In an optional embodiment, the heterojunction cell may further include: a silicon substrate 1, a front intrinsic amorphous silicon layer 21, and a back intrinsic amorphous silicon layer 22. The front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 are respectively stacked on the front and back of the silicon substrate 1. Exemplarily, the silicon substrate 1 may be an N-type single crystal silicon substrate; the front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 may be intrinsic amorphous silicon layers made of the same material, and in some other examples, the intrinsic amorphous silicon layer may also be a microcrystalline silicon layer.

[0086] In one example, both the front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 may be undoped intrinsic amorphous silicon layers.

[0087] As an example, an N-type monocrystalline silicon substrate can be cleaned and textured. The surface morphology of the n-type monocrystalline silicon wafer after textured is a rounded pyramid, the base size of which can be 1-2um and the height can be 1-1.5um. The n-type silicon wafer after textured can reduce light reflection, thereby facilitating the improvement of light utilization.

[0088] The front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 can be deposited by using plasma assisted chemical vapor deposition (PECVD) technology to deposit monosilane (SiH 4 For example, SiH2O2 is introduced into the reaction chamber. 4 and hydrogen (H) which can adjust the quality of the intrinsic amorphous silicon layer 2), the gas flow rates are 500-2000sccm and 0-2000sccm respectively, and under the action of the reaction chamber, it is deposited on the front and back sides of the N-type single crystal silicon substrate at a temperature of 150-200°C to form a front intrinsic amorphous silicon layer 21 and a back intrinsic amorphous silicon layer 22. During the deposition process, the reaction pressure of the reaction chamber is 1-4mTor and the power is 100-1000W.

[0089] The front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 are respectively arranged on the front and back of the N-type single crystal silicon substrate. In the embodiment of the present application, the lattice structure of the intrinsic amorphous silicon layer has a high disorder. Therefore, the defect density of the intrinsic amorphous silicon layer is lower than that of a substrate made of crystalline silicon. Preparing the front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 on the front and back of the N-type crystalline silicon substrate can effectively passivate the interface defects of the N-type crystalline silicon substrate and reduce the recombination of carriers.

[0090] In an optional embodiment, the heterojunction cell may further include: a front doped amorphous silicon layer 31 and a back doped amorphous silicon layer 32. The doping types of the front doped amorphous silicon layer 31 and the back doped amorphous silicon layer 32 are opposite, for example, the doping type of the front doped amorphous silicon layer 31 is N-type, and the doping type of the back doped amorphous silicon layer 32 is P-type.

[0091] The front doped amorphous silicon layer 31 and the back doped amorphous silicon layer 32 can be deposited by PECVD technology. 4 For example, SiH2O2 is introduced into the reaction chamber. 4 and hydrogen (H) which can adjust the quality of the doped amorphous silicon layer 2 ) and doping gas, the gas flow rates are 500-2000sccm, 0-2000sccm and 0.1-50sccm respectively, and under the action of the reaction chamber, they are deposited on the front intrinsic amorphous silicon layer 21 and the back intrinsic amorphous silicon layer 22 at a temperature of 150-200°C to form the front doped amorphous silicon layer 31 and the back doped amorphous silicon layer 32. During the deposition process, the reaction pressure of the reaction chamber is 1-4mTor and the power is 100-1000W. When the N-type doped amorphous silicon layer is to be prepared, the doping gas is phosphine (PH 3 ); when a P-type doped amorphous silicon layer is to be prepared, the doping gas is diborane (B 2 H 3 ).

[0092] The front doped amorphous silicon layer 31 is disposed on the outer side of the front intrinsic amorphous silicon layer 21. The outer side of the front intrinsic amorphous silicon layer 21 is the side facing the sunlight.

[0093] The back doped amorphous silicon layer 32 is disposed on the outer side of the back intrinsic amorphous silicon layer 22. The outer side of the back intrinsic amorphous silicon layer 22 is the side facing away from the sunlight.

[0094] In the embodiment of the present application, the front-doped amorphous silicon layer 31 and the back-doped amorphous silicon layer 32 of opposite doping types jointly form the PN junction of the battery. When sunlight irradiates the heterojunction battery cell, the battery cell will separate the photons absorbed from the sunlight into electrons and holes. The electrons will move to the N-type region under the action of the electric field in the PN junction, and the holes will move to the P-type region under the action of the electric field in the PN junction, thereby realizing the separation and concentration of photogenerated charges (electrons and holes).

[0095] The following provides a comparison of performance parameters between various optional heterojunction cells according to the embodiments of the present application and conventional heterojunction cells, see Table 1.

[0096] Among them, the cell of Experimental Example 1 is a heterojunction cell with only a first quantum dot layer 51 added between the front anti-reflection layer 61 and the front conductive layer 41, and the material of the first quantum dot layer 51 is cadmium selenide quantum dots; the cell of Experimental Example 2 is a heterojunction cell with only a first quantum dot layer 51 added between the front anti-reflection layer 61 and the front conductive layer 41, and the material of the first quantum dot layer 51 is zinc selenide quantum dots; the cell of Experimental Example 3 is a heterojunction cell with a first quantum dot layer 51 added between the front anti-reflection layer 61 and the front conductive layer 41, and a second quantum dot layer added between the back anti-reflection layer 62 and the back conductive layer 42; the cell of Comparative Example 1 is a heterojunction cell without a quantum dot layer. Test data is shown in Table 1: The horizontal table header is the performance parameters selected for the experimental examples of this application, which are: the ratio of photoelectric conversion efficiency to the benchmark photoelectric conversion efficiency, the ratio of short-circuit current to the benchmark short-circuit current, the ratio of open-circuit voltage to the benchmark open-circuit voltage, and the ratio of fill factor to fill factor.

[0097]

[0098] Table 1

[0099] In Table 1, the photoelectric conversion efficiency (Eff b ), short circuit current (Isc b ), open circuit voltage (Voc b ), fill factor (FF b ) is the reference value (100%).

[0100] It can be seen from Table 1 that the ratios of the photoelectric conversion efficiency (Eff), short-circuit current (Isc), open-circuit voltage (Voc), and fill factor (FF) of the heterojunction cells of Experimental Examples 1, 2, and 3 of the present application to the reference values ​​are all greater than 100%, that is, the photoelectric conversion efficiency, short-circuit current, open-circuit voltage, and fill factor of Experimental Examples 1, 2, and 3 of the present application are higher than those of Comparative Example 1 without a quantum dot layer, and the battery performance is better. The data in Table 1 show that the technical solution of the embodiment of the present application can broaden the spectral response range, enhance stability, reduce photon reflection loss, and improve photoelectric conversion efficiency.

[0101] An embodiment of the present application further provides a photovoltaic module, including a plurality of cells, wherein the cells include heterojunction cells as described above, and adjacent cells can be connected together by series welding.

[0102] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0103] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when a specific feature, structure or characteristic is described in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0104] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0105] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A heterojunction cell, characterized in that: include: A first quantum dot layer; the first quantum dot layer is arranged between the front anti-reflection layer and the front conductive layer; the front anti-reflection layer is an anti-reflection layer facing the sunlight side, and the front conductive layer is a conductive layer facing the sunlight side; the front anti-reflection layer is located on the sunlight side of the front conductive layer in the heterojunction cell.

2. The heterojunction cell according to claim 1, characterized in that: The side of the front conductive layer facing the front anti-reflection layer includes a first reserved area for printing a first main grid, and the first reserved area is reserved by configuring a mask plate adapted to the first reserved area.

3. The heterojunction cell according to claim 2, characterized in that: The first quantum dot layer is spin-coated on an area outside the first reserved area on a side of the front conductive layer facing the front anti-reflection layer.

4. The heterojunction cell according to claim 2 or 3, characterized in that: It also includes a first electrode, which is electrically connected to the first main grid and passes through the front anti-reflection layer.

5. The heterojunction cell according to claim 1, characterized in that: The first quantum dot layer is made based on at least one or more materials of cadmium selenide, copper indium gallium sulfide, zinc selenide and perovskite quantum dots.

6. The heterojunction cell according to claim 1, characterized in that: The thickness of the first quantum dot layer is 50-150 nm.

7. The heterojunction cell according to claim 1, characterized in that: It also includes a second quantum dot layer, which is arranged between the back anti-reflection layer and the back conductive layer; the back anti-reflection layer is the anti-reflection layer on the side facing away from the sunlight, and the back conductive layer is the conductive layer on the side facing away from the sunlight; the back anti-reflection layer is located on the side of the back conductive layer facing away from the sunlight in the heterojunction cell.

8. The heterojunction cell according to any one of claims 1 to 3, characterized in that: A first functionalized film is formed on a side of the front conductive layer facing the front anti-reflection layer, so that the first quantum dot layer is attached to the side of the front conductive layer facing the front anti-reflection layer through the first functionalized film.

9. The heterojunction cell according to claim 8, characterized in that: The first functionalized film is formed by modifying the front conductive layer.

10. A photovoltaic module, characterized in that: include: A plurality of battery cells, wherein the battery cells are heterojunction battery cells according to any one of claims 1 to 9.

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