Handwriting board erasing circuit and chip

Abstract

The utility model provides a handwriting board erasing circuit and a chip, and belongs to the technical field of electronic circuits, and the handwriting board erasing circuit comprises a trigger circuit, a clock generator, a frequency dividing circuit, an erasing control circuit and a booster circuit. Wherein the trigger circuit generates an erase enable signal, the clock generator outputs a clock signal in response to the erase enable signal, the frequency dividing circuit outputs an erase drive signal with a preset duty ratio, and the erase control circuit outputs an erase control signal in response to the erase drive signal. The boost circuit generates a boost signal based on the erasing control signal and the output voltage of the voltage source, and outputs the boost signal to the first electrode of the handwriting board diaphragm so as to erase the handwriting board. Thus, the amplitude of the boosting signal is controlled through the erasing driving signal with the preset duty ratio, the effect of effectively erasing the content on the handwriting board diaphragm through the voltage source with the low amplitude is achieved, and then the handwriting board erasing function in the scene that the voltage source supplies power to the low-voltage power source is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a handwriting board erasing circuit and chip. Background Art

[0002] An LCD tablet is a device that can be reused and erased multiple times. It displays and erases images by changing the arrangement of liquid crystal molecules. Specifically, when a user writes on the LCD screen, the LCD screen will adjust the arrangement of the internal liquid crystal molecules based on the user's writing electrical signal, thereby changing the light transmittance and displaying the user's writing. When the content on the LCD tablet needs to be erased, a high-voltage pulse needs to be applied between the two poles of the LCD liquid crystal membrane to reset the arrangement of the membrane's liquid crystal molecules.

[0003] However, LCD tablets usually use low-voltage power supplies such as button batteries to provide voltage. The output voltage of button batteries is generally around 3V, which is much lower than the voltage required to erase the content of the LCD tablet. How to achieve the erasing function of the LCD tablet based on the lower voltage output by the button battery is a problem that needs to be solved urgently. Utility Model Content

[0004] In view of the deficiencies in the prior art, the present application provides a handwriting board erasing circuit and chip.

[0005] In a first aspect, the present application provides a handwriting board erasing circuit, comprising:

[0006] A trigger circuit receives an erase instruction and generates an erase enable signal based on the erase instruction;

[0007] A clock generator connected to the trigger circuit, responsive to the erase enable signal to output a clock signal;

[0008] A frequency dividing circuit is connected to the trigger circuit and the clock generator, and responds to the erase enable signal and the clock signal to output an erase drive signal with a preset duty cycle;

[0009] An erase control circuit is connected to the frequency division circuit and outputs an erase control signal in response to the erase drive signal;

[0010] The boost circuit is connected to the erase control circuit, the voltage source and the first electrode of the handwriting board membrane, generates a boost signal based on the erase control signal and the output voltage of the voltage source, and outputs the boost signal to the first electrode of the handwriting board membrane to erase the handwriting board.

[0011] Optionally, the trigger circuit includes a first trigger, a second trigger, a first timer and a first AND gate;

[0012] The first trigger includes a clock terminal connected to the erase instruction, a first output terminal connected to the input terminal of the first timer, a reset terminal connected to the output terminal of the first AND gate, a second output terminal connected to the clock terminal of the second trigger, and a data input terminal;

[0013] The second trigger comprises a data input terminal connected to a voltage source, a first output terminal for outputting an erase enable signal, and a reset terminal connected to an output terminal of the first AND gate;

[0014] The first AND gate further comprises a first input terminal connected to the output terminal of the timer and a second input terminal connected to an end reset signal for indicating the end of erasing.

[0015] Optionally, the frequency division circuit includes a trigger subcircuit and a logic subcircuit;

[0016] The trigger subcircuit comprises a first output terminal and a clock terminal, and a third trigger, a fourth trigger, a fifth trigger and a sixth trigger are connected in series in sequence; the clock terminal of the third trigger is connected to the clock generator;

[0017] The logic subcircuit includes a NOR gate, a second AND gate and a NAND gate;

[0018] The NOR gate comprises a first input terminal connected to the first output terminal of the fourth flip-flop, a second input terminal connected to the first output terminal of the fifth flip-flop, and an output terminal connected to the first input terminal of the second AND gate;

[0019] The second AND gate comprises a second input terminal connected to the first output terminal of the sixth flip-flop and an output terminal connected to the first input terminal of the NAND gate;

[0020] The NAND gate includes a second input terminal connected to the trigger circuit and an output terminal connected to the erase control circuit.

[0021] Optionally, the frequency division circuit further includes a second timer;

[0022] The second timer includes a first input terminal connected to the clock generator, a second input terminal connected to the trigger circuit, and an output terminal connected to the trigger circuit and the clock generator. The second timer is used to output an end reset signal to the trigger circuit and the clock generator to indicate the end of erasure after receiving a preset duration of an erase enable signal.

[0023] Optionally, the erase control circuit includes a transistor;

[0024] The transistor includes a control electrode connected to the frequency dividing circuit, a first electrode connected to the voltage boosting circuit, and a grounded second electrode.

[0025] Optionally, a signal driver is further provided between the frequency division circuit and the erase control circuit;

[0026] The signal driver includes an input end connected to the frequency division circuit and an output end connected to the erase control circuit. The signal driver is used to amplify the driving capability of the erase drive signal and output the amplified erase drive signal to the erase control circuit.

[0027] Optionally, the boost circuit includes an inductor, a diode, a first resistor and a first capacitor;

[0028] One end of the inductor is connected to a voltage source, and the other end is connected to an anode of a diode and an erase control circuit;

[0029] One end of the first capacitor is connected to the cathode of the diode, one end of the first resistor and the first electrode of the tablet film, and the other end of the first capacitor is connected to the other end of the first resistor and a voltage source.

[0030] Optionally, the handwriting board erasing circuit further includes a debouncing circuit; the debouncing circuit includes a second resistor, a third resistor, a second capacitor and a buffer;

[0031] One end of the second resistor is used to be connected to the erase button, and the other end is connected to one end of the second capacitor and the input end of the buffer;

[0032] One end of the third resistor is connected to one end of the second resistor, and the other end is grounded;

[0033] The other end of the second capacitor is grounded;

[0034] The output end of the buffer is used to output an erase instruction.

[0035] Optionally, the second electrode of the handwriting tablet membrane is connected to a voltage source.

[0036] In a second aspect, in one embodiment, the present application provides a chip including the handwriting board erasing circuit as described above.

[0037] Through the above technical solution, this application includes at least the following beneficial technical effects:

[0038] First, after receiving the erase instruction, the trigger circuit generates an erase enable signal, and transmits the erase enable signal to the clock generator and the frequency division circuit, so that the clock generator outputs a clock signal after receiving the erase enable signal, and outputs the clock signal to the frequency division circuit; the frequency division circuit starts working after receiving the erase enable signal to generate an erase drive signal with a preset duty cycle based on the clock signal. Next, the erase control circuit outputs an erase control signal for controlling the working state of the boost circuit based on the erase drive signal with a preset duty cycle, so that the erase control signal also has a preset duty cycle. Finally, after receiving the erase control signal, the boost circuit boosts the output voltage of the voltage source to obtain a boost signal. The boost signal is controlled to be adjusted to the required amplitude by the erase drive signal with a preset duty cycle, thereby achieving the effect of effectively erasing the content on the handwriting board membrane after the output voltage of the voltage source with a lower amplitude is boosted, thereby realizing the handwriting board erasing function in the scenario where the voltage source is powered by a low-voltage power supply such as a button battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is a structural diagram of a handwriting board erasing circuit in one embodiment of the present application.

[0041] Figure 2 A schematic diagram of a circuit implementation of a trigger circuit in one embodiment of the present application.

[0042] Figure 3 Schematic diagram of a circuit implementation of a frequency division circuit in one embodiment of the present application.

[0043] Figure 4 This is a schematic diagram of the circuit implementation of an erase control circuit, a boost circuit, and a signal driver in one embodiment of the present application.

[0044] Figure 5 A schematic diagram of a circuit implementation of a de-jitter circuit in one embodiment of the present application.

[0045] Explanation of the reference numerals: 1. trigger circuit; 11. first timer; 2. clock generator; 3. frequency division circuit; 31. trigger sub-circuit; 32. logic sub-circuit; 33. second timer; 4. erase control circuit; 5. boost circuit; 6. signal driver; 7. debouncing circuit; 100. handwriting tablet membrane. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0047] In the description of the present application, it should be understood that the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can also be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0048] First, as Figure 1 As shown, in one embodiment, the present application provides a handwriting board erasing circuit, which includes a trigger circuit 1, a clock generator 2, a frequency division circuit 3, an erasing control circuit 4 and a boost circuit 5.

[0049] Among them, the trigger circuit 1 receives the erase instruction and generates an erase enable signal based on the erase instruction. The clock generation is connected to the trigger circuit 1, and responds to the erase enable signal to output the clock signal. The frequency division circuit 3 is connected to the trigger circuit 1 and the clock generator 2, and responds to the erase enable signal and the clock signal to output an erase drive signal with a preset duty cycle. The erase control circuit 4 is connected to the frequency division circuit 3, and responds to the erase drive signal to output an erase control signal. The boost circuit 5 is connected to the erase control circuit 4, the voltage source VDD and the first electrode of the handwriting board diaphragm 100, generates a boost signal based on the erase control signal and the output voltage of the voltage source VDD, and outputs the boost signal to the first electrode of the handwriting board diaphragm 100 to erase the handwriting board.

[0050] The voltage source VDD may be a button battery, or other types of low-voltage power sources similar to a button battery.

[0051] The clock signal has a fixed frequency, so that the duration information can be obtained by calculating the number of cycles of the clock signal, so that the clock signal can be used as the basis for timing later.

[0052] In the above-mentioned implementation mode, first, the trigger circuit 1 generates an erase enable signal after receiving the erase instruction, and transmits the erase enable signal to the clock generator 2 and the frequency division circuit 3, so that the clock generator 2 outputs a clock signal after receiving the erase enable signal, and outputs the clock signal to the frequency division circuit 3. Then, the frequency division circuit 3 starts to work after receiving the erase enable signal, so as to generate an erase drive signal with a preset duty cycle based on the clock signal. Next, the erase control circuit 4 outputs an erase control signal for controlling the working state of the boost circuit 5 based on the erase drive signal with a preset duty cycle, so that the erase control signal also has a preset duty cycle. Finally, the boost circuit 5 boosts the output voltage of the voltage source VDD after receiving the erase control signal to obtain a boost signal. The boost signal is controlled to be adjusted to the desired amplitude by the erase drive signal with a preset duty cycle, thereby achieving the effect of effectively erasing the content on the handwriting board membrane 100 after the output voltage of the voltage source VDD with a lower amplitude is boosted, thereby realizing the handwriting board erasing function in the scenario where the voltage source VDD is powered by a button battery.

[0053] Reference Figure 2 As an implementation of the trigger circuit 1, the trigger circuit 1 includes a first trigger FF1, a second trigger FF2, a first timer 11 and a first AND gate U1.

[0054] The first trigger FF1 includes a clock terminal connected to the erase instruction, a first output terminal connected to the input terminal of the first timer 11, a reset terminal connected to the output terminal of the first AND gate U1, a second output terminal connected to the clock terminal of the second trigger FF2, and a data input terminal. The second trigger FF2 includes a data input terminal connected to the voltage source VDD, a first output terminal for outputting an erase enable signal, and a reset terminal connected to the output terminal of the first AND gate U1. The first AND gate U1 also includes a first input terminal connected to the output terminal of the first timer 11 and a second input terminal connected to an end reset signal for indicating the end of erase.

[0055] As an example, the first trigger FF1 and the second trigger FF2 can be D triggers. For example, in the initial state, the first timer 11, the first trigger FF1 and the second trigger FF2 are in an unstarted state, and a low-level signal is output at this time to indicate that no erase instruction is detected. When the erase instruction is received for the first time, the first output end of the first trigger FF1 outputs a high-level signal to the first timer 11, triggering the first timer 11 to start timing and output a high-level signal. At this time, the second output end of the first trigger FF1 is inverted with its first output end, that is, the second output end of the first trigger FF1 outputs a low-level signal, so that the second trigger FF2 is not started. When the erase instruction is received again within the preset timing duration of the first timer 11, the state of the output input terminal of the first trigger FF1 is written to its first output terminal. At this time, the first output terminal of the first trigger FF1 outputs a low-level signal to the first timer 11 to terminate the timing of the first timer 11 so that the output of the first timer 11 maintains a high-level signal. At the same time, the second output terminal of the first trigger FF1 outputs a high-level signal to the clock terminal of the second trigger FF2 to write the state of the data signal terminal of the second trigger terminal to its first output terminal. At this time, the first output terminal of the second trigger terminal outputs a high-level erase enable signal. When the erase instruction is not received again within the timing duration of the first timer 11, the first output terminal of the first trigger FF1 continues to output a high-level signal to the first timer 11, so that the first timer 11 maintains the timing state. After the preset timing duration of the first timer 11 ends, the first timer 11 outputs a low-level abort reset signal to reset the first trigger FF1 and the second trigger FF2. At this time, the first output terminal of the second trigger FF2 maintains a low-level signal and cannot output a valid erase enable signal. Combination Figure 2 , Figure 2 EN represents the erase enable signal, RES1 represents the end reset signal, and RES2 represents the abort reset signal.

[0056] It should be noted that the preset timing duration of the first timer 11 can be set according to actual needs, for example, the preset timing duration can be set to 1 second. The first trigger FF1 and the second trigger FF2 can be configured as rising edge triggering or falling edge triggering. The reset end of the first trigger FF1 and the reset end of the second trigger FF2 can be configured as low level valid or high level valid, which is not specifically limited here.

[0057] Combination Figure 2As an example, taking the reset end of the first trigger FF1 and the reset end of the second trigger FF2 being effective at a low level as an example, the first input end of the first AND gate U1 receives a stop reset signal for indicating the end of the timing of the first timer 11, and the second input end of the first AND gate U1 receives an end reset signal for indicating the end of erasure. When the first output end or the second output end of the first AND gate U1 changes to a low level, the output end of the first AND gate U1 outputs a low level signal to reset the first trigger FF1 and the second trigger FF2.

[0058] In the above embodiment, the second trigger FF2 can be triggered to output a high-level erase enable signal only when two erase instructions are received within the preset timing duration of the first timer 11. If only one erase instruction is received within the preset timing duration of the first timer 11, no valid erase enable signal can be output, and thus the content on the handwriting board cannot be erased. In this way, if the user accidentally touches the erase button and only outputs one erase instruction, the content on the handwriting board will not be erased, thereby reducing the occurrence of accidental erasure of the handwriting board content due to accidental touch by the user.

[0059] Reference Figure 3 As an implementation of the frequency division circuit 3, the frequency division circuit 3 includes a trigger subcircuit 31 and a logic subcircuit 32. The trigger subcircuit 31 includes a third trigger FF3, a fourth trigger FF4, a fifth trigger FF5 and a sixth trigger FF6, which are connected in series with the first output terminal and the clock terminal in sequence. The logic subcircuit 32 includes a NOR gate U2, a second AND gate U3 and a NAND gate U4.

[0060] The clock end of the third flip-flop FF3 is connected to the clock generator 2. The NOR gate U2 includes a first input end connected to the first output end of the fourth flip-flop FF4, a second input end connected to the first output end of the fifth flip-flop FF5, and an output end connected to the first input end of the second AND gate U3. The second AND gate U3 includes a second input end connected to the first output end of the sixth flip-flop FF6 and an output end connected to the first input end of the NAND gate U4. The NAND gate U4 includes a second input end connected to the trigger circuit 1 and an output end connected to the erase control circuit 4.

[0061] Among them, the first output terminal and the clock terminal are connected in series in sequence, which means that the first output terminal of the third trigger FF3 is connected to the clock terminal of the fourth trigger FF4, the first output terminal of the fourth trigger FF4 is connected to the clock terminal of the fifth trigger FF5, and the first output terminal of the fifth trigger FF5 is connected to the clock terminal of the sixth trigger FF6.

[0062] The trigger subcircuit 31 can output a plurality of signals of different periods obtained based on the clock signal, and the logic subcircuit 32 can perform logic operations on the signals of different periods to output a driving control signal with a preset duty cycle.

[0063] As an example, combining Figure 3 , Figure 3 Where CLK is the clock signal, RES1 is the end reset signal, and EN is the erase enable signal. The data signal terminals of the third flip-flop FF3, the fourth flip-flop FF4, the fifth flip-flop FF5, and the sixth flip-flop FF6 are connected to their respective second output terminals, so that the signal period output by the first output terminal of each flip-flop is half of the signal period input by its clock terminal. The clock signal output by the clock generator 2 is input to the clock terminal of the third flip-flop FF3, and the first output terminal of the third flip-flop FF3 outputs a signal with a period of half the clock signal period. By analogy, the first output terminal of the fourth flip-flop FF4 outputs a signal with a period of one-quarter the clock signal period, the first output terminal of the fifth flip-flop FF5 outputs a signal with a period of one-eighth the clock signal period, and the first output terminal of the sixth flip-flop FF6 outputs a signal with a period of one-sixteenth the clock signal period. Furthermore, in combination with the truth table of the NOR gate U2, the second AND gate U3 and the NAND gate U4, a signal with a period of one quarter of the clock signal is input to the first input terminal of the NOR gate U2, a signal with a period of one eighth of the clock signal is input to the second input terminal of the NOR gate U2, a signal with a period of one sixteenth of the clock signal is input to the first input terminal of the second AND gate U3, and the second input terminal of the last-stage NAND gate U4 is connected to the erase control signal, so that within the effective time of the erase control signal, the output terminal of the NAND gate U4 outputs an erase drive signal with a duty cycle of one eighth.

[0064] In the above implementation, the third trigger FF3, the fourth trigger FF4, the fifth trigger FF5 and the sixth trigger FF6 respectively output signals of different periods, and then the NOR gate U2, the second AND gate U3 and the NAND gate U4 perform logical operations on the signals of different periods to obtain an erase drive signal of a preset period.

[0065] Reference Figure 3 As a further implementation of the frequency dividing circuit 3 , the frequency dividing circuit 3 further includes a second timer 33 .

[0066] Among them, the second timer 33 includes a first input end connected to the clock generator 2, a second input end connected to the trigger circuit 1, and an output end connected to the trigger circuit 1 and the clock generator 2. The second timer 33 is used to output an end reset signal to the trigger circuit 1 and the clock generator 2 to indicate the end of erasure after receiving a preset duration of the erase enable signal.

[0067] Among them, different preset durations can be set by the second timer 33, and the preset duration is the erasing time of applying the boost signal to the handwriting tablet film 100. Different types of handwriting tablet films 100 can set different erasing times. For example, the preset duration of the second timer 33 can be set to 500ms.

[0068] As an example, the second timer 33 starts timing when it receives an enable signal from the trigger circuit 1. In the timing state of the second timer 33, the NAND gate U4 outputs an erase drive signal to control the handwriting board to erase. After the timing duration of the second timer 33 reaches the preset duration, the second timer 33 outputs an end reset signal to reset the trigger circuit 1 and the clock generator 2, so that the trigger circuit 1 stops outputting a high-level erase enable signal, and the clock generator 2 stops outputting a clock signal, thereby causing the trigger circuit 1 and the clock generator 2 to enter a low power consumption state, and the trigger subcircuit 31 and the logic subcircuit 32 in the frequency division circuit 3 also enter a low power consumption state due to the lack of a clock signal.

[0069] In the above embodiment, the second timer 33 is used to facilitate setting a suitable preset duration so that an erase drive signal is output to erase the handwriting board within the preset duration. After the preset duration, the second timer 33 outputs an end reset signal to cause the trigger circuit 1, the clock generator 2 and the frequency division circuit 3 to enter a low power consumption mode, so as to reduce the energy consumption of the handwriting board erasing function.

[0070] Reference Figure 4 As an implementation of the erase control circuit 4, the erase control circuit 4 includes a transistor Q1.

[0071] The transistor Q1 includes a control electrode connected to the frequency dividing circuit 3, a first electrode connected to the boosting circuit 5, and a grounded second electrode. The control electrode may be the gate of the transistor Q1, one of the first electrode and the second electrode may be the source, and the other may be the drain.

[0072] Reference Figure 4 As a further implementation of the handwriting erasing circuit, a signal driver 6 is further provided between the frequency dividing circuit 3 and the erasing control circuit 4 .

[0073] The signal driver 6 includes an input end connected to the frequency dividing circuit 3 and an output end connected to the erasure control circuit 4 . The signal driver 6 is used to amplify the driving capability of the erasure drive signal and output the amplified erasure drive signal to the erasure control circuit 4 .

[0074] As an example, the output terminal of the signal driver 6 may be connected to the control electrode of the transistor Q1 .

[0075] In the above embodiment, the erasing driving signal is amplified by the signal driver 6 so that the amplified erasing driving signal can stably drive the transistor Q1 to realize the erasing function of the handwriting board.

[0076] Reference Figure 4 As an implementation of the boost circuit 5 , the boost circuit 5 includes an inductor L, a diode D1 , a first resistor R1 , and a first capacitor C1 .

[0077] One end of the inductor L is connected to the voltage source VDD, and the other end is connected to the anode of the diode D1 and the erase control circuit 4. One end of the first capacitor C1 is connected to the cathode of the diode D1, one end of the first resistor R1 and the first electrode of the handwriting tablet film 100, and the other end of the first capacitor C1 is connected to the other end of the first resistor R1 and the voltage source VDD.

[0078] In the above embodiment, the erase control circuit 4 outputs an erase control signal with a preset duty cycle, so that the inductor L repeatedly stores and releases energy to generate an instantaneous high voltage potential, and then the high voltage potential is rectified and the output amplitude is adjusted through the diode D1, the first capacitor C1 and the first resistor R1 to obtain a boost signal applied to the handwriting board membrane 100.

[0079] Reference Figure 5 As a further implementation of the handwriting erasing circuit, the handwriting erasing circuit further includes an anti-jitter circuit 7. The anti-jitter circuit 7 includes a second resistor R2, a third resistor R3, a second capacitor C2 and a buffer U5.

[0080] Among them, one end of the second resistor R2 is used to be connected to the erase button, and the other end is connected to one end of the second capacitor C2 and the input end of the buffer U5. One end of the third resistor R3 is connected to one end of the second resistor R2, and the other end is grounded. The other end of the second capacitor C2 is grounded. The output end of the buffer U5 is used to output the erase instruction.

[0081] As an example, the charging process of the second capacitor C2 can smooth the jitter of the switch, so that the input end of the buffer U5 only receives a stable rising edge signal.

[0082] In the above embodiment, when the erase button is pressed, the voltage source VDD is connected to the second capacitor C2, and the output voltage of the voltage source VDD starts to charge the second capacitor C2. The second capacitor C2 is divided by the second resistor R2 and the third resistor R3 to provide a discharge path, and the signal output by the second capacitor C2 is buffered by the buffer U5, so as to output a stable erase instruction through the buffer U5, thereby preventing interference signals or accidentally touching the erase button for a short time and erroneously outputting an erase instruction, resulting in accidental erasure of the handwriting board.

[0083] Reference Figure 4 As a further implementation of the handwriting tablet film 100 , the second electrode of the handwriting tablet film 100 is connected to the voltage source VDD.

[0084] The first electrode of the handwriting tablet film 100 may be a positive electrode, and the second electrode may be a negative electrode.

[0085] In the above embodiment, since the amplitude of the boost signal output by the boost circuit 5 is higher than the output voltage of the voltage source VDD, during the erasing process of the handwriting board, the first electrode of the handwriting board membrane 100 is connected to the boost signal and the second electrode is connected to the output voltage of the voltage source VDD, so that the erasing function of the handwriting board can be realized. When the handwriting board does not need to be erased, the second electrode of the handwriting board membrane 100 is connected to the voltage source VDD, which can reduce the voltage difference between the first electrode and the second electrode of the handwriting board membrane 100, so as to reduce the static current consumption caused by the leakage of the handwriting board membrane 100, and further reduce the power consumption of the handwriting board.

[0086] In a second aspect, in one embodiment, the present application provides a chip including the handwriting board erasing circuit as described above.

[0087] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A handwriting board erasing circuit, characterized in that: include: A trigger circuit receives an erase instruction and generates an erase enable signal based on the erase instruction; a clock generator connected to the trigger circuit and responsive to the erase enable signal to output a clock signal; A frequency dividing circuit connected to the trigger circuit and the clock generator, responsive to the erase enable signal and the clock signal to output an erase drive signal with a preset duty cycle; An erase control circuit, connected to the frequency division circuit, and responsive to the erase drive signal to output an erase control signal; The boost circuit is connected to the erase control circuit, the voltage source and the first electrode of the handwriting board membrane, generates a boost signal based on the erase control signal and the output voltage of the voltage source, and outputs the boost signal to the first electrode of the handwriting board membrane to erase the handwriting board.

2. The handwriting board erasing circuit according to claim 1, characterized in that: The trigger circuit includes a first trigger, a second trigger, a first timer and a first AND gate; The first trigger includes a clock terminal connected to the erase instruction, a first output terminal connected to the input terminal of the first timer, a reset terminal connected to the output terminal of the first AND gate, a second output terminal connected to the clock terminal of the second trigger, and a data input terminal; The second trigger comprises a data input terminal connected to the voltage source, a first output terminal for outputting the erase enable signal, and a reset terminal connected to the output terminal of the first AND gate; The first AND gate includes a first input terminal connected to the output terminal of the first timer and a second input terminal connected to an end reset signal for indicating the end of erasing.

3. The handwriting board erasing circuit according to claim 2, characterized in that: The frequency division circuit includes a trigger subcircuit and a logic subcircuit; The trigger subcircuit comprises a first output terminal and a clock terminal, and a third trigger, a fourth trigger, a fifth trigger and a sixth trigger are connected in series in sequence; the clock terminal of the third trigger is connected to the clock generator; The logic subcircuit includes a NOR gate, a second AND gate and a NAND gate; The NOR gate comprises a first input terminal connected to the first output terminal of the fourth flip-flop, a second input terminal connected to the first output terminal of the fifth flip-flop, and an output terminal connected to the first input terminal of the second AND gate; The second AND gate comprises a second input terminal connected to the first output terminal of the sixth flip-flop and an output terminal connected to the first input terminal of the NAND gate; The NAND gate includes a second input terminal connected to the trigger circuit and an output terminal connected to the erase control circuit.

4. The handwriting board erasing circuit according to claim 3, characterized in that: The frequency division circuit also includes a second timer; The second timer includes a first input terminal connected to the clock generator, a second input terminal connected to the trigger circuit, and an output terminal connected to the trigger circuit and the clock generator. The second timer is used to output an end reset signal to the trigger circuit and the clock generator to indicate the end of erasure after receiving a preset duration of an erase enable signal.

5. The handwriting board erasing circuit according to claim 1, characterized in that: The erase control circuit includes a transistor; The transistor includes a control electrode connected to the frequency dividing circuit, a first electrode connected to the voltage boosting circuit, and a grounded second electrode.

6. The handwriting board erasing circuit according to claim 1, characterized in that: A signal driver is also provided between the frequency division circuit and the erasure control circuit; The signal driver includes an input end connected to the frequency division circuit and an output end connected to the erase control circuit. The signal driver is used to amplify the driving capability of the erase drive signal and output the amplified erase drive signal to the erase control circuit.

7. The handwriting board erasing circuit according to claim 1, characterized in that: The boost circuit includes an inductor, a diode, a first resistor and a first capacitor; One end of the inductor is connected to the voltage source, and the other end of the inductor is connected to the anode of the diode and the erase control circuit; One end of the first capacitor is connected to the cathode of the diode, one end of the first resistor and the first electrode of the tablet film, and the other end of the first capacitor is connected to the other end of the first resistor and the voltage source.

8. The handwriting board erasing circuit according to claim 1, characterized in that: The handwriting board erasing circuit also includes a de-jitter circuit; the de-jitter circuit includes a second resistor, a third resistor, a second capacitor and a buffer; One end of the second resistor is used to be connected to the erase button, and the other end is connected to one end of the second capacitor and the input end of the buffer; One end of the third resistor is connected to one end of the second resistor, and the other end is grounded; The other end of the second capacitor is grounded; The output end of the buffer is used to output the erase instruction.

9. The handwriting board erasing circuit according to any one of claims 1 to 8, characterized in that: The second electrode of the handwriting tablet membrane is connected to the voltage source.

10. A chip, characterized in that: include: A handwriting board erasing circuit as claimed in any one of claims 1 to 9.

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