Embedded packaging structure

Abstract

The utility model provides an embedded packaging structure of an integrated circuit and a power device. The embedded packaging structure is used for packaging a tube core of the integrated circuit and the power device on a resin carrier plate. A pressure welding point of the integrated circuit tube core is arranged on the surface of the chip; the surface of the power device is provided with pressure welding spots, and the back is other electrodes. A plurality of sinking grooves are formed in the surface of the resin carrier plate, and the depths of the sinking grooves are different so as to adapt to integrated circuit tube cores and power devices with different thicknesses; a conductive layer extending to the surface of the resin carrier plate is laid at the bottom of the sunken groove where the power device is embedded, a back electrode of the power device is in contact with the conductive layer, and the back electrode is led out and connected to the surface of the resin carrier plate through the conductive layer at the bottom of the sunken groove; pressure welding points on the surface of the integrated circuit, a surface electrode of the power device and a back electrode of the power device are all arranged on the surface of the resin carrier plate, a tube core of the integrated circuit is connected with the power device and provided with electric conductors communicated with the outside, and the part, except for the second electric conductor, of the surface electric conductor of the resin carrier plate is packaged by the packaging layer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor packaging technology, and in particular to an embedded packaging structure. Background Art

[0002] Different from the traditional chip packaging method, which is to package the chip after wafer cutting, Wafer Level Chip Scale Packaging (WLCSP) is an advanced electronic packaging technology based on BGA technology and improved CSP. Its main feature is that packaging and testing are completed directly before wafer cutting. According to different lead methods, wafer level packaging is mainly divided into fan-in wafer level packaging (Fan-In WLCSP) and fan-out wafer level packaging (Fan-Out WLCSP).

[0003] In current fan-in and fan-out packaging, all the pins of the die need to be on the same side of the wafer to facilitate subsequent wiring, ball implantation and other processes. However, in the fan-out packaging process, when some dies are discrete devices (such as power devices), the electrodes of the discrete devices are often blocked on the back of the device, but the electrodes need to be conductively connected, which makes the current fan-out packaging process unable to meet such requirements. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present disclosure is to provide an embedded packaging structure to solve the problems in the related art.

[0005] The first aspect of the present disclosure provides an embedded packaging structure, comprising: a resin carrier having a plurality of sunken grooves formed on its surface; a first wiring structure comprising: a conductive layer extending from the bottom of part of the sunken grooves to the surface of the resin carrier; an integrated circuit die and a power device respectively buried in the sunken grooves; a surface of the integrated circuit die having a welding point; in addition to the welding points on the surface, the power device also has a back electrode on the back side that contacts the conductive layer in the sunken grooves; a second wiring structure interconnected with the integrated circuit die and the power device, comprising: a conductor that interconnects the welding points on the surface of the integrated circuit die, the welding points on the surface of the power device, and the conductive layer on the surface of the resin carrier connected to the back electrode of the power device with the outside; and a packaging layer that packages the integrated circuit die and the power device on the resin carrier from the surface of the resin carrier.

[0006] In an embodiment of the first aspect, the depth of the sinker groove matches the thickness of the embedded integrated circuit die or power device.

[0007] In an embodiment of the first aspect, the conductor includes a first conductor for connecting the integrated circuit die and the pads of the power device, and a second conductor formed on the first conductor and the conductive layer on the surface of the resin carrier for external interconnection.

[0008] In an embodiment of the first aspect, the encapsulation layer exposes the second conductor.

[0009] As described above, the present disclosure provides an embedded packaging structure for integrated circuits and power devices, which is used to package integrated circuit dies and power devices on a resin carrier. The pressure welding points of the integrated circuit die are on the surface of the chip; the surface of the power device has pressure welding points, and the back is other electrodes. There are multiple sunken grooves on the surface of the resin carrier, and the depths of the sunken grooves are different to accommodate integrated circuit dies and power devices of different thicknesses; the bottom of the sunken groove in which the power device is buried is laid with a conductive layer extending to the surface of the resin carrier, and the back electrode of the power device contacts the conductive layer, and the back electrode is led out and connected to the surface of the resin carrier through the conductive layer at the bottom of the sunken groove; the pressure welding points on the surface of the integrated circuit, the surface electrodes of the power device, and the back electrodes of the power device are all on the surface of the resin carrier, and the integrated circuit die is interconnected with the power device, and there is a conductor connected to the outside, and the surface conductor of the resin carrier except the second conductor is encapsulated by the packaging layer. The packaging structure in the embodiment of the present disclosure can make the integrated chip die, the pressure welding points of the power device, and the back electrodes of the power device all be conveniently packaged, overcoming the shortcomings of the embedded packaging process in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram showing an embedded packaging structure in an embodiment of the present disclosure.

[0011] Figure 2 A schematic diagram showing a flow chart of an embedded packaging method in an embodiment of the present disclosure.

[0012] Figure 3 A schematic structural diagram of a mold used to form the resin carrier in one embodiment of the present disclosure is shown.

[0013] Figure 4 Shown in Figure 3 A schematic diagram of the structure of a resin carrier board formed by plastic encapsulation of the surface of the middle mold with, for example, a resin material.

[0014] Figure 5 Display pair Figure 4 Schematic diagram of the structure in which the resin carrier is separated from the mold.

[0015] Figure 6 Display pair Figure 5 Schematic diagram of the structure in which metal thin film is formed by metal sputtering on one side of the surface of the resin carrier obtained.

[0016] Figure 7 Display pair Figure 6 Schematic diagram of the structure of the conductive layer obtained by processing the metal film.

[0017] Figure 8 Demonstrate the embedding of integrated circuit dies and power devices into Figure 7 Schematic diagram of the structure of the sunken groove of the resin carrier. DETAILED DESCRIPTION

[0018] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0019] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0020] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0022] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0023] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0024] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0025] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0026] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0027] In current fan-in or fan-out packaging, all pins of the die need to be on the same side of the wafer. However, in the fan-out packaging process, some discrete devices have electrodes on the back side facing the resin carrier, and the electrodes need to be conductively connected but are blocked, resulting in the current fan-out packaging process being unable to meet this conductive connection requirement.

[0028] In view of this, an embedded packaging structure is provided in an embodiment of the present disclosure to solve the above-mentioned problem.

[0029] refer to Figure 1 , which is a schematic diagram showing an embedded packaging structure in an embodiment of the present disclosure.

[0030] exist Figure 1 In the embodiment, the embedded packaging structure includes a resin carrier 101, a first wiring structure 102, an integrated circuit die 104a, a power device 104b, a second wiring structure 105 and a packaging layer 106 which are arranged in sequence.

[0031] The resin carrier 101 has a surface 111, which is exemplified as an upper surface. The surface 111 is formed with a plurality of recessed grooves 112a, 112b. Figure 1 In the example, the surface 111 is presented as a horizontal plane. The multiple sunken grooves 112a, 112b are provided for matching and embedding the integrated circuit die 104a and the power device 104b. The thickness of different integrated circuit dies 104a and power devices 104b may be different. To this end, the depth of the sunken grooves 112a, 112b can be configured to match the thickness of the embedded integrated circuit die 104a and the power device 104b, respectively. Thus, when the integrated circuit die 104a and the power device 104b are inserted into the sunken grooves 112a, 112b having a depth matching their thickness, the surface exposed in the sunken grooves 112a, 112b (for example, the upper surface facing the same direction as the surface 111) can be kept basically flat with the surface 111 of the resin carrier 101. That is to say, corresponding to the packaging requirements of various embedded devices with different thicknesses, the sinking grooves 112a, 112b may also have corresponding different depths to set each integrated circuit die 104a and power device 104b to be packaged in a one-to-one matching manner. The sinking grooves 112a, 112b of different depths are used to adapt to the integrated circuit dies 104a and power devices 104b of different thicknesses. After the integrated circuit dies 104a and power devices 104b of different thicknesses are buried, the surface and the surface 111 can be kept basically flat. In addition, in some embodiments, the shape of each sinking groove 112a, 112b can also match the shape of the corresponding integrated circuit die 104a and power device 104b. In some embodiments, the width and / or length of each sinker groove 112a, 112b may also match the width and / or length of the corresponding combined integrated circuit die 104a or power device 104b so that the integrated circuit die 104a and the power device 104b are buried in the sinker grooves 112a, 112b with matching sizes.

[0032] The first wiring structure 102 includes a conductive layer 121 extending from the surface of the sinking groove 112b for setting the power device to the surface 111. That is, the conductive layer 121 includes a first portion 1211 located in the sinking groove 112b and a second portion 1212 extending to the surface 111. Exemplarily, the first portion 1211 may include a first sub-portion 12111 located at the bottom surface of the sinking groove 112b and a second sub-portion 12112 extending upward from the side wall of the sinking groove 112b. In some embodiments, the first wiring structure 102 can be formed by metal patterning technology, such as performing metal sputtering of a target material on one side of the surface 111 of the resin carrier 101, and then obtaining the first wiring structure 102 by photolithography, etching, etc.

[0033] The surfaces of the integrated circuit die 104a and the power device 104b may have bonding pads 141a and 141b, respectively. In addition, the sunken groove 112b provided with the conductive layer 121 may be used to provide the power device 104b with a back electrode 142b. Figure 1 As shown, the back electrode 142b of the power device 104b can be electrically connected to the first sub-portion 12111 of the conductive layer 121 at the bottom of the sinking groove 112b to form an electrical connection, and the back electrode 142b can be led to the surface 111 through the conductive layer 121. Thus, each of the bonding points 141a, 141b and the back electrode 142b are all led to the same surface 111, which is convenient for subsequent packaging.

[0034] The second wiring structure 105 is interconnected with the integrated circuit die 104a and the power device 104b. Specifically, the second wiring structure 105 includes: a conductor that interconnects the bonding pad 141a on the surface of the integrated circuit die 104a, the bonding pad 141b on the surface of the power device 104b, and the conductive layer 121 located on the surface 111 of the resin carrier 101 connected to the back electrode 142b of the power device 104b with the outside.

[0035] Exemplarily, the second wiring structure 105 may include a first conductor 151 and a second conductor 152. The first conductor 151 is formed by a redistribution layer (RDL) and is led out to a desired position by setting a second conductor 152, including a position outside the integrated circuit die 104a and the power device 104b. The second wiring structure 105 is formed on the surface 111. The plurality of first conductors 151 are electrically connected to the pads 141a and 141b of the integrated circuit die 104a and the power device 104, respectively, and the second conductor 152 is led out at a predetermined position on the surface 111 for external conductive connection of the pads 141a and 141b. In addition, the conductive layer 121 may also be provided with a second conductor 152 at a predetermined position on the surface 111 for external conductive connection of the back electrode 142b.

[0036] The packaging layer 106 packages the integrated circuit die 104a and the power devices 104b, 104b on the resin carrier 101 from the surface 111 side, and leads out a second conductor 152 conductively connected to the pads 141a, 141b and the back electrode 142b.

[0037] Exemplarily, the encapsulation layer 106 covers the second wiring structure 105 on the resin carrier 101 and exposes the second conductor 152. The encapsulation layer 106 may be provided with a hole to expose the second conductor 152. Further exemplary, the encapsulation layer 106 may be an organic polymer material, such as polyimide (PI). Exemplarily, each of the second conductors 152 may be a solder ball obtained by ball grid array (BGA) packaging.

[0038] refer to Figure 2 As shown, a schematic diagram of the process of the embedded packaging method in one embodiment of the present disclosure is shown. The embedded packaging method can be used to prepare a reference Figure 1 The embedded package structure shown in .

[0039] exist Figure 2 The process specifically includes:

[0040] Step S201 : forming a plurality of sunken grooves 112 a and 112 b on the surface of the resin carrier 101 .

[0041] As an example, refer to Figures 3 to 5 As shown. Figure 3 In FIG. 1 , a mold 201 for forming the resin carrier 101 is shown. Figure 4 In the figure, the surface of the mold 201 is encapsulated with a resin material, for example, so that the protrusions on the surface of the mold 201 are completely covered with the resin, forming the resin carrier 101. Figure 5In the process, the resin carrier 101 is separated from the mold 201 to obtain an independent resin carrier 101.

[0042] Step S202: forming a first wiring structure on the surface of the resin carrier, wherein the first wiring structure comprises a conductive layer extending from a portion of the bottom of the sinking groove to the surface.

[0043] As an example, refer to Figure 6 to Figure 7 As shown. Figure 6 In FIG. 1 , metal sputtering is performed on one side of the surface of the resin carrier 101 to form a metal film 301. Figure 7 It is shown that the metal film 301 is processed by photolithography, etching, etc. to retain the conductive layer 121 extending from the bottom surface of the sinking groove 112b to the surface 111.

[0044] Step S203: embed the integrated circuit die and the power device into the sinking groove respectively, so that the bonding points on the surfaces of the integrated circuit die and the power device are exposed, and the back electrode of the power device contacts the conductive layer in the sinking groove.

[0045] For reference Figure 8 As shown. As an example, the depth of the sinking grooves 112a, 112b is configured to match the thickness of the embedded integrated circuit die 104a and the power device 104b, so that the outward surface of the embedded integrated circuit die 104a and the power device 104b remains basically flat with the surface. The surfaces of the integrated circuit die 104a and the power device 104b are provided with welding points 141a, 141b. The conductive layer 121 includes a first sub-portion 12111 provided on the bottom surface of the sinking groove 112b. The back surface of the power device 104b facing the bottom surface of the sinking groove 112b may be provided with a back electrode 142b for forming a conductive contact with the first sub-portion 12111.

[0046] Step S204: forming a second wiring structure interconnected with the integrated circuit die and the power device on the integrated circuit die and the power device, the second wiring structure comprising: a conductor interconnecting the bonding pads on the surface of the integrated circuit die, the bonding pads on the surface of the power device, and the conductive layer on the surface of the resin carrier board connected to the back electrode of the power device with the outside.

[0047] Specifically, a second wiring structure 105 is formed on the surface 111 of the resin carrier 101. The conductors in the second wiring structure 105 include a plurality of first conductors 151, which are electrically connected to the pads 141a and 141b of the integrated circuit die 104a and the power device 104b, respectively, and a second conductor 152 is led out at a predetermined position of the conductive layer 121 on the surface 111. Exemplarily, the second conductor 152 can be implemented as a package solder joint, such as a solder ball formed by a BGA package.

[0048] Step S205: encapsulating the integrated circuit die and the power device on the resin carrier from one side of the surface of the resin carrier.

[0049] Specifically, the encapsulation layer may be an insulating layer made of materials such as PI.

[0050] Thus, we get Figure 1 Embedded packaging structure in.

[0051] It can be seen that by leading the back electrode on the back of the power device to the surface through the first wiring structure, in addition, the integrated circuit die and the power device can be buried in a sunken groove with a depth matching their thickness, so that the solder joints on the surface of the die are basically flat with the surface, and then RDL packaging is performed on the surface to facilitate leading the conductor from the solder joints and the back electrode at the same time, thereby realizing an improved embedded packaging structure process and solving the problems in the related technology.

[0052] In summary, the present disclosure provides an embedded packaging structure for integrated circuits and power devices, which is used to package integrated circuit dies and power devices on a resin carrier. The pressure welding points of the integrated circuit die are on the surface of the chip; the surface of the power device has pressure welding points, and the back is other electrodes. There are multiple sunken grooves on the surface of the resin carrier, and the depths of the sunken grooves are different to accommodate integrated circuit dies and power devices of different thicknesses; a conductive layer extending to the surface of the resin carrier is laid at the bottom of the sunken groove in which the power device is buried, and the back electrode of the power device contacts the conductive layer, and the back electrode is led out and connected to the surface of the resin carrier through the conductive layer at the bottom of the sunken groove; each pressure welding point on the surface of the integrated circuit, the surface electrode of the power device, and the back electrode of the power device are all on the surface of the resin carrier, the integrated circuit die and the power device are interconnected, and there is a conductor connected to the outside, and the surface conductor of the resin carrier except the second conductor is encapsulated by the packaging layer.

[0053] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. An embedded packaging structure, characterized in that: include: A resin carrier plate having a plurality of sunken grooves formed on its surface; The first wiring structure includes: a conductive layer extending from the bottom of a portion of the sinking groove to the surface of the resin carrier; The integrated circuit die and the power device are respectively buried in the sinking grooves; The surface of the integrated circuit die has bonding pads; In addition to the bonding pad on the surface, the power device also has a back electrode on the back side that contacts the conductive layer in the sunken groove. The second wiring structure interconnects the integrated circuit die and the power device, including: a conductor that interconnects the bonding pads on the surface of the integrated circuit die, the bonding pads on the surface of the power device, and the conductive layer on the surface of the resin carrier connected to the back electrode of the power device with the outside; The packaging layer packages the integrated circuit die and the power device on the resin carrier from the surface of the resin carrier.

2. The embedded packaging structure according to claim 1, characterized in that: The depth of the sinking groove matches the thickness of the embedded integrated circuit die or power device.

3. The embedded packaging structure according to claim 1, characterized in that: The conductors include a first conductor for connecting the integrated circuit die and the pads of the power device, and a second conductor formed on the first conductor and the conductive layer on the surface of the resin carrier for external interconnection.

4. The embedded packaging structure according to claim 3, characterized in that: The packaging layer exposes the second conductor.

5. The embedded packaging structure according to claim 1, characterized in that: The shape of the sinking groove matches the shape of the corresponding integrated circuit die or power device.

6. The embedded packaging structure according to claim 1, characterized in that: The width and / or length of the sinker groove matches the width and / or length of the corresponding integrated circuit die or power device.

7. The embedded packaging structure according to claim 3, characterized in that: The first electrical conductor is formed by a redistribution layer.

8. The embedded packaging structure according to claim 3, characterized in that: The second conductor is a packaging solder joint.

9. The embedded packaging structure according to claim 3, characterized in that: The second conductor is a solder ball formed by BGA packaging.

10. The embedded packaging structure according to claim 1, characterized in that: The conductive layer includes a first portion located in the sinking groove and a second portion extending to the surface of the resin carrier; the first portion includes a first sub-portion located at the bottom surface of the sinking groove and a second sub-portion extending upward from the side wall of the sinking groove.

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