Chip adapter plate, PCB assembly and vehicle

Abstract

The utility model relates to the technical field of circuit boards, and discloses a chip adapter plate, a PCB assembly and a vehicle, the chip adapter plate comprises a first conductive layer, a middle conductive layer and a second conductive layer which are arranged in sequence; the number of the middle conducting layers is multiple; the first conductive layer is provided with a plurality of first connecting structures; the first connection structures are used for being connected with pins of a target chip, and the distribution positions of the multiple first connection structures are in one-to-one correspondence with the distribution positions of the pins of the target chip; the second conductive layer is provided with a plurality of second connecting structures corresponding to the first connecting structures; the second connecting structure is used for being connected with a bonding pad of the PCB mainboard; the distance between the second connecting structures is larger than that between the first connecting structures. The first connecting structures are connected with the corresponding second connecting structures through fan-out lines. According to the utility model, the distribution sparsification of the chip pins can be realized, the requirement on the number of layers of the PCB mainboard is reduced, and the cost is effectively reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit boards, and in particular to a chip adapter board, a PCB assembly and a vehicle. Background Art

[0002] With the continuous advancement of chip production technology and the gradual increase in demand, chip functions are highly integrated and miniaturized, with more and more chip pins and smaller and smaller pin spacing. When designing a PCB (Printed Circuit Board), the number of layers of the PCB board mainly depends on the fan-out requirements of the chip with the densest pins. The more layers of the PCB board, the more expensive it is, resulting in more layers of PCB board when densely pinned chips are used. Utility Model Content

[0003] In view of this, the utility model provides a chip adapter board, a PCB assembly and a vehicle to solve the problem of a large number of PCB layers.

[0004] In a first aspect, the utility model provides a chip adapter board, comprising: a first conductive layer, an intermediate conductive layer, and a second conductive layer arranged in sequence; the intermediate conductive layer is multi-layered;

[0005] The first conductive layer is provided with a plurality of first connection structures; the first connection structures are used to be connected to pins of a target chip, and the distribution positions of the plurality of first connection structures correspond one to one to the distribution positions of the pins of the target chip;

[0006] The second conductive layer is provided with a plurality of second connection structures corresponding to the first connection structures; the second connection structures are used to be connected to the pads of the PCB mainboard; the spacing between the second connection structures is greater than the spacing between the first connection structures;

[0007] The first connection structure is connected to the corresponding second connection structure through a fan-out line.

[0008] In some optional embodiments, the first connection structure of the first part is connected to the corresponding second connection structure through a first fan-out line; the first connection structure of the second part is connected to the corresponding second connection structure through a second fan-out line; the routing layer corresponding to the first fan-out line is the first conductive layer, and the routing layer corresponding to the second fan-out line is the intermediate conductive layer.

[0009] In some optional embodiments, the first fan-out line includes a first conductive line distributed in the first conductive layer and a first via line arranged along the first via; the first via is a through hole; the second fan-out line includes a second via line arranged along the second via, a second conductive line distributed in the intermediate conductive layer, and a third via line arranged along the third via; the second via is a via that at least passes through the first conductive layer and the intermediate conductive layer, and the third via is a via that at least passes through the intermediate conductive layer and the second conductive layer.

[0010] In some optional implementations, the first connection structure of the third part is connected to the corresponding second connection structure through a third fan-out line; and the routing layer corresponding to the third fan-out line is the second conductive layer.

[0011] In some optional implementations, the third fan-out line includes a fourth via line arranged along a fourth via hole and a third conductive line distributed in the second conductive layer; and the fourth via hole is a through hole.

[0012] In some optional embodiments, the spacing of the second connection structure is not less than the spacing required to achieve n-layer fan-out, where n is the number of layers of the PCB mainboard.

[0013] In some optional embodiments, the intermediate conductive layer includes: a signal layer, a power layer and a ground layer.

[0014] In some optional embodiments, the first conductive layer and the second conductive layer are also signal layers, and the multiple signal layers are evenly distributed.

[0015] In a second aspect, the utility model provides a PCB assembly, comprising: a PCB main board and a chip adapter board according to the first aspect or any corresponding embodiment thereof.

[0016] In some optional embodiments, the number of layers of the PCB main board is less than the number of layers of the chip adapter board.

[0017] In a third aspect, the utility model provides a vehicle, comprising: a PCB assembly according to the second aspect or any corresponding embodiment thereof.

[0018] In this embodiment, a first connection structure for connecting to the chip pin is provided on the first conductive layer, a more sparse second connection structure is provided on the second conductive layer, and corresponding fan-out lines are arranged using multiple conductive layers to realize interconnection between the first connection structure and the second connection structure, thereby making the chip pin distribution sparse, which can reduce the number of layers required for the PCB motherboard. The PCB motherboard can realize fan-out of the second connection structure with fewer layers, effectively reducing the cost. Since the chip area is small, the area of ​​the chip adapter board that is only suitable for fanning out the chip pins will not be very large, and the cost of the chip adapter board is low, which is still lower than the solution of directly increasing the number of layers of the PCB motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 is a cross-sectional schematic diagram of a chip adapter board according to an embodiment of the utility model;

[0021] Figure 2 This is a schematic diagram of an application of a chip adapter board according to an embodiment of the utility model;

[0022] Figure 3 It is a cross-sectional schematic diagram of a partial structure of a chip transfer board according to an embodiment of the utility model;

[0023] Figure 4 According to the embodiment of the utility model Figure 3 The fan-out line schematic diagram of the chip adapter board shown;

[0024] Figure 5 is a schematic top view of a partial structure of a first conductive layer according to an embodiment of the utility model;

[0025] Figure 6 It is a specific application schematic diagram of the chip adapter board according to the embodiment of the utility model.

[0026] Description of reference numerals:

[0027] 10. First conductive layer; 20. Middle conductive layer; 30. Second conductive layer; 40. Fan-out line; 11. First connection structure; 31. Second connection structure; 101. First via hole; 102. Second via hole; 103. Third via hole; 104. Fourth via hole; 41. First fan-out line; 411. First conductor; 412. First via line; 42. Second fan-out line; 421. Second via line; 422. Second conductor; 423. Third via line; 43. Third fan-out line; 431. Fourth via line; 432. Third conductor; 1. Chip adapter board; 2. Target chip; 3. PCB motherboard. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0029] In the description of the present invention, it should be understood that terms indicating orientation or positional relationships, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., are based on the orientation or positional relationships shown in the drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0031] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] In addition, in order to better illustrate the utility model, numerous specific details are given in the specific embodiments below. It should be understood by those skilled in the art that the utility model can also be implemented without certain specific details. In some examples, methods, means, and elements well known to those skilled in the art are not described in detail in order to highlight the main purpose of the utility model.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] At present, in order not to affect the normal fan-out of dense pin chips, HDI (high-density interconnect) technology can be used, but the cost of DHI technology is relatively high; if the current number of layers of the PCB board is not enough to achieve the normal fan-out of dense pin chips, the number of layers of the PCB board needs to be increased. For example, a PCB board only needs 4 layers to complete the layout of each circuit module, but if the introduced dense pin chip requires 8 layers to fan out, the number of layers of the PCB board needs to be increased to 8, which instantly leads to a rapid increase in costs.

[0035] The present invention provides a chip adapter board, which is used to install a chip on a PCB board (hereinafter referred to as a PCB main board) that needs to use the chip, without using HDI technology or increasing the number of layers of the PCB main board. For example, the number of layers of the PCB main board can remain unchanged. Specifically, the chip adapter board can be a multi-layer PCB board. Figure 1 As shown, the chip transfer board includes: a first conductive layer 10, an intermediate conductive layer 20 and a second conductive layer 30 arranged in sequence; the intermediate conductive layer 20 is multi-layered. Figure 1 An example is shown in which two intermediate conductive layers 20 are included.

[0036] The first conductive layer 10, the middle conductive layer 20 and the second conductive layer 30 are all conductive layers for realizing routing, such as copper foil layers. Figure 1 As shown, an insulating layer, such as a core layer (Core) or a semi-solid sheet (Prepreg), is provided between two adjacent conductive layers. Figure 2 An application schematic diagram of the chip adapter board is shown in FIG. Figure 2 As shown, the chip adapter board 1 is arranged between the target chip 2 and the PCB main board 3 to achieve the installation of the target chip 2 on the PCB main board 3.

[0037] Specifically, in this embodiment, the first conductive layer 10 is provided with a plurality of first connection structures 11 ; the first connection structures 11 are used to be connected to the pins of the target chip 2 , and the distribution positions of the plurality of first connection structures 11 correspond one-to-one to the distribution positions of the pins of the target chip 2 .

[0038] The second conductive layer 30 is provided with a plurality of second connection structures 31 corresponding to the first connection structures 11 ; the second connection structures 31 are used to be connected to the pads of the PCB main board 3 ; and the spacing between the second connection structures 31 is greater than the spacing between the first connection structures 11 .

[0039] The first connection structure 11 is connected to the corresponding second connection structure 31 through the fan-out line 40 .

[0040] In this embodiment, the first conductive layer 10 may be the top layer (Top) of the chip adapter board, and the second conductive layer 30 may be the bottom layer (Bottom) of the chip adapter board, and the first conductive layer 10 and the second conductive layer 30 are respectively provided with connection structures for connecting with other components, and the connection structures may be, for example, pads, pins, etc. Figure 1 As shown, the first conductive layer 10 is provided with a plurality of first connection structures 11 corresponding to the pin distribution positions of the target chip 2, and the first connection structure can be specifically a pad to be welded with the pins of the target chip 2; and the second conductive layer 30 is provided with a plurality of second connection structures 31, and these second connection structures 31 are also one-to-one corresponding to the first connection structures 11, that is, the second connection structures 31 can also correspond one-to-one to the pins of the target chip. The second connection structure 31 can be a pad or a pin, which can be determined based on actual needs.

[0041] Moreover, the spacing of the second connection structures 31 is greater than the spacing of the first connection structures 11, that is, the first connection structures 11 for connecting the pins of the target chip 2 are relatively dense, while the second connection structures 31 for connecting the PCB main board 3 are more sparse. In addition, the fan-out of the first connection structure 11 is realized through the fan-out line 40, so that the first connection structure 11 can be connected to the corresponding second connection structure 31, and the dense pins of the target chip 2 are converted into the relatively sparse second connection structure 31, which is connected to the PCB main board 3 by the sparse second connection structure 31, thereby reducing the number of layers required for the PCB main board 3.

[0042] The chip adapter provided by the embodiment of the utility model has a first connection structure 11 for connecting to the chip pins on the first conductive layer 10, a more sparse second connection structure 31 on the second conductive layer 30, and uses multiple conductive layers to lay corresponding fan-out lines to achieve interconnection between the first connection structure 11 and the second connection structure 31, so that the chip pin distribution is sparse, which can reduce the number of layers required for the PCB motherboard 3. The PCB motherboard 3 can achieve fan-out of the second connection structure 31 with fewer layers, effectively reducing the cost. Since the chip area is small, the area of ​​the chip adapter only suitable for fanning out the chip pins will not be very large, and the cost of the chip adapter is low, which is still lower than the solution of directly increasing the number of layers of the PCB motherboard.

[0043] In some optional implementations, when setting the fan-out line 40, the first conductive layer 10, the middle conductive layer 20, etc. need to be used as corresponding routing layers to achieve fan-out; wherein the routing layers corresponding to different fan-out lines 40 may be different. Specifically, in this embodiment, a plurality of first connection structures 11 are divided based on different routing layers.

[0044] Specifically, the fan-out line 40 whose corresponding routing layer is the first conductive layer 10 is called a first fan-out line 41, and the fan-out line 40 whose corresponding routing layer is the middle conductive layer 20 is called a second fan-out line 42. Correspondingly, for the multiple first connection structures 11 of the first conductive layer 10, the first connection structures 11 of the first part are connected to the corresponding second connection structures 31 through the first fan-out line 41; the first connection structures 11 of the second part are connected to the corresponding second connection structures 31 through the second fan-out line 42.

[0045] In this embodiment, different fan-out lines can be routed on different conductive layers, so that the multi-layer structure of the chip adapter can be fully utilized, which is conducive to realizing multi-layer fan-out.

[0046] In addition, optionally, if the second conductive layer 30 can also be used as a routing layer for one or some fan-out lines 40, the fan-out line 40 whose corresponding routing layer is the second conductive layer 30 is called a third fan-out line 43, and the first connection structure 11 of the third part is connected to the corresponding second connection structure 31 through the third fan-out line 43. The bottom second conductive layer 30 is also used as a routing layer for the fan-out line 40, that is, the fan-out line 40 can also be routed on the second conductive layer 30, which can further improve the utilization rate of the multi-layer conductive layer, and the chip adapter board has a compact structure.

[0047] Figure 3 FIG. 4 shows a cross-sectional schematic diagram of a portion of the chip transfer board structure. Figure 3As shown, in order to connect the first connection structure 11 and the second connection structure 31, the fan-out line 40 needs to pass through certain vias; and the fan-out line 40 also needs to be routed on a certain conductive layer to achieve fan-out, and the conductive layer is called the routing layer of the fan-out line 40. Figure 3 As shown, the fan-out line on the far left is the first fan-out line 41, and its horizontal routing is located in the first conductive layer 10; the fan-out line on the far right is the third fan-out line 43, and its horizontal routing is located in the second conductive layer 30; and the two middle fan-out lines are the second fan-out line 42, and their horizontal routing is located in a middle conductive layer 20.

[0048] For example, the first connection structures 11 at the periphery may be used as the first connection structures 11 of the first part, the first connection structures 11 at the center may be used as the first connection structures 11 of the third part, and the remaining first connection structures 11 may be used as the first connection structures 11 of the second part. Alternatively, the first connection structures 11 at one side (e.g., the left side) may be used as the first connection structures 11 of the third part, the first connection structures 11 at the other side (e.g., the right side) corresponding to the side may be used as the first connection structures 11 of the first part, and the remaining first connection structures 11 may be used as the first connection structures 11 of the second part.

[0049] In the embodiment of the present invention, the fan-out line 40 needs to pass through certain vias, based on which the fan-out line 40 can be divided into multiple parts. Figure 4 Shows Figure 3 The fan-out lines of the chip interposer shown; see Figure 3 and Figure 4 As shown, the first fan-out line 41 includes a first conductive line 411 distributed in the first conductive layer 10 and a first via line 412 arranged along the first via hole 101; the first via hole 101 is a through hole.

[0050] The second fan-out line 42 includes a second via line 421 arranged along the second via 102, a second wire 422 distributed in the middle conductive layer 20, and a third via line 423 arranged along the third via 103; the second via 102 is a via that at least passes through the first conductive layer 10 and the middle conductive layer 20, and the third via 103 is a via that at least passes through the middle conductive layer 20 and the second conductive layer 30.

[0051] The third fan-out line 43 includes a fourth via line 431 disposed along the fourth via hole 104 and a third conductive line 432 distributed in the second conductive layer 30 ; the fourth via hole 104 is a through hole.

[0052] In this embodiment, the chip adapter is provided with a plurality of vias, which may be through holes, for example, the first via 101 and the fourth via 104 are through holes, that is, the first via 101 and the fourth via 104 may be the chip adapter; some vias may also be blind holes with a certain depth, for example, the second via 102 and the third via 103 may be blind holes, wherein the second via 102 at least penetrates the first conductive layer 10 and the corresponding intermediate conductive layer 20, so that the second via line 421 in the second via 102 may realize the interconnection between the first connection structure 11 and the second conductive wire 422; and the third via 103 at least penetrates the intermediate conductive layer 20 and the corresponding second conductive layer 30, so that the third via line 423 in the third via 103 may realize the interconnection between the second conductive wire 422 and the second connection structure 31. Of course, if the structure allows, the second via 102 and the third via 103 may also be through holes, which is determined based on the actual situation.

[0053] In order to facilitate the description, the wiring on the wiring layer is called "wire", such as the first wire 411, the second wire 422, the third wire 432, etc.; the wiring set in the via hole is called "hole wire", such as the first hole wire 412, the second hole wire 421, the third hole wire 423, the fourth hole wire 431, etc. It can be understood that the hole wire is a wiring (such as a copper wire) set on the hole wall. Figure 3 In order to facilitate the distinction between hole lines and vias, the hole lines are schematically shown as being separated from the via hole walls.

[0054] Figure 5 A schematic top view of a partial structure of the first conductive layer 10 is shown. Figure 5 The black circles in the figure represent the first connection structures 11, and the white circles represent the corresponding vias, such as the first via 101, the second via 102, etc. The first connection structures 11 correspond one-to-one to the chip pins of the ball grid array (BGA) package.

[0055] in, Figure 5 The first connection structures 11 in the first row and the second row are the first connection structures 11 of the first part, and the first conductive layer 10 is provided with a first wire 411 routed to the corresponding first via hole 101, so that the first wire 411 can be connected to the first via line 412 in the first via hole 101 to form a first fan-out line 41. The principles of the second fan-out line 42 and the third fan-out line 43 are similar to this, and are not described in detail here.

[0056] In this embodiment, the first connection structure 11 may be located at the same position as some of the vias (e.g., the second via 102 and the fourth via 104), or the first connection structure 11 may be located at different positions from these vias and correspond one to one. In this case, similar to the arrangement of the first conductive wire 411, Figure 5As shown, it is necessary to set a corresponding connecting line 4111 in the first conductive layer 10, based on the connecting line 4111, the first connecting structure 11 ( Figure 5 The first connection structures 11 in the third and fourth rows can be connected to the second via lines 421 in the second via holes 102 , thereby forming the second fan-out lines 42 .

[0057] It can be understood that which first connection structures 11 can be used as the first connection structures 11 of the first part can be determined based on the spacing of the first connection structures 11. Figure 5 As shown, if the spacing between the first connection structures 11 allows for an additional wire to be routed, two rows of first connection structures 11 can be used as the first connection structures 11 of the first part; if the spacing between the first connection structures 11 is too small to meet the requirement for additional routing, only the first connection structures 11 in the outermost row can be used as the first connection structures 11 of the first part.

[0058] In this embodiment, the fan-out line is formed by combining the hole line in the via hole and the wire routed in the conductive layer, so that the connection between the first connection structure and the second connection structure can be easily realized. In addition, for the fan-out line using the middle conductive layer as the routing layer, its via hole may not be a through hole, which can effectively reduce the number of via holes in the first conductive layer 10 and the second conductive layer 30 to avoid affecting the fan-out.

[0059] In some optional embodiments, the spacing of the second connection structure 31 can be set based on the number of layers n of the PCB main board 3; specifically, the spacing of the second connection structure 31 is not less than the spacing required to achieve n-layer fan-out, so that after the chip adapter board expands the spacing of the second connection structure 31, the n-layer PCB main board 3 can continue to perform n-layer fan-out on the second connection structure 31, so that the fan-out wires can be led to the corresponding circuit modules in the PCB main board 3.

[0060] In addition, after determining the spacing of the second connection structure 31, the number of layers of the chip adapter board can be determined based on the spacing of the first connection structure 11 and the spacing of the second connection structure 31. The number of layers of the chip adapter board needs to meet the requirement of fanning out the first connection structure 11 to the second connection structure 31.

[0061] Optionally, the middle conductive layer 20 includes: a signal layer, a power layer and a ground layer, which are used to transmit data signals, power signals and ground signals respectively. Optionally, the first conductive layer 10 and the second conductive layer 30 are also signal layers, and the multiple signal layers are evenly distributed. The chip adapter is provided with conductive layers with multiple functions, which can realize the transmission of multiple signals; and the signal layers are evenly distributed, which can minimize the impact between the signal layers.

[0062] Figure 6 FIG. 1 shows a specific application schematic diagram of the chip adapter board. Figure 6 As shown, the PCB main board 3 is a four-layer board, specifically including a top layer (TOP), a ground layer (GND2), a power layer (PWR3) and a bottom layer (BOTTOM), wherein the top layer and the bottom layer are signal layers. If the target chip 2 with dense pins requires a four-layer signal layer fan-out, the PCB main board 3 has only two signal layers, the top layer and the bottom layer, which do not meet the fan-out requirements, so the chip adapter board 1 provided in this embodiment can be introduced, such as a 6-layer or 8-layer chip adapter board, etc. Figure 6 The chip transfer board 1 is taken as an example of an 8-layer board.

[0063] like Figure 6 As shown, the chip adapter board 1 includes a top layer (TOP), a ground layer (GND2), a signal layer (SIGNAL3), a power layer (PWR4), a ground layer (GND5), a signal layer (SIGNAL6), a power layer (PWR7) and a bottom layer (BOTTOM), wherein the top layer is a first conductive layer 10, the bottom layer is a second conductive layer 30, and the remaining six layers are intermediate conductive layers 20.

[0064] The target chip 2 with dense pins is welded to the top layer (TOP) of the chip adapter board 1, and fan-out can be performed based on the top layer (TOP), signal layer (SIGNAL3), signal layer (SIGNAL6) and bottom layer (BOTTOM). The remaining power layers and ground layers are provided with corresponding power lines and ground lines. After normal fan-out, the chip adapter board 1 can lead the signal line to the second connection structure 31 of the bottom layer, and weld the chip adapter board 1 to the PCB main board 3 based on the second connection structure 31. Since the solder joints on the PCB main board 3 are sparsely distributed, they can be fanned out at the top and bottom layers, and then led to each corresponding circuit module after fanning out.

[0065] The present invention also provides a PCB assembly, which includes: a PCB main board 3 and a chip adapter board 1 as described in the above embodiment, wherein the PCB main board 3 is connected to the second connection structure 31 of the chip adapter board 1. The PCB assembly as a whole also has a low-cost effect, which will not be described in detail here.

[0066] Optionally, the number of layers of the PCB main board 3 is less than that of the chip adapter board, that is, the chip adapter board has a larger number of layers, which can more effectively utilize the fan-out function of the chip adapter board, ensuring that the overall cost of the chip adapter board + PCB main board 3 is also relatively low.

[0067] The embodiment of the utility model further provides a vehicle, which includes: the PCB assembly as described in the above embodiment. For example, for a control board in a vehicle that needs to use a PCB mainboard 3 to implement a control function, the PCB assembly can be used, that is, the pins of the target chip 2 are fanned out in multiple layers using a chip adapter board, thereby reducing costs.

[0068] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip adapter board, characterized in that: include: A first conductive layer (10), an intermediate conductive layer (20) and a second conductive layer (30) are sequentially arranged; the intermediate conductive layer (20) is a multi-layer layer; The first conductive layer (10) is provided with a plurality of first connection structures (11); the first connection structures (11) are used to be connected to pins of a target chip (2), and the distribution positions of the plurality of first connection structures (11) correspond one-to-one to the distribution positions of the pins of the target chip (2); The second conductive layer (30) is provided with a plurality of second connection structures (31) corresponding to the first connection structures (11); the second connection structures (31) are used to be connected to the pads of the PCB mainboard (3); the spacing between the second connection structures (31) is greater than the spacing between the first connection structures (11); The first connection structure (11) is connected to the corresponding second connection structure (31) via a fan-out line (40).

2. The chip transfer board according to claim 1, characterized in that: The first connection structure (11) of the first part is connected to the corresponding second connection structure (31) through a first fan-out line (41); The first connection structure (11) of the second part is connected to the corresponding second connection structure (31) via a second fan-out line (42); The routing layer corresponding to the first fan-out line (41) is the first conductive layer (10), and the routing layer corresponding to the second fan-out line (42) is the middle conductive layer (20).

3. The chip transfer board according to claim 2, characterized in that: The first fan-out line (41) comprises a first conductive line (411) distributed in the first conductive layer (10) and a first via line (412) arranged along a first via hole (101); the first via hole (101) is a through hole; The second fan-out line (42) comprises a second via line (421) arranged along the second via hole (102), a second conductive line (422) distributed in the intermediate conductive layer (20), and a third via line (423) arranged along the third via hole (103); the second via hole (102) is a via hole that at least passes through the first conductive layer (10) and the intermediate conductive layer (20), and the third via hole (103) is a via hole that at least passes through the intermediate conductive layer (20) and the second conductive layer (30).

4. The chip transfer board according to claim 2, characterized in that: The first connection structure (11) of the third part is connected to the corresponding second connection structure (31) via a third fan-out line (43); the routing layer corresponding to the third fan-out line (43) is the second conductive layer (30).

5. The chip transfer board according to claim 4, characterized in that: The third fan-out line (43) comprises a fourth via line (431) arranged along a fourth via hole (104) and a third conductive line (432) distributed in the second conductive layer (30); the fourth via hole (104) is a through hole.

6. The chip transfer board according to claim 1, characterized in that: The spacing of the second connection structures (31) is not less than the spacing required to achieve n-layer fan-out, where n is the number of layers of the PCB mainboard (3).

7. The chip transfer board according to claim 1, characterized in that: The intermediate conductive layer (20) comprises a signal layer, a power layer and a ground layer.

8. The chip transfer board according to claim 7, characterized in that: The first conductive layer (10) and the second conductive layer (30) are also signal layers, and the multiple signal layers are evenly distributed.

9. A PCB assembly, characterized in that: include: A PCB main board (3) and a chip adapter board (1) as claimed in any one of claims 1 to 8.

10. The PCB assembly according to claim 9, characterized in that: The number of layers of the PCB main board (3) is smaller than the number of layers of the chip adapter board.

11. A vehicle, characterized in that: include: A PCB assembly as claimed in claim 9 or 10.

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