Back contact solar cell, cell module and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system, and the back contact solar cell comprises a silicon substrate which is provided with a back surface and a front surface which are oppositely arranged; the P-type doped polycrystalline silicon layer is positioned in a first region on the back surface of the silicon substrate; the N-type doped polycrystalline silicon layer is positioned in a second region on the back surface of the silicon substrate, and the first region is different from the second region; wherein the thickness of the N-type doped polycrystalline silicon layer is greater than that of the P-type doped polycrystalline silicon layer. According to the back contact solar cell provided by the utility model, the etching difficulty of the P-type doped polycrystalline silicon can be reduced, the patterning process of the P-type doped polycrystalline silicon can be conveniently realized, the boron diffusion treatment process of the P-type doped polycrystalline silicon layer is facilitated, the P-type doped polycrystalline silicon layer with relatively high concentration can be conveniently prepared, and the cell efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cells, in particular to a back-contact solar cell, a battery assembly and a photovoltaic system. Background Art

[0002] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductors to convert sunlight into electrical energy, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cells, also known as interdigitated back contact cells, have positive and negative electrodes designed on the back of the cell, so that the front surface is completely free from the shading of metal grid lines, eliminating the optical loss caused by the shading of metal grid lines. At the same time, the electrode width can be designed to be wider than the current one, reducing the series resistance loss, thereby greatly improving the cell conversion efficiency. In addition, due to the design of no electrode on the front, the product appearance is more beautiful and suitable for a variety of application scenarios.

[0003] In the prior art, a staggered P region and an N region are formed on the back side of a back-contact solar cell. Usually, the thickness of the P-type doped polysilicon layer in the P region is equal to that of the N-type doped polysilicon layer in the N region. Since the back-contact solar cell first prepares the P-type doped polysilicon and then prepares the N-type doped polysilicon layer, if the P-type doped polysilicon layer is thick, it is difficult to etch the P-type doped polysilicon, and it is inconvenient to pattern the P-type doped polysilicon. Moreover, the thick P-type doped polysilicon layer is not conducive to boron diffusion, and boron diffusion is difficult, making it inconvenient to prepare a P-type doped polysilicon layer with a higher concentration. Utility Model Content

[0004] The utility model provides a back contact solar cell, aiming to solve the problem of the back contact solar cell in the prior art that it is inconvenient to pattern P-type doped polysilicon and to prepare a P-type doped polysilicon layer with a higher concentration.

[0005] The utility model is implemented by providing a back contact solar cell, comprising:

[0006] A silicon substrate having a back surface and a front surface arranged opposite to each other;

[0007] A P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate;

[0008] An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region;

[0009] Wherein, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

[0010] Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2 and is not equal to 1.

[0011] Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.

[0012] Preferably, there is a first height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer close to the silicon substrate, and the surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the front side of the silicon substrate than the surface of the N-type doped polysilicon layer close to the silicon substrate.

[0013] Preferably, there is a second height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate, and the surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the front side of the silicon substrate than the surface of the N-type doped polysilicon layer away from the silicon substrate.

[0014] The utility model also provides a battery assembly, comprising the above-mentioned back contact solar cell.

[0015] The utility model also provides a photovoltaic system, comprising the above-mentioned battery assembly.

[0016] The utility model provides a back-contact solar cell. By setting the thickness of the N-type doped polysilicon layer to be greater than the thickness of the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is reduced under the premise that the thickness of the N-type doped polysilicon layer remains unchanged, and the etching difficulty of the P-type doped polysilicon is reduced, thereby reducing the difficulty of the P-type doped polysilicon patterning process, and facilitating the implementation of the P-type doped polysilicon patterning process; moreover, reducing the thickness of the P-type doped polysilicon layer can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process, and is convenient for preparing a P-type doped polysilicon layer with a higher concentration, thereby improving the battery efficiency; moreover, the thickness of the N-type doped polysilicon layer is greater than that of the P-type doped polysilicon layer. The N-type doped polysilicon layer is thicker than the P-type doped polysilicon layer, which can enhance the passivation effect and improve the battery efficiency. In addition, since the back-contact solar cell first prepares P-type doped polysilicon on the entire surface and then prepares the N-type doped polysilicon layer, when preparing the N-type doped polysilicon layer, it is necessary to first etch and remove the P-type doped polysilicon in the N region. The utility model thins the thickness of the P-type doped polysilicon layer, reduces the difficulty of etching the P-type doped polysilicon, facilitates the clean removal of the P-type doped polysilicon in the N region, and facilitates the preparation of the N-type doped polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a back-contact solar cell provided by an embodiment of the utility model;

[0018] Figure 2 A schematic diagram of a partial structure of a back-contact solar cell provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0020] The utility model provides a back-contact solar cell. By setting the thickness of the N-type doped polysilicon layer to be greater than the thickness of the P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is reduced under the premise that the thickness of the N-type doped polysilicon layer remains unchanged, and the etching difficulty of the P-type doped polysilicon is reduced, thereby reducing the difficulty of the P-type doped polysilicon patterning process, and facilitating the implementation of the P-type doped polysilicon patterning process; moreover, reducing the thickness of the P-type doped polysilicon layer can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process, and is convenient for preparing a P-type doped polysilicon layer with a higher concentration, thereby improving the battery efficiency; moreover, the thickness of the N-type doped polysilicon layer is greater than that of the P-type doped polysilicon layer. The N-type doped polysilicon layer is thicker than the P-type doped polysilicon layer, which can enhance the passivation effect and improve the battery efficiency.

[0021] Please refer to Figure 1 , a back contact solar cell provided by an embodiment of the utility model comprises:

[0022] A silicon substrate 1, wherein the silicon substrate 1 has a back surface and a front surface that are arranged opposite to each other;

[0023] A P-type doped polysilicon layer 2, located in a first region on the back side of the silicon substrate 1;

[0024] The N-type doped polysilicon layer 3 is located in a second region on the back side of the silicon substrate 1, and the first region is different from the second region;

[0025] The thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2 .

[0026] A back-contact solar cell provided by an embodiment of the utility model sets the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2. On the premise that the thickness of the N-type doped polysilicon layer 3 remains unchanged and the effect of the N-type doped polysilicon layer 3 is not affected, the thickness d2 of the P-type doped polysilicon layer 2 is reduced, thereby reducing the etching difficulty of the P-type doped polysilicon and the difficulty of the patterning process, thereby facilitating the patterning process of the P-type doped polysilicon. Moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 can reduce the difficulty of boron diffusion, which is beneficial to the boron diffusion process and facilitates the preparation of a P-type doped polysilicon layer 2 with a higher concentration. Moreover, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2. The N-type doped polysilicon is thicker than the P-type doped polysilicon layer 2, thereby enhancing the passivation effect and improving the battery efficiency. Moreover, since the back contact solar cell first prepares the P-type doped polysilicon layer 2 on the entire surface, and then prepares the N-type doped polysilicon layer 3, it is necessary to first etch and remove the P-type doped polysilicon in the N region when preparing the N-type doped polysilicon layer 3. Therefore, in this embodiment, by reducing the thickness of the P-type doped polysilicon layer 2, the etching difficulty of the P-type doped polysilicon 2 is reduced, and it is also convenient to remove the P-type doped polysilicon in the N region, which is convenient for the preparation of the N-type doped polysilicon layer.

[0027] exist Figure 1 In the figure, the back side of the silicon substrate 1 is the lower side, and the front side is the upper side. The dotted line L1 and the dotted line L2 are only used to distinguish the first area from the second area, and do not actually exist in the back contact solar cell. Figure 1 , the area on the left side of the dotted line L1 is the first area, the area on the right side of the dotted line L2 is the second area, and the first area and the second area are different areas. The P-type doped polysilicon layer 2 is located in the first area on the back side of the silicon substrate 1, and the N-type doped polysilicon layer 3 is located in the second area on the back side of the silicon substrate 1; the P-type doped polysilicon layer 2 is located in the area on the left side of the dotted line L1 on the back side of the silicon substrate 1; the N-type doped polysilicon layer 3 is located in the area on the right side of the dotted line L2 on the first side of the silicon substrate 1.

[0028] In the embodiment of the utility model, the silicon substrate 1 can be an N-type silicon substrate or a P-type silicon substrate.

[0029] As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2 and is not equal to 1.

[0030] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2, which can reduce the etching difficulty of the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon layer 2, and facilitate the boron diffusion process, reduce the difficulty of boron diffusion, and facilitate the preparation of a higher concentration of the P-type doped polysilicon layer 2. Moreover, more importantly, it can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, thereby reducing the loss of battery efficiency.

[0031] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 may be:

[0032] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0033] Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 3 is 100nm to 600nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm to 300nm. When d1 and d2 are within the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are easy to achieve good doping effects, both have good passivation effects, and at the same time ensure that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, which is convenient for the patterning process of the P-type doped polysilicon, and is conducive to the boron diffusion process, reducing the difficulty of boron diffusion, and facilitating the preparation of a high-concentration P-type doped polysilicon layer 2.

[0034] For example, the thickness d1 of the N-type doped polysilicon layer 3 may be 100 nm, or 105 nm, or 135 nm, or 145 nm, or 173 nm, or 185 nm, or 200 nm, or 240 nm, or 285 nm, or 300 nm, or 301 nm, or 342 nm, or 367 nm, or 370 nm, or 420 nm, or 456 nm, or 482 nm, or 500 nm, or 550 nm, or 570 nm, or 590 nm, or 600 nm.

[0035] For example, the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm, or 45nm, or 52nm, or 60nm, or 66.7nm, or 73nm, or 81nm, or 90nm, or 92nm, or 100nm, or 112nm, or 133nm, or 144nm, or 175nm, or 190nm, or 211nm, or 243nm, or 270nm, or 282nm, or 296nm, or 300nm.

[0036] As an embodiment of the present invention, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-1.5 and is not equal to 1.

[0037] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 1.5. This can reduce the processing cost of the thickness D1 of the N-type doped polysilicon layer 3 and the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon, and is beneficial to the boron diffusion process and facilitates the preparation of a higher concentration of the P-type doped polysilicon layer 2; and can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, thereby reducing the loss of battery efficiency.

[0038] As an embodiment of the utility model, it also includes:

[0039] A first metal electrode 6, located in a first area on the back side of the silicon substrate 1 and in contact with the P-type doped polysilicon layer 2;

[0040] The second metal electrode 7 is located in the second region on the back side of the silicon substrate 1 and is in contact with the N-type doped polysilicon layer 2 .

[0041] As an embodiment of the present invention, the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 is greater than the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 .

[0042] In this embodiment, the first metal electrode 6 and the second metal electrode 7 can be printed by using pastes with different burn-through capabilities, so as to control the depths of the metal crystals of the metal electrodes entering the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. For example, the burn-through capability of the paste of the first metal electrode 6 is greater than the burn-through capability of the paste of the second metal electrode 7, so that the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

[0043] As an embodiment of the present invention, the first metal electrode 6 and the second metal electrode 7 both include silver, glass frit and organic material, and the content of glass frit in the first metal electrode 6 is greater than that in the second metal electrode 7 .

[0044] In the present embodiment, the first metal electrode 6 and the second metal electrode 7 both include silver, glass frit and organic material components; wherein the glass frit includes at least one of PbO, Bi2O3, ZnO, SiO2 and MgO, and the glass frit content in the first metal electrode 6 is greater than the glass frit content in the second metal electrode 7, so that the slurry burn-through capability of the first metal electrode 6 is greater than the slurry burn-through capability of the second metal electrode 7, thereby making the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 greater than the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

[0045] As an embodiment of the present invention, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 is 1-4 and is not equal to 1.

[0046] In this embodiment, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4. This can reduce the metallization damage of the P-type doped polysilicon layer 2, reduce the square resistance of the P region, and improve the battery efficiency, and can ensure good contact between the metal electrode and the P-type doped polysilicon layer 2.

[0047] For example, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 may be:

[0048] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0049] As an embodiment of the present invention, the ratio of the depth d3 of the metal crystals of the first metal electrode 6 penetrating into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystals of the second metal electrode 7 penetrating into the N-type doped polysilicon layer 3 is 1-2 and is not equal to 1.

[0050] In the present embodiment, the ratio of the depth d4 of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d3 of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2. This can reduce the metallization damage of the P region, reduce the square resistance of the P region, and improve the battery efficiency, and can ensure good contact between the metal electrode and the P-type doped polysilicon layer 2, and it is convenient for the process control of the depth of the metal crystals of the second metal electrode 7 entering the N-type doped polysilicon layer 3 and the depth of the metal crystals of the first metal electrode 6 entering the P-type doped polysilicon layer 2.

[0051] As an embodiment of the present invention, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3 .

[0052] In this embodiment, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3. It can be understood that the average value of all grain sizes of the P-type doped polysilicon layer 2 per unit area is greater than the average value of all grain sizes of the N-type doped polysilicon layer 3 per unit area; that is, within a unit area, the number of doped polysilicon layers in the N-type doped polysilicon layer 3 is greater, and compared with the N-type doped polysilicon layer 3 per unit area, the P-type doped polysilicon layer 2 per unit area has fewer grain boundaries, thereby improving the compactness of the P-type doped polysilicon layer 2, reducing the square resistance of the P-type doped polysilicon layer 2, reducing current loss, and thus improving battery efficiency. Moreover, the P-type doped polysilicon layer 2 has fewer grain boundaries, which can reduce the metallization damage of the P-type doped polysilicon layer 2, which is also conducive to improving battery efficiency.

[0053] In practical applications, during the preparation process of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, intrinsic amorphous silicon may be first deposited, and then doping diffusion may be performed. During the doping diffusion process, high temperature treatment may be performed. By controlling the diffusion temperature and diffusion time of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, the average grain size of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 may be controlled. For example, the doping diffusion temperature of the P-type doped polysilicon layer 2 may be set higher and the diffusion time may be set longer, so that the average grain size of the prepared P-type doped polysilicon layer 2 may be larger than the average grain size of the N-type doped polysilicon layer 3.

[0054] As an embodiment of the present invention, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is 1-4 and is not equal to 1.

[0055] In this embodiment, the ratio of the grain size of the P-type doped polysilicon layer 2 to the grain size of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4, which can ensure that the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 are within a suitable range, which can reduce the square resistance of the P region and improve the battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0056] As an embodiment of the present invention, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is 1-2 and is not equal to 1.

[0057] In the present embodiment, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2, which can further ensure that the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 are within a more optimal range, which can not only reduce the square resistance of the P region and improve the battery efficiency, but also make it easier to implement the preparation process of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0058] As an embodiment of the present invention, the average grain size of the P-type doped polysilicon layer 2 is 50-600nm; the average grain size of the N-type doped polysilicon layer 3 is 10-400nm, which facilitates the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0059] In this embodiment, when the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3, the average grain size of the P-type doped polysilicon layer 2 is 50 to 600 nm; the average grain size of the N-type doped polysilicon layer 3 is 10 to 400 nm. The average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 can be flexibly set according to actual conditions, as long as the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3.

[0060] Among them, the average grain size of the P-type doped polysilicon layer 2 can be 50nm, or 60nm, or 80nm, or 95nm, or 100nm, or 105nm, or 110nm, or 120nm, or 130nm, or 140nm, or 145nm, or 150nm, or 200nm, or 230nm, or 240nm, or 250nm, or 270nm, or 280nm, or 290nm, or 300nm, or 300nm, or 330nm, or 350nm, or 400nm, or 410nm, or 420nm, or 450nm, or 480nm, or 490nm, or 500nm, or 550nm, or 600nm.

[0061] The average grain size of the N-type doped polysilicon layer 3 can be 10nm, or 20nm, or 30nm, or 40nm, or 50nm, or 55nm, or 65nm, or 70nm, or 80nm, or 100nm, or 120nm, or 130nm, or 150nm, or 200nm, or 210nm, or 240nm, or 250nm, or 260nm, or 270nm, or 280nm, or 290nm, or 300nm, or 320nm, or 340nm, or 360nm, or 380nm, or 400nm.

[0062] Please refer to Figure 2 As an embodiment of the utility model, there is a first height difference h1 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1. The surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1.

[0063] In this embodiment, the surface of the silicon substrate 1 close to the P-type doped polysilicon layer 2 and the surface close to the N-type doped polysilicon layer 3 are not on the same plane; the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1, and there is a first height difference h1 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1. The relative position control of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 is more accurate, and the position reference function is more accurate; and before the latter doped polysilicon layer is made, the part to be etched in the first doped polysilicon layer is etched more cleanly, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first region and the second region are etched more cleanly, and the electrical performance is better. Among them, the first height difference h1 can be flexibly set according to actual needs and is not limited here.

[0064] As an embodiment of the present utility model, there is a second height difference h2 between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. The surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1.

[0065] In this embodiment, the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 is farther away from the front of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. There is a second height difference h2 between the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, so that a good isolation effect between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 is achieved, and the electrical isolation effect is good, and the risk of short circuit or leakage is lower. The second height difference h2 can be flexibly set according to actual needs and is not limited here.

[0066] As an embodiment of the present invention, the front side of the silicon substrate 1 has a suede structure (not shown), which can achieve a good light trapping effect and improve the conversion efficiency of the back contact solar cell. In addition, a front passivation anti-reflection film layer can be provided on the front side of the back contact solar cell to further improve the conversion efficiency of the back contact solar cell.

[0067] Please refer again Figure 1 As an embodiment of the utility model, the back-contact solar cell further includes a back passivation film layer 5 located on the surface of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 to further improve the conversion efficiency of the back-contact solar cell.

[0068] As an embodiment of the present invention, the silicon substrate 1 is further provided with a groove between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are physically isolated by the groove, which can further enhance the isolation effect between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, and further reduce the risk of short circuit or leakage. Among them, the width d5 ​​of the groove can be flexibly set according to actual needs and is not limited here.

[0069] The present invention also provides a battery assembly, which includes the back-contact solar cell of the above embodiment. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, they will not be described here.

[0070] The present invention also provides a photovoltaic system, which includes the battery assembly of the above embodiment. It should be noted that the battery assembly has the same or similar beneficial effects as the back contact solar cell, and the relevant parts between the two can be referenced to each other. In order to avoid repetition, it will not be repeated here.

[0071] A back-contact solar cell provided by an embodiment of the utility model sets the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2, thereby reducing the thickness d2 of the P-type doped polysilicon layer 2 compared to the thickness d1 of the N-type doped polysilicon layer 3, thereby reducing the difficulty of etching the P-type doped polysilicon, thereby reducing the difficulty of the patterning process, and facilitating the patterning process of the P-type doped polysilicon; moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 is conducive to reducing the difficulty of boron diffusion, facilitating the boron diffusion process, and facilitating the preparation of a P-type doped polysilicon layer 2 with a higher concentration. Moreover, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2, and the N-type doped polysilicon layer 3 is thicker than the P-type doped polysilicon layer 2, which can enhance the passivation effect and improve the battery efficiency.

[0072] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A back contact solar cell, characterized in that: include: A silicon substrate having a back surface and a front surface arranged opposite to each other; A P-type doped polysilicon layer, located in a first region on the back side of the silicon substrate; An N-type doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; Wherein, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

2. The back contact solar cell according to claim 1, characterized in that: The ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2 and is not equal to 1.

3. The back contact solar cell according to claim 1, characterized in that: The ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1 to 1.5, and is not equal to 1.

4. The back contact solar cell according to claim 1, characterized in that: There is a first height difference between the surface of the P-type doped polysilicon layer close to the silicon substrate and the surface of the N-type doped polysilicon layer close to the silicon substrate, and the surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the front side of the silicon substrate than the surface of the N-type doped polysilicon layer close to the silicon substrate.

5. The back contact solar cell according to claim 1, characterized in that: There is a second height difference between the surface of the P-type doped polysilicon layer close to the silicon substrate and the surface of the N-type doped polysilicon layer far from the silicon substrate, and the surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the front side of the silicon substrate than the surface of the N-type doped polysilicon layer far from the silicon substrate.

6. A battery assembly, characterized in that: Comprising a back-contact solar cell as described in any one of claims 1 to 5.

7. A photovoltaic system, characterized in that: Comprising the battery assembly as claimed in claim 6.

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