Solar cell and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar power generation, and provides a solar cell and a photovoltaic system, the solar cell comprises a silicon substrate, the rear surface of the silicon substrate is provided with a first texture structure, the side surface of the silicon substrate is provided with a second texture structure, and the first texture structure and the second texture structure both present a table-shaped microstructure morphology. The first texture structure comprises a plurality of first micro polygonal table bodies, the second texture structure comprises a plurality of second micro polygonal table bodies, and the size of the first micro polygonal table bodies is smaller than that of the second micro polygonal table bodies. Through the arrangement, the front surface, the back surface and the side surface of the silicon substrate are textured to generate the first texture structure, and then the second texture structure is etched again on the basis of the first texture structure on the side surface of the silicon substrate, so that an emitter layer material and a doped polycrystalline silicon layer material which permeate and extend to the side surface of the silicon substrate are etched away; and short circuit caused by contact of the emitter layer and the doped polycrystalline silicon layer on the back surface on the side surface of the silicon substrate is prevented.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar power generation, and in particular relates to a solar cell and a photovoltaic system. Background Art

[0002] The production and preparation process of solar cells involves a texturing process to create an uneven velvet surface on the surface of the cell. On the one hand, the velvet surface utilizes the light trapping effect to increase the silicon wafer's absorption of sunlight and reduce reflectivity. On the other hand, it increases the surface area of ​​the silicon wafer, thereby increasing the PN junction area, increasing the short-circuit current, and ultimately improving the cell's photoelectric conversion efficiency.

[0003] After the texturing process, the cell needs to further deposit tunneling layers, emitter layers, back surface field layers and other film layers on the front and / or back side of the cell. However, the emitter layer and back surface field layers may come into contact with the side of the cell during deposition, causing a short circuit in the cell. Utility Model Content

[0004] The embodiment of the utility model provides a solar cell, aiming to solve the problem of short circuit risk of existing solar cells.

[0005] The utility model is implemented in this way: a solar cell comprises:

[0006] A silicon substrate, wherein a first texture structure is arranged on a rear surface of the silicon substrate, and a second texture structure is arranged on a side surface of the silicon substrate;

[0007] The first texture structure and the second texture structure both present a terrace-like microstructure morphology. The first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces. The size of the first micro-polygonal terraces is smaller than that of the second micro-polygonal terraces.

[0008] Furthermore, both the first micro-polygonal platform and the second micro-polygonal platform have a top surface, and the size of the first micro-polygonal platform and the size of the second micro-polygonal platform are any one of the length of the corresponding top surface, the width of the top surface, the length of the docking line of the top surface, and the diameter of the top surface.

[0009] Furthermore, the size of the first micro-polygonal mesa is greater than or equal to 4 microns and less than 10 microns.

[0010] Furthermore, the size of the second micro-polygonal stage is greater than or equal to 10 microns and less than or equal to 20 microns.

[0011] Furthermore, the top surface of the first micro-polygonal stage and the top surface of the second micro-polygonal stage are any one of rhombus, square, trapezoid and circle.

[0012] Further, the solar cell further includes a first anti-reflection film, a first passivation film, a first conductive type region, a second conductive type region and a second passivation film;

[0013] The first conductive type region, the first passivation film and the first anti-reflection film are sequentially arranged on the front surface of the silicon substrate, and the second conductive type region and the second passivation film are sequentially arranged on the rear surface of the silicon substrate.

[0014] Furthermore, the solar cell further includes a first tunneling layer, and the first tunneling layer is arranged between the first conductive type region and the silicon substrate.

[0015] Furthermore, the solar cell further includes a second tunneling layer, and the second tunneling layer is arranged between the second conductive type region and the silicon substrate.

[0016] Furthermore, the solar cell further includes a first doping layer, and the first doping layer is arranged between the silicon substrate and the first tunneling layer.

[0017] Furthermore, the solar cell further includes a second doping layer, and the second doping layer is arranged between the silicon substrate and the second tunneling layer.

[0018] Furthermore, the solar cell further includes a first electrode and a second electrode, the first electrode is connected to the first conductive type region, and the second electrode is connected to the second conductive type region.

[0019] In a second aspect, the present application also provides a photovoltaic system, comprising the solar cell as described above.

[0020] The beneficial effect of the present application is that the solar cell of the present application includes a silicon substrate, wherein the rear surface of the silicon substrate is provided with a first texture structure, and the side surface of the silicon substrate is provided with a second texture structure, and both the first texture structure and the second texture structure present a terrace-shaped microstructure morphology, and the first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces, and the size of the first micro-polygonal terraces is smaller than the size of the second micro-polygonal terraces. Through the above arrangement, in the manufacturing process of the solar cell, the front, back and side surfaces of the silicon substrate are firstly textured to generate the first texture structure, and then other film layers are further deposited, such as depositing an emitter layer on the front surface of the silicon substrate, or depositing a tunneling layer and a doped polysilicon layer on the back surface of the silicon substrate, and then etching again on the basis of the first texture structure on the side surface of the silicon substrate to generate a second texture structure, so as to etch away the emitter layer material and the doped polysilicon layer material that have infiltrated to the side surface of the silicon substrate, and prevent the emitter layer and the doped polysilicon layer on the back surface from contacting at the side surface of the silicon substrate and causing a short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of an embodiment of a solar cell provided by the present application;

[0022] Figure 2 It is a schematic structural diagram of another embodiment of a solar cell provided in the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, in which the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the utility model, and cannot be understood as limiting the utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model.

[0024] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present invention.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0026] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0027] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0028] The disclosure below provides many different embodiments or examples for realizing different structures of the utility model. In order to simplify the disclosure of the utility model, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the utility model. In addition, the utility model can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the utility model provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0029] The solar cell of the present application includes a silicon substrate, wherein a first texture structure is provided on the rear surface of the silicon substrate, and a second texture structure is provided on the side of the silicon substrate, wherein both the first texture structure and the second texture structure present a terrace-shaped microstructure morphology, wherein the first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces, and the size of the first micro-polygonal terraces is smaller than the size of the second micro-polygonal terraces. Through the above arrangement, in the manufacturing process of the solar cell, the front, back and side surfaces of the silicon substrate are firstly textured to generate the first texture structure, and then other film layers are further deposited, such as depositing an emitter layer on the front surface of the silicon substrate, or depositing a tunneling layer and a doped polysilicon layer on the back surface of the silicon substrate, and then etching again on the basis of the first texture structure on the side surface of the silicon substrate to generate a second texture structure, so as to etch away the emitter layer material and the doped polysilicon layer material that have infiltrated to the side surface of the silicon substrate, and prevent the emitter layer and the doped polysilicon layer on the back surface from contacting at the side surface of the silicon substrate and causing a short circuit.

[0030] Embodiment 1

[0031] like Figure 1 to Figure 2 As shown, one embodiment of the present application provides a solar cell, comprising:

[0032] A silicon substrate 100, wherein a first texture structure is disposed on a rear surface of the silicon substrate 100, and a second texture structure is disposed on a side surface of the silicon substrate 100;

[0033] The first texture structure and the second texture structure both present a terrace-like microstructure morphology. The first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces. The size of the first micro-polygonal terraces is smaller than that of the second micro-polygonal terraces.

[0034] In implementation, the solar cell provided by the present application is a cell having opposite polarity film layers respectively arranged on the front and back sides of a silicon substrate 100. By way of example, taking a PERC (Passivated Emitter and Rear Cell) cell as an example, the PERC cell includes a front metal electrode, a front anti-reflection film, an emitter region, a silicon substrate 100, a back surface field, a back surface anti-reflection film and a back surface metal electrode, which are sequentially distributed from top to bottom, wherein the emitter region and the back surface field are respectively located on the front and back sides of the silicon substrate 100, the front metal electrode is connected to the emitter region, i.e., the positive electrode, the back metal electrode is connected to the back surface field, i.e., the negative electrode.

[0035] It should be noted that PERC cells may also include other film layer structures, such as a passivation layer, etc., which will not be elaborated here.

[0036] In the conventional solar cell manufacturing process, the back side of the silicon substrate 100 is subjected to a texturing treatment to generate a first texture structure, and then an LPCVD (low pressure chemical vapor deposition) device is used to generate an emitter region and a back surface field on the front and back sides of the silicon substrate 100. Of course, the emitter region and the back surface field may be generated in other ways, not limited to LPCVD equipment, such as using PVD (Physical Vapor Deposition) equipment to generate an emitter region and a back surface field on the front and back sides of the silicon substrate 100, without limitation. The generated emitter region and back surface field may be connected at the side of the silicon substrate 100 and cause a short circuit, wherein the side of the silicon substrate 100 is the surface between the front and back sides of the silicon substrate 100, such as Figure 1 As shown, the front side, back side and side surface of the silicon substrate 100 are 101, 102 and 103 respectively.

[0037] When the back side of the silicon substrate 100 is subjected to texturing to generate the first texture structure, the first texture structure is also generated on the side of the silicon substrate 100. The first texture structure is a table-shaped microstructure morphology, and the first texture structure includes a plurality of first micro-polygonal tables. The polygonal table is a non-pyramid structure, such as a truncated cone, a nearly truncated cone, a tetrahedron, a nearly tetrahedron, a pentahedron, or a nearly pentahedron, etc., without limitation.

[0038] Optionally, the texturing process includes but is not limited to chemical etching, laser etching, mechanical method, plasma etching and the like, without limitation.

[0039] The first texture structure on the back side of the silicon substrate 100 enables the metal paste to be better filled into the above-mentioned microstructure when forming an electrode by screen printing, thereby obtaining a better electrode contact, effectively reducing the battery series resistance, and improving the filling factor.

[0040] After the emitter region and the back surface field are generated, the side of the silicon substrate 100 is etched for the second time, that is, based on the first texture structure on the side of the silicon substrate 100, a second texture structure is etched again to generate a second texture structure, and the second texture structure includes a plurality of second micro-polygonal terraces. The etching method is the same as the method of etching to generate the first texture structure, and will not be repeated here.

[0041] Since the second micro-polygonal terrace is generated by secondary etching based on the first micro-polygonal terrace, that is, further etching is performed on the first micro-polygonal terrace to generate the second micro-polygonal terrace, the size of the second micro-polygonal terrace is larger than that of the first micro-polygonal terrace.

[0042] The polygonal stage has a top surface. For example, the top surface of the first micro-polygonal stage and the top surface of the second micro-polygonal stage may be any one of a rhombus, a square, a trapezoid and a circle.

[0043] The size of the polygonal table can be any one of the length of the top surface, the width of the top surface, the length of the butt joint line of the top surface, and the diameter of the top surface. In some other embodiments, the size of the polygonal table can also be any one of the length, width, diagonal length, or bottom diameter of the bottom of the polygonal table, without limitation.

[0044] Optionally, the size of the first micro-polygonal table is greater than or equal to 4 microns and less than 10 microns, and the size of the second micro-polygonal table is greater than or equal to 10 microns and less than or equal to 20 microns. Exemplarily, taking the first micro-polygonal table as a first triangular pyramid table and the second micro-polygonal table as a second triangular pyramid table, the triangular pyramid table includes a top surface and three side surfaces. The size of the top surface of the first triangular pyramid table is a, and the size of the top surface of the second triangular pyramid table is b, wherein 4 microns ≤ a < 10 microns, 10 microns ≤ b ≤ 20 microns. Exemplarily, taking the side length of the top surface as an example, the side length of the top surface of the first triangular pyramid table can be 4 microns, 5 microns, 6 microns, 7 microns, 8 microns or 9 microns, and the side length of the top surface of the second triangular pyramid table can be 10 microns, 12 microns, 13 microns, 15 microns, 19 microns or 20 microns, etc., without limitation.

[0045] In some embodiments, the size of the polygonal platform may also be the vertical distance from the top surface to the bottom of the polygonal platform, that is, the size of the polygonal platform refers to the height of the polygonal platform, which will not be elaborated.

[0046] It can be understood that due to the anisotropy of the crystal orientation of the back silicon crystal, the number of micro-polygonal terraces formed on the back side cannot be exhausted. The size of the micro-polygonal terrace referred to in this application can be the average value of the size data of the top surface of the micro-polygonal terrace randomly selected in a specific area, which is used to characterize the texture characteristics of the micro-polygonal terrace.

[0047] The solar cell of the present application includes a silicon substrate 100, wherein a first texture structure is provided on the rear surface of the silicon substrate 100, and a second texture structure is provided on the side of the silicon substrate 100, wherein both the first texture structure and the second texture structure present a terrace-shaped microstructure morphology, wherein the first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces, and the size of the first micro-polygonal terraces is smaller than the size of the second micro-polygonal terraces. Through the above arrangement, in the manufacturing process of the solar cell, the front, back and side surfaces of the silicon substrate 100 are firstly textured to generate the first texture structure, and then other film layers are further deposited, such as depositing an emitter layer on the front surface of the silicon substrate 100, or depositing a tunneling layer and a doped polysilicon layer on the back surface of the silicon substrate 100, and then etching again on the basis of the first texture structure on the side surface of the silicon substrate 100 to generate a second texture structure, so as to etch away the emitter layer material and the doped polysilicon layer material that have infiltrated to the side surface of the silicon substrate 100, and prevent the emitter layer and the doped polysilicon layer on the back surface from contacting on the side surface of the silicon substrate 100 and causing a short circuit.

[0048] In some optional embodiments, the solar cell further includes a first anti-reflection film 200, a first passivation film 300, a first conductive type region 400, a second conductive type region 500, and a second passivation film 600;

[0049] The first conductive type region 400 , the first passivation film 300 and the first anti-reflection film 200 are sequentially disposed on the front surface of the silicon substrate 100 , and the second conductive type region 500 and the second passivation film 600 are sequentially disposed on the rear surface of the silicon substrate 100 .

[0050] During implementation, the front surface and the rear surface of the silicon substrate 100 are the front side and the back side of the silicon substrate 100, respectively. By way of example, taking the front side of the silicon substrate 100 facing upward as an example, on the front side of the silicon substrate 100, the first conductive type region 400, the first passivation film 300 and the first anti-reflection film 200 are sequentially arranged from bottom to top, and on the back side of the silicon substrate 100, the second conductive type region 500 and the second passivation film 600 are sequentially arranged from top to bottom.

[0051] Optionally, the first conductive type region 400 and the second conductive type region 500 may include an emitter region and a back surface field region, wherein the emitter region refers to the portion that draws electrons out of the solar cell, and the emitter region is usually considered to be the "positive electrode" of the solar cell. Similarly, the back surface field region is generally an aluminum back surface field in a solar cell, and its main functions include reflecting long waves, reducing light transmission, back heavy doping, passivation, increasing minority carrier lifetime, and increasing open circuit voltage, etc. The back surface field region is usually considered to be the "negative electrode" of the solar cell, and will not be elaborated.

[0052] In some embodiments, one of the first conductive type region 400 and the second conductive type region 500 is an emitter region, and the other is a back surface field region. In the embodiments of the present application, terms such as first or second are only used to distinguish elements, and the embodiments of the present application are not limited to this.

[0053] In some possible embodiments, the silicon substrate 100 may include a base region containing a dopant of the first conductivity type at a relatively low doping concentration. The base region may be composed of a crystalline semiconductor containing a dopant of the first conductivity type. For example, the base region may include a single crystal or polycrystalline semiconductor (e.g., single crystal silicon or polycrystalline silicon) containing a dopant of the first conductivity type. Alternatively, the base region may be composed of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically, a semiconductor silicon wafer) containing a dopant of the first conductivity type. Therefore, when the base region is composed of single crystal silicon, the solar cell constitutes a single crystal silicon solar cell. Therefore, the solar cell including a single crystal semiconductor is based on the base region or the silicon substrate 100, which has few defects due to excellent crystallinity and therefore exhibits excellent electrical properties.

[0054] Exemplarily, the first conductive type dopant is an n-type or p-type dopant. For example, the first conductive type dopant may be an n-type impurity such as a Group V element (including phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), etc.). Or the first conductive type dopant may be a p-type impurity such as a Group III element (including boron (B), aluminum (Al), gallium (Ga), indium (In), etc.).

[0055] Similarly, the base region may include n-type impurities as dopants of the first conductivity type, and the emitter region forming a pn junction with the base region is p-type. When light is emitted to the pn junction, electrons generated by the photoelectric effect move toward the back side of the silicon substrate 100 and are collected by the corresponding electrode, and holes move toward the front side of the silicon substrate 100 and are then collected by the corresponding electrode, thereby generating electrical energy. Holes with a low moving speed move toward the front side of the silicon substrate 100, thereby improving the photoelectric conversion efficiency, but the embodiments of the present application are not limited thereto. In other embodiments of the present application, for example, the base region and the back surface field region may be designed as p-type, and the emitter region may be designed as n-type, without limitation.

[0056] In some embodiments, the silicon substrate 100 may include only the base region without the additional doped region. That is, in a conventional solar cell, a doped region having a different conductivity type from the silicon substrate 100 or a doped region having the same conductivity type and a relatively high doping concentration as the silicon substrate 100 is formed on the silicon substrate 100.

[0057] As described above, the silicon substrate 100 is only composed of the base region and does not include the additional doping region. For example, the difference between the lowest doping concentration and the highest doping concentration in the silicon substrate 100 is less than or equal to 10%, such as 9%, 8% or 6%, etc., without limitation.

[0058] The first passivation film 300 and the second passivation film 600 are both passivation films, which are used to improve the photoelectric conversion efficiency and stability of solar cells, reduce surface damage and oxidation reactions of solar cells, and extend the service life of solar cells.

[0059] In some possible embodiments, the passivation film includes titanium dioxide, aluminum oxide, ferric oxide, etc., without limitation. Preferably, the first passivation film 300 and / or the second passivation film 600 may be made of aluminum oxide to ensure light absorption rate.

[0060] The first anti-reflection film 200 is an anti-reflection film. Optionally, the first anti-reflection film 200 may be composed of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, without limitation.

[0061] In some possible embodiments, the solar cell provided in the present application also includes a second anti-reflection film 700, which is arranged on a side of the second passivation film 600 away from the second conductive type region 500, and the second anti-reflection film 700 can be composed of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, without limitation.

[0062] Anti-reflection film, also known as anti-reflection film, is used to reduce or eliminate reflected light from optical surfaces such as lenses, prisms, and plane mirrors, thereby increasing the light transmittance of these components and reducing or eliminating stray light in the system.

[0063] In some embodiments, the solar cell provided in the present application further includes a first tunneling layer 810 , and the first tunneling layer 810 is disposed between the first conductive type region 400 and the silicon substrate 100 .

[0064] In practice, when photons enter a solar cell, they excite electrons on one side and push them toward the tunneling layer. In the tunneling layer, electrons tunnel through the band gap to the other side. These electrons can generate current or voltage, thereby converting light energy into electrical energy. The tunneling effect improves the efficiency of electron transmission by reducing the height of the energy barrier for electrons to cross, thereby improving the efficiency of solar cells. In other words, the role of the tunneling layer is to improve the efficiency of charge transmission, that is, to increase the efficiency of solar cells.

[0065] The first tunneling layer 810 is formed on the front surface of the silicon substrate 100. The first tunneling layer 810 passivates the surface of the silicon substrate 100 having many recombination sites and facilitates the migration of carriers through the tunneling effect.

[0066] Optionally, the first tunneling layer 810 may include a material that provides passivation and tunneling effects, such as oxides, nitrides, semiconductors, and conductive polymers, etc. For example, the first tunneling layer 810 may include silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polysilicon, etc., without limitation.

[0067] In some embodiments, the solar cell provided in the present application further includes a second tunneling layer 820 , which is disposed between the second conductive type region 500 and the silicon substrate 100 . The second tunneling layer 820 may refer to the first tunneling layer 810 , and will not be described in detail.

[0068] In some embodiments, the solar cell provided in the present application further includes a first doping layer, and the first doping layer is disposed between the silicon substrate 100 and the first tunneling layer 810 .

[0069] In practice, the first doping layer refers to a thin layer of dopant (such as boron, phosphorus, etc.) formed on the solar cell by sputtering or chemical deposition, so as to increase the thickness of the effective layer in the subsequent epitaxial growth process to improve the cell efficiency.

[0070] In some embodiments, the solar cell provided in the present application further includes a second doping layer, which is disposed between the silicon substrate 100 and the second tunneling layer 820 . The second doping layer may be doped with the first doping layer mentioned above, which will not be described in detail.

[0071] It should be noted that the first doping layer and the second doping layer have the same doping polarity as the same surface, for example, the first doping layer has the same doping type as the first conductive type region 400, and the second doping layer has the same doping type as the second conductive type region 500, which will not be elaborated.

[0072] In some embodiments, the solar cell provided in the present application further includes a first electrode 910 and a second electrode 920 , the first electrode 910 is connected to the first conductive type region 400 , and the second electrode 920 is connected to the second conductive type region 500 .

[0073] In implementation, the first passivation film 300 and the first anti-reflection film 200 are both provided with openings, and the first electrode 910 is electrically connected to the first conductive type region 400 via the openings formed by the first passivation film 300 and the first anti-reflection film 200, that is, the first electrode 910 is connected to the first conductive type region 400 after passing through the first anti-reflection film 200 and the first passivation film 300. Similarly, the second passivation film 600 and the second anti-reflection film 700 are both provided with openings, and the second electrode 920 is electrically connected to the second conductive type region 500 via the openings formed by the second passivation film 600 and the second anti-reflection film 700, that is, the second electrode 920 is connected to the second conductive type region 500 after passing through the second anti-reflection film 700 and the second passivation film 600. The first electrode 910 and the second electrode 920 can be formed into various shapes using various conductive materials (such as copper or silver, etc.), such as strips, sheets or other shapes, without limitation.

[0074] Embodiment 2

[0075] In some optional embodiments, the present application also provides a photovoltaic system, comprising the solar cell as described above.

[0076] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the structure and implementation principle of the photovoltaic assembly described above can refer to the corresponding structure and implementation principle in the aforementioned embodiment 1, and will not be repeated here.

[0077] The solar cell of the present application includes a silicon substrate 100, wherein a first texture structure is provided on the rear surface of the silicon substrate 100, and a second texture structure is provided on the side of the silicon substrate 100, wherein both the first texture structure and the second texture structure present a terrace-shaped microstructure morphology, wherein the first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces, and the size of the first micro-polygonal terraces is smaller than the size of the second micro-polygonal terraces. Through the above arrangement, in the manufacturing process of the solar cell, the front, back and side surfaces of the silicon substrate 100 are firstly textured to generate the first texture structure, and then other film layers are further deposited, such as depositing an emitter layer on the front surface of the silicon substrate 100, or depositing a tunneling layer and a doped polysilicon layer on the back surface of the silicon substrate 100, and then etching again on the basis of the first texture structure on the side surface of the silicon substrate 100 to generate a second texture structure, so as to etch away the emitter layer material and the doped polysilicon layer material that have infiltrated to the side surface of the silicon substrate 100, and prevent the emitter layer and the doped polysilicon layer on the back surface from contacting on the side surface of the silicon substrate 100 and causing a short circuit.

[0078] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein a first texture structure is disposed on a rear surface of the silicon substrate, and a second texture structure is disposed on a side surface of the silicon substrate; The first texture structure and the second texture structure both present a terrace-shaped microstructure morphology. The first texture structure includes a plurality of first micro-polygonal terraces, and the second texture structure includes a plurality of second micro-polygonal terraces. The size of the first micro-polygonal terraces is smaller than that of the second micro-polygonal terraces.

2. The solar cell according to claim 1, wherein: The first micro-polygonal platform and the second micro-polygonal platform both have a top surface, and the size of the first micro-polygonal platform and the size of the second micro-polygonal platform are any one of the corresponding length of the top surface, the width of the top surface, the length of the docking line of the top surface, and the diameter of the top surface.

3. The solar cell according to any one of claims 1 to 2, characterized in that The size of the first micro-polygonal platform is greater than or equal to 4 microns and less than 10 microns.

4. The solar cell according to claim 3, characterized in that The size of the second micro-polygonal stage is greater than or equal to 10 microns and less than or equal to 20 microns.

5. The solar cell according to claim 1, wherein: The top surface of the first micro-polygonal stage and the top surface of the second micro-polygonal stage are any one of rhombus, square, trapezoid and circle.

6. The solar cell according to claim 1, wherein: The solar cell further includes a first anti-reflection film, a first passivation film, a first conductive type region, a second conductive type region, and a second passivation film; The first conductive type region, the first passivation film and the first anti-reflection film are sequentially arranged on the front surface of the silicon substrate, and the second conductive type region and the second passivation film are sequentially arranged on the rear surface of the silicon substrate.

7. The solar cell according to claim 6, characterized in that The solar cell further includes a first tunneling layer disposed between the first conductive type region and the silicon substrate.

8. The solar cell according to claim 6, wherein: The solar cell further includes a second tunneling layer disposed between the second conductive type region and the silicon substrate.

9. The solar cell according to claim 7, wherein: The solar cell further includes a first doping layer disposed between the silicon substrate and the first tunneling layer.

10. The solar cell according to claim 8, characterized in that The solar cell further includes a second doping layer, and the second doping layer is disposed between the silicon substrate and the second tunneling layer.

11. The solar cell according to any one of claims 6 to 10, characterized in that The solar cell further includes a first electrode and a second electrode, the first electrode being connected to the first conductive type region, and the second electrode being connected to the second conductive type region.

12. A photovoltaic system, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 11.

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