Display panel and display device

Abstract

A display panel and a display device relate to the technical field of display. The display panel comprises a display area and a non-display area surrounding the display area, and the display panel comprises a first substrate, a second substrate and a third substrate, the conducting layers are sequentially arranged on one side of the first substrate in a stacked mode in the normal direction of the first substrate; and the dimming structure is arranged on one side, deviating from the first substrate, of the at least one conductive layer, and the dimming structure is used for transmitting linearly polarized light with the polarization direction being the first direction.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The current metaverse technology promotes the rapid development of virtual reality (VR), augmented reality (AR) and mixed reality (MR) display technology. AR, VR and MR technologies require display panels to have ultra-high resolution, ultra-high refresh rate, ultra-fast response and other characteristics. Utility Model Content

[0003] The present disclosure provides a display panel, comprising a display area and a non-display area surrounding the display area, the display panel comprising:

[0004] a first substrate base plate;

[0005] A plurality of conductive layers are sequentially stacked on one side of the first substrate along a normal direction of the first substrate; and

[0006] The dimming structure is arranged on a side of at least one of the conductive layers away from the first substrate, and the dimming structure is used for transmitting linearly polarized light with a polarization direction in a first direction.

[0007] In some embodiments, the display area includes a plurality of sub-pixels, and the sub-pixels include an opening area, and the opening area is used to transmit light;

[0008] The orthographic projection of the dimming structure on the first substrate partially covers the display area, and the orthographic projection of the opening area of ​​the sub-pixel on the first substrate is at least partially located outside the orthographic projection range of the dimming structure on the first substrate.

[0009] In some embodiments, the dimming structure includes at least one dimming pattern, and an orthographic projection contour line of the dimming pattern on the first substrate is parallel or perpendicular to the first direction.

[0010] In some embodiments, the orthographic projection of the dimming structure on the first base substrate entirely covers the display area.

[0011] In some embodiments, the display panel includes an array substrate, an opposing substrate, and a liquid crystal layer located between the array substrate and the opposing substrate, the first base substrate and the plurality of conductive layers are both located on the array substrate, and the opposing substrate includes a second base substrate;

[0012] The dimming structure includes at least one of the following:

[0013] A first dimming structure, disposed on the array substrate and located between one or more of the conductive layers and the liquid crystal layer; and

[0014] The second dimming structure is arranged on the opposite substrate and located between the second base substrate and the liquid crystal layer.

[0015] In some embodiments, the conductive layer includes scan lines and data lines arranged in different layers, and the first dimming structure is located on a side of the scan lines and the data lines away from the first substrate;

[0016] The orthographic projection of the first dimming structure on the first substrate covers the orthographic projection of the scan line and the orthographic projection of the data line on the first substrate.

[0017] In some embodiments, the conductive layer includes a first conductive pattern and a second conductive pattern disposed in different layers, and the first conductive pattern is connected to the second conductive pattern through a first via;

[0018] The first dimming structure is disposed on a side of the first conductive pattern and the second conductive pattern away from the first base substrate, and an orthographic projection of the first dimming structure on the first base substrate covers an orthographic projection of the first via hole on the first base substrate.

[0019] In some embodiments, the plurality of conductive layers further include a third conductive pattern, along the normal direction of the first substrate, the second conductive pattern is located between the first conductive pattern and the third conductive pattern, and the second conductive pattern is connected to the third conductive pattern through a second via;

[0020] The first dimming structure is disposed on a side of the third conductive pattern away from the first substrate, and an orthographic projection of the first dimming structure on the first substrate also covers an orthographic projection of the second via hole on the first substrate.

[0021] In some embodiments, the counter substrate further comprises:

[0022] A spacer column is provided on a side of the second dimming structure away from the second base substrate, and an orthographic projection of the second dimming structure on the second base substrate covers an orthographic projection of the spacer column on the second base substrate.

[0023] In some embodiments, the display area includes a plurality of sub-pixels, and the sub-pixels include an opening area, and the opening area is used to transmit light;

[0024] The counter substrate further comprises: a shading matrix, which is arranged on a side of the second dimming structure away from the second base substrate, wherein the orthographic projection of the shading matrix on the second base substrate is arranged around the opening area, and the orthographic projection contour line of the shading matrix on the second base substrate comprises an arc line; and

[0025] The orthographic projection of the second dimming structure on the second substrate covers the arc.

[0026] In some embodiments, the display panel further includes:

[0027] The first polarizer is arranged on a side of the first substrate away from the multiple conductive layers, and is used for transmitting linearly polarized light having a polarization direction in the first direction.

[0028] In some embodiments, the dimming structure includes a plurality of gratings arranged at equal intervals along a second direction, and the second direction is perpendicular to the first direction.

[0029] In some embodiments, the display area includes a plurality of sub-pixels, the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is used to transmit a first color light, and the second sub-pixel is used to transmit a second color light;

[0030] The display panel further includes:

[0031] A filter layer is arranged between the first base substrate and the conductive layer, and the filter layer includes a plurality of filter patterns. The plurality of filter patterns include a first filter pattern. In the orthographic projection on the first base substrate, the first filter pattern overlaps with the opening area of ​​the first sub-pixel and does not overlap with the opening area of ​​the second sub-pixel. The first filter pattern is used to transmit the first color light and reflect the second color light.

[0032] In some embodiments, the plurality of filtering patterns further include:

[0033] A second filter pattern, in the orthographic projection on the first substrate, the second filter pattern overlaps with the opening area of ​​the second sub-pixel and does not overlap with the opening area of ​​the first sub-pixel, and the second filter pattern is used to transmit the second color light and reflect the first color light.

[0034] In some embodiments, the display panel further includes:

[0035] A first flat layer is arranged on the first substrate and the filter layer on a side close to the conductive layer, the orthographic projection of the first flat layer on the first substrate covers the first substrate in its entirety, and a surface of the first flat layer facing away from the first substrate is a plane; or

[0036] The second flat layer fills the gaps between the plurality of filter patterns, and a surface of the second flat layer facing away from the first substrate is substantially flush with a surface of the filter pattern facing away from the first substrate.

[0037] In some embodiments, the conductive layer comprises:

[0038] A semiconductor layer is disposed on a side of the filter layer away from the first substrate, the semiconductor layer comprising transistor active layers located in different sub-pixels; and

[0039] In the orthographic projection on the first substrate, the filter pattern completely covers the transistor active layer located in the same sub-pixel.

[0040] In some embodiments, the first sub-pixel includes a red sub-pixel and a green sub-pixel, the first color light includes red light and green light, the second sub-pixel includes a blue sub-pixel, and the second color light includes blue light.

[0041] In some embodiments, the multiple conductive layers include scan lines and data lines arranged in different layers, the scan lines are located on the side of the filter layer away from the first substrate, and the data lines are located on the side of the filter layer away from or close to the first substrate.

[0042] In some embodiments, the filtering pattern includes high fold layers and low fold layers that are stacked and alternately arranged, and the refractive index of the high fold layer is greater than the refractive index of the low fold layer.

[0043] The present disclosure provides a display device, comprising:

[0044] A display panel as provided in any embodiment; and

[0045] A driving component is connected to the display panel and is used to drive the display panel to emit light.

[0046] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0048] Figure 1 Shows bad pictures of several display panels in the related art;

[0049] Figure 2 A schematic diagram of a planar structure of a display panel provided by the present disclosure is exemplarily shown;

[0050] Figure 3 The structural schematic diagram of the first array substrate provided by the present disclosure is exemplarily shown;

[0051] Figure 4 The structural schematic diagram of the second array substrate provided by the present disclosure is exemplarily shown;

[0052] Figure 5 The structural schematic diagram of the third array substrate provided by the present disclosure is exemplarily shown;

[0053] Figure 6 The structural schematic diagram of the first opposing substrate provided by the present disclosure is exemplarily shown;

[0054] Figure 7 The structural schematic diagram of the second opposing substrate provided by the present disclosure is exemplarily shown;

[0055] Figure 8 A schematic cross-sectional structure diagram of a display panel provided by the present disclosure is exemplarily shown;

[0056] Fig. 9 The structural schematic diagram of the fourth array substrate provided by the present disclosure is exemplarily shown;

[0057] Fig.10 The structural schematic diagram of the fifth array substrate provided by the present disclosure is exemplarily shown;

[0058] Fig.11 The structural schematic diagrams of the sixth and seventh array substrates provided by the present disclosure are exemplarily shown;

[0059] Fig.12 The structural schematic diagram of the eighth array substrate provided by the present disclosure is exemplarily shown;

[0060] Fig.13A schematic diagram of a planar structure of an array substrate is exemplarily shown;

[0061] Fig.14 The structural schematic diagram of the ninth array substrate provided by the present disclosure is exemplarily shown;

[0062] Fig.15 A schematic diagram of a process flow for preparing a filter layer is shown exemplarily. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] AR / VR / MR products require ultra-high pixel density (Pixels Per Inch, PPI) display panels to achieve better display effects. However, ultra-high PPI display panels face great challenges in design and process.

[0065] Because the pixels of ultra-high PPI display panels become smaller, and the shielding structures such as wiring, transistors, and spacer columns within the pixels are limited by the capabilities of equipment and materials and are difficult to shrink in the same proportion, the pixel opening ratio of ultra-high PPI display panels is very small. For example, the pixel opening ratio of a 500PPI display panel is 50% to 65%, and the transmittance is about 4%. The pixel size of a 1200PPI display panel is 3 to 20 microns, the pixel opening ratio can only be 20%, and the transmittance is only about 1.5%. It can be seen that the transmittance of ultra-high PPI display panels is low.

[0066] In order to increase the pixel aperture ratio, the main solution adopted by related technologies is to reduce the trace width and via size, etc. However, this brings a series of technical problems, such as graphic distortion, diffraction light leakage and other problems.

[0067] Reference Figure 1 , Figure a shows the design pattern of the data line, and Figure b shows the actual preparation pattern of the data line. Figure 1 From a and b in FIG. 1 , it can be found that the data line actually prepared has serious graphic distortion problem.

[0068] Reference Figure 1Figures c to f show the diffraction light leakage phenomenon. According to the principle of diffraction optics, when the size of the shielding structure (such as wiring, vias, and spacers) is close to the wavelength of light, diffraction is obvious. Diffraction causes the light to deflect, generating light with disordered vibration directions. The deflected light will form very obvious light leakage when passing through the liquid crystal, which will lead to a decrease in contrast.

[0069] In order to improve the contrast, the related technology reduces diffraction light leakage by setting a shielding layer. However, the setting of the shielding layer further reduces the pixel aperture ratio and transmittance.

[0070] In the present disclosure, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain terminal, a drain region, or a drain) and a source (source terminal, a source region, or a source), and current can flow through the drain, the channel region, and the source. In the present disclosure, a channel region refers to a region where current mainly flows.

[0071] In the present disclosure, the transistor may be a thin film transistor or a field effect transistor, etc. The present disclosure is described by taking a thin film transistor as an example.

[0072] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0073] In the related art, the pixel circuit of the liquid crystal display panel (LCD) includes one or two transistors, which is relatively simple, so it can achieve ultra-high pixel density (Pixels Per Inch, PPI), that is, the number of pixels per inch. The liquid crystal display panel has a variety of display modes, such as ADS (Advanced Super Dimension Switch, advanced super-dimensional electric field conversion type) mode, TN (twisted nematic, twisted nematic) mode and VA (Vertical Alignment, vertical alignment) mode. In the ADS mode, the pixel electrode and the common electrode are both located on one side of the liquid crystal layer. In the TN mode and the VA mode, the pixel electrode and the common electrode are respectively arranged on the opposite sides of the liquid crystal layer, the pixel electrode is located on one side of the array substrate, and the common electrode is located on the opposite side of the substrate. The working principle of the ADS mode is that the liquid crystal molecules are in a plane parallel to the substrate. When there is no voltage, the light passes through the lower polarizer to form a linear polarization parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. After voltage is applied, a lateral electric field is formed on the left and right sides of the liquid crystal, and the liquid crystal molecules are arranged along the direction of the electric field. After the light passes through the lower polarizer and the liquid crystal layer, it is in an elliptically polarized state and can be emitted through the upper polarizer. The working principle of the TN mode is that in the no-voltage state, the liquid crystal molecules are twisted and aligned at 90° under the action of the alignment film, and the light passes through the lower polarizer and the liquid crystal molecules and then is emitted from the upper polarizer. When voltage is applied, except for the liquid crystals near the alignment films on the upper and lower sides, most of the other liquid crystal molecules are arranged vertically, and the light passing through the lower polarizer passes through the liquid crystal layer without deflection. Since it is parallel to the polarization axis of the upper polarizer, the light is absorbed and cannot be emitted. The working principle of the VA mode is that the liquid crystal molecules are arranged vertically to the substrate substrate. When there is no voltage, the light passes through the lower polarizer to form a linear polarization parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. After voltage is applied, the liquid crystal molecules are deflected along the direction of the electric field, and the light passes through the lower polarizer and the liquid crystal layer. It is in an elliptically polarized state and can be emitted through the upper polarizer.

[0074] The structure of the display panel is introduced below using the ADS mode as an example.

[0075] In order to solve the diffraction light leakage problem, the present disclosure provides a display panel such as Figure 2 As shown, the display panel includes a display area AA and a non-display area NA surrounding the display area AA.

[0076] The display area AA includes a plurality of sub-pixels PX, and the sub-pixel PX includes an opening area TA and a non-opening area NTA. The opening area TA is used to transmit light, and the non-opening area NTA cannot transmit light. Light-proof shielding structures such as thin film transistors, vias, wiring, and spacer columns PS can be arranged in the non-opening area NTA. The ratio of the area of ​​the opening area TA to the area of ​​the sub-pixel PX is the aperture ratio, and the area of ​​the sub-pixel PX is the sum of the area of ​​the opening area TA and the area of ​​the non-opening area NTA.

[0077] For example, a plurality of sub-pixels PX are arranged in an array along the row direction and the column direction, and two adjacent rows of sub-pixels PX may be aligned (eg Figure 2 ), or they can be arranged in a staggered manner (as shown in a Figure 2 As shown in b in the figure, the staggered arrangement is conducive to achieving ultra-high PPI, but since the data line DL is a bent structure, it is more prone to graphic distortion and diffraction light leakage problems.

[0078] like Figure 3 As shown, the display panel includes: a first base substrate 31; a plurality of conductive layers 32, which are stacked in sequence on one side of the first base substrate 31 along the normal direction of the first base substrate 31; and a dimming structure 33, which is arranged on a side of at least one conductive layer 32 away from the first base substrate 31, and the dimming structure 33 is used to transmit linearly polarized light with a polarization direction of the first direction f1.

[0079] By setting the dimming structure 33 inside the display panel, among the light incident on the dimming structure 33, only the linear polarized light with the polarization direction being the first direction f1 can be transmitted, and other polarized light cannot be transmitted. Therefore, the dimming structure 33 can shield the stray polarized light generated by diffraction, thereby reducing diffraction light leakage and improving contrast. In addition, by setting the dimming structure 33 to reduce or eliminate diffraction light leakage, the size of the shielding layer used to shield the diffraction light leakage can be reduced, which is beneficial to improving the pixel aperture ratio and transmittance of the display panel and is beneficial to realizing ultra-high PPI technology.

[0080] For example, Figure 3 As shown, the conductive layer 32 may include at least one of the following: a semiconductor layer 35, a first conductive layer 321, a second conductive layer 322, a pixel electrode EP layer, and a common electrode EC layer. The semiconductor layer 35 includes an active layer ACT of a thin film transistor, the first conductive layer 321 includes a scan line GL, the second conductive layer 322 includes a data line DL, the pixel electrode EP layer includes a plurality of pixel electrodes EP located in different sub-pixels PX, the common electrode EC layer includes a common electrode EC, and the common electrodes EC of the plurality of sub-pixels PX are interconnected.

[0081] For example, Figure 3As shown, the display panel may further include: a first polarizer POL1, which is disposed on a side of the first base substrate 31 away from the plurality of conductive layers 32, and the first polarizer POL1 is used for transmitting linearly polarized light having a polarization direction in a first direction f1.

[0082] In a specific implementation, the light incident on the first polarizer POL1 is, for example, natural light with a random vibration direction, wherein linearly polarized light with a polarization direction of the first direction f1 passes through the first polarizer POL1, and the linearly polarized light may undergo diffraction and depolarization in the process of passing through the first base substrate 31 and the conductive layer 32. The depolarized light is filtered by the dimming structure 33 and becomes linearly polarized light with a polarization direction of the first direction f1 again.

[0083] For example, Figures 3 to 7 As shown in any one of the figures, the dimming structure 33 includes a plurality of grid lines SL arranged at equal intervals along a second direction f2, and the second direction f2 is perpendicular to the first direction f1.

[0084] In this example, the dimming structure 33 is a wire grid structure. Of course, the dimming structure 33 can also be a coatable polarizer, etc., any structure that can transmit linear polarized light with a polarization direction of the first direction f1 and block the transmission of other polarized light.

[0085] In some embodiments, Figure 3 As shown, the orthographic projection of the dimming structure 33 on the first base substrate 31 covers the entire display area AA.

[0086] In this embodiment, if Figure 3 As shown, the orthographic projection of the dimming structure 33 on the first base substrate 31 covers the opening area TA and the non-opening area NTA of the sub-pixel PX. In this embodiment, by setting the dimming structure 33 on the entire surface of the display area AA, the diffraction leakage light at each position in the display area AA can be fully shielded, which can further improve the contrast of the display panel.

[0087] In other embodiments, Figures 4 to 7 As shown in any one of the figures, the orthographic projection of the dimming structure 33 on the first base substrate 31 partially covers the display area AA, and the orthographic projection of the opening area TA of the sub-pixel PX on the first base substrate 31 is at least partially located outside the orthographic projection range of the dimming structure 33 on the first base substrate 31.

[0088] In this embodiment, if Figures 4 to 7As shown in any one of the figures, the orthographic projection of the dimming structure 33 on the first substrate 31 covers at least a portion of the non-opening area NTA of the sub-pixel PX, and may also cover a portion of the opening area TA of the sub-pixel PX or not cover the opening area TA of the sub-pixel PX. In this way, the dimming structure 33 is only arranged in the area where diffraction light leakage may occur in the display area AA, which can not only effectively shield the diffraction light leakage and improve the contrast, but also improve the transmittance of the opening area TA.

[0089] For example, Figures 4 to 7 As shown in any one of the figures, the dimming structure 33 includes a dimming pattern PT (such as Figure 4 ) or a plurality of dimming patterns PT separated from each other (such as Figures 5 to 7 any one shown).

[0090] The inventors have discovered that when the angle between the orthographic projection contour line of the dimming pattern PT on the first base substrate 31 and the first direction f1 is not 0° or 90°, the diffraction light transmission phenomenon is more serious.

[0091] In order to further improve the diffraction light leakage phenomenon, illustratively, as Figures 4 to 7 As shown in any one of the above, the orthographic projection contour line of the dimming pattern PT on the first base substrate 31 is parallel or perpendicular to the first direction f1.

[0092] like Figure 4 As shown, the contour line L1 is parallel to the first direction f1, and the contour line L2 is perpendicular to the first direction f1.

[0093] For example, Figures 5 to 7 As shown, the orthographic projection shape of the dimming pattern PT on the first base substrate 31 is a rectangle, and the sides of the rectangle are parallel or perpendicular to the first direction f1.

[0094] Exemplarily, the dimming structure 33 may be made of metal materials such as aluminum and molybdenum, or transparent conductive materials such as metal oxides such as ITO, IZO, IGZO, IGO, and ZTO. Transparent conductive materials have a higher transmittance to visible light than metal materials.

[0095] For example, Figure 8 As shown, the display panel includes an array substrate 81, an opposing substrate 82, and a liquid crystal layer 83 located between the array substrate 81 and the opposing substrate 82. The first base substrate 31 and multiple conductive layers 32 are all located on the array substrate 81, and the opposing substrate 82 includes a second base substrate 61.

[0096] The display panel provided in this example is a liquid crystal display panel, which is conducive to achieving ultra-high PPI (such as 2000+PPI) and high resolution (such as 4K), improving the immersiveness of AR / VR display, and reducing the impact of the screen door effect. The field of view angle can reach 100°, and the pixel per degree (PPD) exceeds 40.

[0097] Exemplarily, the display panel may include a dimming structure 33. The dimming structure 33 may be located on the array substrate 81 (eg Figures 3 to 5 as shown) or on the opposing substrate 82 (as shown Figure 6 and Figure 7 shown).

[0098] For example, Figures 3 to 5 As shown in any one of the figures, the dimming structure 33 includes: a first dimming structure 331 disposed on the array substrate 81 . The first dimming structure 331 is located between one or more conductive layers 32 and the liquid crystal layer 83 .

[0099] By providing the first dimming structure 331 in the array substrate 81 , it is helpful to prevent cross-color interference between sub-pixels PX of different colors, thereby further improving the display effect.

[0100] For example, Figure 6 or Figure 7 As shown, the dimming structure 33 includes: a second dimming structure 332 disposed on the opposing substrate 82 and located between the second base substrate 61 and the liquid crystal layer 83 .

[0101] By providing the second dimming structure 332 in the opposing substrate 82 , all diffraction leakage light generated between the first dimming structure 331 and the first base substrate 31 can be shielded, which is beneficial to improving the contrast.

[0102] Exemplarily, the display panel may further include a plurality of dimming structures 33. Figure 8 As shown, the dimming structure 33 includes: a first dimming structure 331, arranged on the array substrate 81, located between the plurality of conductive layers 32 and the liquid crystal layer 83; and a second dimming structure 332, arranged on the opposing substrate 82, located between the second base substrate 61 and the liquid crystal layer 83.

[0103] In order to further shield the diffraction leakage light, illustratively, as Figures 3 to 5 As shown, the first dimming structure 331 can be arranged close to the liquid crystal layer 83 in the array substrate 81, that is, all the conductive layers 32 in the array substrate 81 are located between the first dimming structure 331 and the first base substrate 31. In this way, the first dimming structure 331 can shield the diffraction leakage light generated by all film layers between the first base substrate 31 and the first dimming structure 331.

[0104] For example, Figure 3 As shown, the array substrate 81 may further include a first polarizing insulating layer 34 , which is disposed on a side of the first dimming structure 331 away from the first base substrate 31 to protect the first dimming structure 331 , thereby improving the reliability of the display panel.

[0105] like Figure 4 As shown, the conductive layer 32 includes a scanning line GL and a data line DL arranged in different layers, and the first dimming structure 331 is located on a side of the scanning line GL and the data line DL away from the first substrate 31 .

[0106] For example, Figure 4 As shown, the orthographic projection of the first dimming structure 331 on the first substrate 31 covers the orthographic projection of the scan line GL and the data line DL on the first substrate 31. In this way, the first dimming structure 331 can shield the diffraction leakage light generated by the scan line GL and the data line DL.

[0107] Exemplarily, the thickness of the scan line GL and the data line DL is greater than or equal to 300 angstroms.

[0108] Illustratively, in the orthographic projection on the first substrate 31 , the edge of the first dimming structure 331 extends outward by a first distance relative to the edges of the scan line GL and the data line DL. The first distance is, for example, greater than or equal to 0 micrometers and less than or equal to 1 micrometer or 1.5 micrometers.

[0109] Exemplarily, in the width direction of the data line DL (perpendicular to the extension direction of the data line DL), the line width of the data line DL is 2.5 microns, and the pattern width of the first dimming structure 331 overlapping the data line DL can be greater than or equal to 2.5 microns and less than or equal to 5.5 microns, for example 3.5 microns.

[0110] For example, in the orthographic projection on the first substrate 31, the edge of the first dimming structure 331 extends 0 micrometers relative to the edge of the scan line GL and the data line DL, that is, the edge of the first dimming structure 331 is flush with the edge of the scan line GL and the data line DL. This can further improve the pixel aperture ratio and transmittance.

[0111] like Figure 5 As shown, the conductive layer 32 includes a first conductive pattern 51 and a second conductive pattern 52 arranged in different layers. The first conductive pattern 51 and the second conductive pattern 52 are connected through a first via H1. The first dimming structure 331 is arranged on a side of the first conductive pattern 51 and the second conductive pattern 52 away from the first substrate 31.

[0112] For example, Figure 5As shown, the orthographic projection of the first dimming structure 331 on the first base substrate 31 covers the orthographic projection of the first via hole H1 on the first base substrate 31. In this way, the first dimming structure 331 can shield the diffraction leakage light generated by the first via hole H1.

[0113] Illustratively, in the orthographic projection on the first base substrate 31 , the edge of the first dimming structure 331 extends outward by a first distance relative to the edge of the first via H1 , and the first distance is, for example, greater than or equal to 0 micrometers and less than or equal to 1 micrometer or 1.5 micrometers.

[0114] For example, in the orthographic projection on the first base substrate 31, the edge of the first dimming structure 331 is extended by 0 micrometers relative to the edge of the first via H1, that is, the edge of the first dimming structure 331 is flush with the edge of the first via H1. This can further improve the pixel aperture ratio and transmittance.

[0115] like Figure 5 As shown, the multiple conductive layers 32 also include a third conductive pattern 53. Along the normal direction of the first substrate 31, the second conductive pattern 52 is located between the first conductive pattern 51 and the third conductive pattern 53. The second conductive pattern 52 and the third conductive pattern 53 are connected through a second via H2. The first dimming structure 331 is arranged on the side of the third conductive pattern 53 away from the first substrate 31.

[0116] For example, Figure 5 As shown, the orthographic projection of the first dimming structure 331 on the first base substrate 31 also covers the orthographic projection of the second via hole H2 on the first base substrate 31. In this way, the first dimming structure 331 can shield the diffraction leakage light generated by the second via hole H2.

[0117] Illustratively, in the orthographic projection on the first base substrate 31 , the edge of the first dimming structure 331 extends outward by a first distance relative to the edge of the second via H2 , and the first distance is, for example, greater than or equal to 0 micrometers and less than or equal to 1 micrometer or 1.5 micrometers.

[0118] For example, in the orthographic projection on the first base substrate 31, the edge of the first dimming structure 331 is extended by 0 micrometers relative to the edge of the second via H2, that is, the edge of the first dimming structure 331 is flush with the edge of the second via H2. This can further improve the pixel aperture ratio and transmittance.

[0119] Exemplarily, the first conductive pattern 51 may include at least one of conductive materials such as metal, metal oxide and semiconductor, and may be disposed in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0120] Exemplarily, the second conductive pattern 52 may include at least one of conductive materials such as metal, metal oxide and semiconductor, and may be disposed in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0121] Exemplarily, the third conductive pattern 53 may include at least one of conductive materials such as metal, metal oxide and semiconductor, and may be disposed in the same layer as the active layer ACT of the thin film transistor, the scan line GL, the data line DL, the pixel electrode EP or the common electrode EC.

[0122] For example, Figure 5 As shown, the first conductive pattern 51 is the active layer ACT of the thin film transistor, and correspondingly, the second conductive pattern 52 is the transfer electrode EZ, and the third conductive pattern 53 is the pixel electrode EP.

[0123] Exemplarily, the transfer electrode EZ may be made of a transparent conductive material, and may be located between the data line DL and the pixel electrode EP in a direction perpendicular to the first base substrate 31. Of course, the transfer electrode EZ may also be disposed in the same layer as the data line DL.

[0124] like Figure 6 As shown, the counter substrate 82 further includes a spacer column PS, which is disposed on the side of the second dimming structure 332 away from the second base substrate 61. The spacer column PS is disposed to help maintain the liquid crystal thickness between the array substrate 81 and the counter substrate 82 and improve display uniformity.

[0125] For example, Figure 6 As shown, the orthographic projection of the second dimming structure 332 on the second base substrate 61 covers the orthographic projection of the spacer column PS on the second base substrate 61. In this way, the second dimming structure 332 can shield the diffraction leakage light generated by the spacer column PS.

[0126] Illustratively, in the orthographic projection on the second base substrate 61 , the edge of the second dimming structure 332 extends outward by a first distance relative to the edge of the spacer column PS. The first distance is, for example, greater than or equal to 0 micrometers and less than or equal to 1 micrometer or 1.5 micrometers.

[0127] For example, in the orthographic projection on the second base substrate 61, the edge of the second dimming structure 332 is extended by 0 micrometers relative to the edge of the spacer column PS, that is, the edge of the second dimming structure 332 is flush with the edge of the spacer column PS. This can further improve the pixel aperture ratio and transmittance.

[0128] For example, the orthographic projection shape of the spacer column PS on the first base substrate 31 may be a circle (eg Figure 6 As shown in a), rectangle (as shown in Figure 6As shown in b) and interconnected networks, etc., the present disclosure does not limit this.

[0129] For example, the spacer column PS may be made of organic material or metal material.

[0130] like Figure 7 As shown, the counter substrate 82 further includes: a light shielding matrix BM, the second dimming structure 332 is arranged on the side away from the second base substrate 61, the orthographic projection of the light shielding matrix BM on the second base substrate 61 is arranged around the opening area TA, and the orthographic projection contour line of the light shielding matrix BM on the second base substrate 61 includes an arc line hx. The arc line hx is located on the side of the light shielding matrix BM close to the opening area TA.

[0131] For example, Figure 7 As shown, the orthographic projection of the second dimming structure 332 on the second substrate 61 covers the arc hx. In this way, the second dimming structure 332 can shield the diffraction leakage light generated by the arc hx of the light shielding matrix BM.

[0132] Illustratively, in the orthographic projection on the second base substrate 61 , the edge of the second dimming structure 332 extends outward by a first distance relative to the arc line hx, and the first distance is, for example, greater than or equal to 0 micrometers and less than or equal to 1 micrometer or 1.5 micrometers.

[0133] For example, Figure 6 or Figure 7 As shown, the counter substrate 82 may further include: a color filter layer CF and a protective layer OC stacked in sequence between the light shielding matrix BM and the spacer, and the color filter layer CF is arranged close to the light shielding matrix BM. The color filter layer CF, for example, includes a red color filter R located in the red sub-pixel PXR, a green color filter G located in the green sub-pixel PXG, and a blue color filter B located in the blue sub-pixel PXB. The red color filter R is used to transmit red light, the green color filter G is used to transmit green light, and the blue color filter B is used to transmit blue light.

[0134] For example, Figure 6 As shown, the counter substrate 82 may further include: a second polarizing insulating layer 62 disposed between the second dimming structure 332 and the spacer column PS to protect the second dimming structure 332 .

[0135] For example, Figure 8 As shown, the display panel may further include: a second polarizer POL2, which is arranged on a side of the second base substrate 61 away from the first base substrate 31, and the second polarizer POL2 is used for transmitting linearly polarized light with a polarization direction in a second direction f2.

[0136] For example, Figure 4The array substrate 81 shown can be prepared according to the following process flow: a buffer layer buffer → semiconductor layer 35 → first insulating layer 36 → first conductive layer 321 → second insulating layer 37 → second conductive layer 322 → third insulating layer 38 → pixel electrode EP layer → fourth insulating layer 39 → common electrode EC layer → fifth insulating layer 310 → first dimming structure 331 are formed in sequence on the first base substrate 31.

[0137] For example, Figure 7 The counter substrate 82 shown can be prepared according to the following process flow: a second dimming structure 332 → a light shielding matrix BM → a color filter layer CF → a protective layer OC → a spacer column PS are sequentially formed on the second base substrate 61 .

[0138] Exemplarily, the dimming structure 33 may be prepared by the following process: metal layer film formation, photoresist coating, exposure, photoresist stripping, etching, etc.; the dimming structure 33 may also be prepared by nanoimprinting and other patterning processes, which is not limited in the present disclosure.

[0139] For example, Figure 3 As shown, a transparent auxiliary electrode FZ may be formed between the first insulating layer 36 and the first conductive layer 321. In the orthographic projection on the first base substrate 31, the transparent auxiliary electrode FZ has substantially the same shape as the orthographic projection of the scanning line GL. The transparent auxiliary electrode FZ covers the scanning line GL, and the outline of the transparent auxiliary electrode FZ is expanded relative to the outline of the scanning line GL. By providing the transparent auxiliary electrode FZ, the channel size may be increased without increasing the aperture ratio, which is beneficial to improving the pixel aperture ratio.

[0140] The transparent auxiliary electrode FZ may be made of a transparent conductive material.

[0141] In order to further improve the transmittance of the display panel, Fig. 9 As shown, the display area AA includes a plurality of sub-pixels PX, and the plurality of sub-pixels PX include a first sub-pixel PX1 and a second sub-pixel PX2. The first sub-pixel PX1 is used to transmit a first color light, and the second sub-pixel PX2 is used to transmit a second color light.

[0142] The first subpixel PX1 may include one or more of a red subpixel PXR, a green subpixel PXG, and a blue subpixel PXB, and the second subpixel PX2 may include one or more of a red subpixel PXR, a green subpixel PXG, and a blue subpixel PXB.

[0143] For example, Fig. 9As shown, the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light.

[0144] For example, Fig. 9 As shown, the display panel further includes: a filter layer 91 disposed between the first base substrate 31 and the conductive layer 32, the filter layer 91 includes a plurality of filter patterns 91P, and the filter patterns 91P are used to transmit a portion of the incident light and reflect a portion of the incident light.

[0145] For example, Fig. 9 As shown, multiple filter patterns 91P include a first filter pattern 91P1. In the orthographic projection on the first base substrate 31, the first filter pattern 91P1 overlaps with the opening area TA of the first sub-pixel PX1 and does not overlap with the opening area TA of the second sub-pixel PX2. The first filter pattern 91P1 is used to transmit the first color light and reflect the second color light.

[0146] In the case where the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light, as shown in FIG. Fig. 9 As shown, the first filter pattern 91P1 is disposed on the red sub-pixel PXR and the green sub-pixel PXG, transmits red light and green light, and reflects blue light.

[0147] Since the first filter pattern 91P1 located in the first sub-pixel PX1 can reflect the second color light, the thickness of the color filter layer CF disposed in the first sub-pixel PX1 can be reduced, thereby improving the transmittance of the first sub-pixel PX1.

[0148] Exemplarily, the thickness of the first filter pattern 91P1 is 0.58 micrometers. Under the premise of maintaining the same color gamut, the thickness of the color filter layer CF disposed in the first sub-pixel PX1 can be reduced by 1 micrometer, and the transmittance is increased by 16%.

[0149] For example, Fig.10 As shown, the multiple filter patterns 91P also include: a second filter pattern 91P2. In the orthographic projection on the first base substrate 31, the second filter pattern 91P2 overlaps with the opening area TA of the second sub-pixel PX2 and does not overlap with the opening area TA of the first sub-pixel PX1. The second filter pattern 91P2 is used to transmit the second color light and reflect the first color light.

[0150] In the case where the first sub-pixel PX1 includes a red sub-pixel PXR and a green sub-pixel PXG, the first color light includes red light and green light, the second sub-pixel PX2 includes a blue sub-pixel PXB, and the second color light includes blue light, as shown in FIG. Fig.10 As shown, the second filter pattern 91P2 is disposed in the blue sub-pixel PXB, transmits blue light and reflects red light and green light.

[0151] Since the second filter pattern 91P2 located in the second sub-pixel PX2 can reflect the first color light, the thickness of the color filter layer CF disposed in the second sub-pixel PX2 can be reduced, thereby improving the transmittance of the second sub-pixel PX2.

[0152] For example, Fig. 9 As shown, the filter pattern 91P includes high fold layers and low fold layers stacked and alternately arranged, and the refractive index of the high fold layer is greater than the refractive index of the low fold layer.

[0153] Exemplarily, the high fold layer includes one or more dielectric materials such as TiO2, Nb2O5, Y2O3, TaO2, SiN, etc., and the low fold layer includes one or more dielectric materials such as SiO2, MgF2, LiF, etc. The greater the refractive index difference between the high fold layer and the low fold layer, the thinner the thickness of the filter pattern 91P.

[0154] Exemplarily, the high folding layer is made of TiO2, the low folding layer is made of SiO2, and TiO2 and SiO2 are alternately stacked one by one to obtain the first filter pattern 91P1, and the transmittance of the first filter pattern 91P1 to red and green light exceeds 90%, and the reflectivity to blue light exceeds 90%.

[0155] For example, Fig.11 As shown in a, the display panel may also include: a first flat layer PLN1, which is arranged on the first base substrate 31 and the side of the filter layer 91 close to the conductive layer 32, the orthographic projection of the first flat layer PLN1 on the first base substrate 31 covers the entire surface of the first base substrate 31, and the surface of the first flat layer PLN1 facing away from the first base substrate 31 is a plane.

[0156] like Fig.11 As shown in a, the first flat layer PLN1 is not only arranged in the gap between the first filter patterns 91P1, but also arranged on the side of the first filter pattern 91P1 away from the first base substrate 31, that is, the first flat layer PLN1 is arranged in both the first sub-pixel PX1 and the second sub-pixel PX2, and the surface of the first flat layer PLN1 away from the first base substrate 31 is higher than the surface of the filter layer 91 away from the first base substrate 31.

[0157] By setting the first flat layer PLN1 and forming a subsequent film layer on the flattened surface of the first flat layer PLN1, the step difference can be eliminated and the risk of line breakage can be avoided.

[0158] For example, Fig.11 As shown in b, the display panel may further include: a second flat layer PLN2 filling the gaps between the plurality of filter patterns 91P, wherein the surface of the second flat layer PLN2 facing away from the first base substrate 31 is substantially flush with the surface of the filter pattern 91P facing away from the first base substrate 31.

[0159] By setting the second flat layer PLN2, the surface of the second flat layer PLN2 facing away from the first base substrate 31 and the surface of the filter pattern 91P facing away from the first base substrate 31 are located in the same plane, and subsequent film layers are formed on the flattened surface, which can avoid the risk of wire breakage.

[0160] In addition, by setting the surface of the second flat layer PLN2 facing away from the first base substrate 31 to be roughly flush with the surface of the filter pattern 91P facing away from the first base substrate 31, the distance between the filter layer 91 and the color filter layer CF can be reduced, which is beneficial to reducing the risk of cross-color.

[0161] In the case where the filter layer 91 includes only the first filter pattern 91P1 located in the first sub-pixel PX1, as shown in FIG. Fig.11 As shown in b, the orthographic projection of the second flat layer PLN2 on the first base substrate 31 overlaps with the second sub-pixel PX2 and does not overlap with the first sub-pixel PX1, that is, the second flat layer PLN2 is arranged in the gap between the first filter patterns 91P1.

[0162] In order to improve the reliability of the display panel, the temperature resistance of the first flat layer PLN1 or the second flat layer PLN2 is greater than or equal to 350°C.

[0163] In order to improve the transmittance of the display panel, the refractive index of the first flat layer PLN1 or the second flat layer PLN2 is, for example, equivalent to the refractive index of the first base substrate 31. For example, the first base substrate 31 is a glass substrate, and the refractive index of the first flat layer PLN1 or the second flat layer PLN2 is, for example, greater than or equal to 1.4 and less than or equal to 1.5.

[0164] Exemplarily, the transmittance of the first planar layer PLN1 or the second planar layer PLN2 is greater than or equal to 99%.

[0165] Exemplarily, the first planar layer PLN1 or the second planar layer PLN2 uses a high-transmittance high-temperature planar glue.

[0166] For example, Fig. 9As shown, the conductive layer 32 includes: a semiconductor layer 35, which is arranged on a side of the filter layer 91 away from the first substrate 31, and the semiconductor layer 35 includes transistor active layers ACT located in different sub-pixels PX.

[0167] Exemplarily, the transistor active layer ACT includes an oxide semiconductor material, which is beneficial to improving the pixel aperture ratio.

[0168] Exemplarily, the transistor active layer ACT includes a semiconductor material M1OaNb, wherein M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents an oxygen element, and N represents a nitrogen element, that is, the semiconductor material is a metal oxide material or a metal oxynitride material.

[0169] Suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb and Cd-Sn-O. The material of the transistor active layer ACT may be in an amorphous, partially crystalline, single crystal or polycrystalline state, and may also be a single layer or multilayer structure.

[0170] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride or combinations thereof. In one example, the material of the transistor active layer ACT includes indium gallium zinc oxide (IGZO).

[0171] For example, Fig. 9 As shown, in the orthographic projection on the first base substrate 31, the filter pattern 91P completely covers the transistor active layer ACT located in the same sub-pixel PX. In this way, the filter pattern 91P can block part of the light for the active layer ACT, improve the stability of the transistor, and improve the threshold voltage drift caused by light.

[0172] For example, Fig. 9 As shown, in the orthographic projection on the first base substrate 31 , the first filter pattern 91P1 completely covers the transistor active layer ACT located in the first sub-pixel PX1 , thereby preventing the blue light from being refracted into the transistor active layer ACT located in the first sub-pixel PX1 .

[0173] For example, Fig. 9 or Fig.12 As shown, the plurality of conductive layers 32 include scanning lines GL and data lines DL arranged in different layers. The scanning lines GL are located on the side of the filter layer 91 away from the first substrate 31, and the data lines DL are located on the side of the filter layer 91 away from the first substrate 31 (as shown in FIG. Fig. 9 ), or the data line DL is located on the side of the filter layer 91 close to the first substrate 31 (as shown in Fig.12 shown).

[0174] By arranging the data line DL on the side of the filter layer 91 close to the first base substrate 31 , it is helpful to reduce diffraction light leakage.

[0175] In the case where the data line DL is disposed on a side of the filter layer 91 close to the first base substrate 31 , the data line DL may be disposed in the same layer and made of the same material as the alignment mark.

[0176] For example, Fig. 9 As shown, the data line DL may be located on the side of the semiconductor layer 35 away from the first substrate 31. In this case, the active layer ACT is connected to the data line DL in an overlay manner; Fig.12 As shown, the data line DL may also be located on a side of the semiconductor layer 35 close to the first substrate 31 . In this case, the active layer ACT is connected to the data line DL in a bottom-overlapping manner.

[0177] Exemplarily, the data line DL may also be disposed on the surface of the first flat layer PLN1 away from the first base substrate 31 , and the data line DL may also be disposed on the surface of the second flat layer PLN2 and the filter layer 91 away from the first base substrate 31 .

[0178] For example, Fig.13 As shown, the rectangular frame k is the orthographic projection boundary of the filter layer 91 on the first base substrate 31 , and the orthographic projection of the filter pattern 91P on the first base substrate 31 completely covers the orthographic projection of the scan line GL on the first base substrate 31 .

[0179] Since the line width of the data line DL is relatively small (eg, 1.3 microns), in the case where the filter layer 91 has a large step difference away from the surface of the first substrate 31, in order to avoid the data line DL from being broken, for example, Fig.13 As shown in a and b, in the orthographic projection on the first base substrate 31, the boundary of the filter layer 91 along the column direction has no overlap with the data line DL, and the spacing between the boundary of the filter layer 91 along the column direction and the data line DL is greater than or equal to 0.7 microns.

[0180] For example, in the orthographic projection on the first base substrate 31, the boundary of the first filter pattern 91P1 along the column direction may be located on a side of the data line DL close to the second sub-pixel PX2 (eg, Fig.13 ), or the side away from the second sub-pixel PX2 (as shown in a in FIG. Fig.13 (as shown in a in the figure).

[0181] In the case where the surface of the filter layer 91 facing away from the first base substrate 31 is flattened, in the orthographic projection on the first base substrate 31, the boundary of the filter layer 91 along the column direction may overlap with the data line DL (eg Fig.13 c in the figure) or no overlap, Fig.13 In c, the boundary of the filter layer 91 along the column direction is flush with the center line of the data line DL along the column direction.

[0182] Exemplarily, the transistor may adopt a top gate structure, that is, the scan line GL is located on the side of the active layer ACT away from the first substrate 31. Of course, the transistor may also adopt a bottom gate structure, that is, the scan line GL is located on the side of the active layer ACT close to the first substrate 31, which is not limited in the present disclosure.

[0183] Exemplarily, the color filter layer CF may be located on the counter substrate 82 .

[0184] For example, the color filter layer CF may be located on the array substrate 81. Fig.14 As shown, the color filter layer CF may be located between the transistor and the pixel electrode EP and the common electrode EC, which may improve the color cross-talk problem between pixels caused by the alignment deviation between the array substrate 81 and the counter substrate 82 .

[0185] like Fig.14 As shown, the pixel electrode EP is connected to the transistor through a via hole arranged on the color filter layer CF. Since the setting of the filter layer 91 can reduce the thickness of the color filter layer CF, the thinner color filter layer CF thickness can reduce the depth and aperture of the via hole. Therefore, the risk of climbing and breaking and the light leakage problem caused by excessive via holes can be reduced.

[0186] Exemplarily, the thickness of the color filter layer CF is, for example, greater than or equal to 1.5 micrometers and less than or equal to 2 micrometers.

[0187] Reference Fig.15 , Fig.10 The filter layer 91 shown can be prepared according to the following steps:

[0188] Step 1: Form a filter membrane 151 on the first base substrate 31, such as Fig.15 As shown in a in .

[0189] Step 2: Etch the filter film 151 located in the second sub-pixel PX2 to obtain a first filter pattern 91P1 located in the first sub-pixel PX1, as shown in FIG. Fig.15 As shown in b in FIG. 1 , the first filter pattern 91P1 may also be located in the non-display area NA.

[0190] Step 3: forming a filter film 152 on the surface of the first filter pattern 91P1 away from the first base substrate 31, such as Fig.15 As shown in c.

[0191] Step 4: Etch the filter film 152 located at the first sub-pixel PX1 to obtain Fig.15 The array substrate shown in d in FIG. 1 is then subjected to an ashing process to obtain a second filter pattern 91P2 located at the second sub-pixel PX2, as shown in FIG. Fig.15 As shown in e in FIG. 1 , a first filter pattern 91P1 and a second filter pattern 91P2 that are in close contact can be prepared in this way.

[0192] The present disclosure provides a display device, comprising: a display panel as provided in any embodiment; and a driving component connected to the display panel and used to drive the display panel to emit light.

[0193] Those skilled in the art can understand that the display device provided by the present disclosure has the advantages of the display panel of any of the above embodiments.

[0194] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0195] In the present disclosure, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly and specifically defined.

[0196] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0197] In this disclosure, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, product or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, commodity or device comprising the element.

[0198] References in this disclosure to "one embodiment", "some embodiments", "exemplary embodiments", "one or more embodiments", "example", "an example", "some examples", etc. are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0199] In the present disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0200] In this specification, "electrically connected" and "coupled" include the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0201] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0202] The polygon in this specification is not a strict polygon, and can be an approximate triangle, rectangle, trapezoid, pentagon or hexagon, etc. There can be some small deformations caused by tolerances, and there can be chamfers, rounded corners, arc edges and deformations.

[0203] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0204] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0205] The use of "for" or "configured to" in this disclosure is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0206] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0207] As used in the present disclosure, "parallel", "perpendicular", "equal", and "level" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 10° or 5°.

[0208] "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equals is less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein the acceptable deviation range of approximate flush can be, for example, the distance between the two flushes is less than or equal to 5% of either one.

[0209] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0210] The present disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present disclosure, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0211] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a non-display area surrounding the display area, and the display panel comprises: a first substrate base plate; A plurality of conductive layers are sequentially stacked on one side of the first substrate along a normal direction of the first substrate; and The dimming structure is arranged on a side of at least one of the conductive layers away from the first substrate, and the dimming structure is used for transmitting linearly polarized light with a polarization direction in a first direction.

2. The display panel according to claim 1, characterized in that: The display area includes a plurality of sub-pixels, each of which includes an opening area, and the opening area is used to transmit light; The orthographic projection of the dimming structure on the first substrate partially covers the display area, and the orthographic projection of the opening area of ​​the sub-pixel on the first substrate is at least partially located outside the orthographic projection range of the dimming structure on the first substrate.

3. The display panel according to claim 2, characterized in that: The dimming structure includes at least one dimming pattern, and an orthographic projection contour line of the dimming pattern on the first substrate is parallel or perpendicular to the first direction.

4. The display panel according to claim 1, characterized in that: The orthographic projection of the dimming structure on the first substrate covers the entire display area.

5. The display panel according to claim 1, characterized in that: The display panel includes an array substrate, an opposing substrate, and a liquid crystal layer located between the array substrate and the opposing substrate, the first base substrate and the plurality of conductive layers are both located on the array substrate, and the opposing substrate includes a second base substrate; The dimming structure includes at least one of the following: A first dimming structure, disposed on the array substrate and located between one or more of the conductive layers and the liquid crystal layer; as well as The second dimming structure is arranged on the opposite substrate and located between the second base substrate and the liquid crystal layer.

6. The display panel according to claim 5, characterized in that: The conductive layer includes a scan line and a data line arranged in different layers, and the first dimming structure is located on a side of the scan line and the data line away from the first substrate; The orthographic projection of the first dimming structure on the first substrate covers the orthographic projection of the scan line and the orthographic projection of the data line on the first substrate.

7. The display panel according to claim 5, characterized in that: The conductive layer includes a first conductive pattern and a second conductive pattern arranged in different layers, and the first conductive pattern and the second conductive pattern are connected through a first via hole; The first dimming structure is disposed on a side of the first conductive pattern and the second conductive pattern away from the first base substrate, and an orthographic projection of the first dimming structure on the first base substrate covers an orthographic projection of the first via hole on the first base substrate.

8. The display panel according to claim 7, characterized in that: The plurality of conductive layers further include a third conductive pattern, along the normal direction of the first substrate, the second conductive pattern is located between the first conductive pattern and the third conductive pattern, and the second conductive pattern is connected to the third conductive pattern through a second via hole; The first dimming structure is disposed on a side of the third conductive pattern away from the first substrate, and an orthographic projection of the first dimming structure on the first substrate also covers an orthographic projection of the second via hole on the first substrate.

9. The display panel according to claim 5, characterized in that: The counter substrate further comprises: A spacer column is provided on a side of the second dimming structure away from the second base substrate, and an orthographic projection of the second dimming structure on the second base substrate covers an orthographic projection of the spacer column on the second base substrate.

10. The display panel according to claim 5, characterized in that: The display area includes a plurality of sub-pixels, each of which includes an opening area, and the opening area is used to transmit light; The counter substrate further comprises: a shading matrix, which is arranged on a side of the second dimming structure away from the second base substrate, wherein the orthographic projection of the shading matrix on the second base substrate is arranged around the opening area, and the orthographic projection contour line of the shading matrix on the second base substrate comprises an arc line; and The orthographic projection of the second dimming structure on the second substrate covers the arc.

11. The display panel according to claim 1, characterized in that: The display panel further includes: The first polarizer is arranged on a side of the first substrate away from the multiple conductive layers, and is used for transmitting linearly polarized light having a polarization direction in the first direction.

12. The display panel according to claim 1, characterized in that: The dimming structure includes a plurality of grid bars arranged at equal intervals along a second direction, and the second direction is perpendicular to the first direction.

13. The display panel according to any one of claims 1 to 12, characterized in that: The display area includes a plurality of sub-pixels, and the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is used to transmit a first color light, and the second sub-pixel is used to transmit a second color light; The display panel further includes: A filter layer is arranged between the first base substrate and the conductive layer, and the filter layer includes a plurality of filter patterns. The plurality of filter patterns include a first filter pattern. In the orthographic projection on the first base substrate, the first filter pattern overlaps with the opening area of ​​the first sub-pixel and does not overlap with the opening area of ​​the second sub-pixel. The first filter pattern is used to transmit the first color light and reflect the second color light.

14. The display panel according to claim 13, characterized in that: The plurality of filtering patterns further include: A second filter pattern, in the orthographic projection on the first substrate, the second filter pattern overlaps with the opening area of ​​the second sub-pixel and does not overlap with the opening area of ​​the first sub-pixel, and the second filter pattern is used to transmit the second color light and reflect the first color light.

15. The display panel according to claim 13, characterized in that: The display panel further includes: A first flat layer is arranged on the first substrate and the filter layer on a side close to the conductive layer, the orthographic projection of the first flat layer on the first substrate covers the first substrate in its entirety, and a surface of the first flat layer facing away from the first substrate is a plane; or The second flat layer fills the gaps between the plurality of filter patterns, and a surface of the second flat layer facing away from the first substrate is substantially flush with a surface of the filter pattern facing away from the first substrate.

16. The display panel according to claim 13, characterized in that: The conductive layer comprises: A semiconductor layer is disposed on a side of the filter layer away from the first substrate, the semiconductor layer comprising transistor active layers located in different sub-pixels; and In the orthographic projection on the first substrate, the filter pattern completely covers the transistor active layer located in the same sub-pixel.

17. The display panel according to claim 13, characterized in that: The first sub-pixel includes a red sub-pixel and a green sub-pixel, the first color light includes a red light and a green light, the second sub-pixel includes a blue sub-pixel, and the second color light includes a blue light.

18. The display panel according to claim 13, characterized in that: The multiple conductive layers include scan lines and data lines arranged in different layers. The scan lines are located on a side of the filter layer away from the first substrate, and the data lines are located on a side of the filter layer away from or close to the first substrate.

19. The display panel according to claim 13, characterized in that: The filtering pattern includes high fold layers and low fold layers that are stacked and alternately arranged, and the refractive index of the high fold layer is greater than the refractive index of the low fold layer.

20. A display device, characterized in that: include: The display panel according to any one of claims 1 to 19; as well as A driving component is connected to the display panel and is used to drive the display panel to emit light.

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