2.5 D packaging system based on FPGA architecture

Abstract

The utility model relates to a 2.5 D packaging system based on an FPGA (Field Programmable Gate Array) architecture. The packaging structure comprises a packaging substrate; the chip module is used for leading out the chip module through the packaging substrate; the chip module comprises an intermediate substrate and a chip unit group, and the chip unit group comprises a communication interface module, a storage configuration module and a chip selection signal control module; the communication interface module comprises an FPGA chip capable of supporting multiple configuration modes, the chip selection signal control module is connected with the FPGA chip and the storage configuration module in an adaptive mode, and connection between the storage configuration module and the FPGA chip can be configured based on chip selection control over the chip selection signal control module. And enabling the connection state between the storage configuration module and the FPGA chip to be matched with the currently selected configuration mode. According to the utility model, the packaging miniaturization and the packaging density can be improved, and conflicts existing in FPGA configuration data can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to a packaging system, in particular to a 2.5D packaging system based on FPGA architecture. Background Art

[0002] At present, the integration of electronic systems is mainly divided into three levels, namely, on-chip integration, in-package integration, and PCB board-level integration. As the characteristic size of transistors gradually moves towards 1nm, on-chip integration is unsustainable, and Moore's Law has come to an end; the wiring density and assembly density of PCB board-level integration are gradually approaching the limit, and there has been no significant improvement for many years. In addition, affected by the chip package size, the device assembly density on the PCB board is also difficult to continue to increase. Initially, the integration in the package was mostly in the form of single-chip packaging. With the expansion of the scale of integration in the package, the enhancement of functions, and the application of 2.5D and 3D integration technologies, the concept of system-level packaging (SiP) technology emerged and has gradually been widely used.

[0003] SiP modules based on FPGA architecture have broad applications and development prospects in the field of electronic products. At present, most electronic products on the market require high performance, miniaturization, multiple varieties and small batches. Therefore, with the increase in application requirements, SiP modules usually need to integrate multiple chips. In this case, the packaging layout of multiple chips can no longer meet the needs of miniaturization. In addition, for SiP modules using FPGA architecture, there will be data conflicts when configuring data. How to effectively resolve data conflicts is a difficult problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the utility model is to overcome the deficiencies in the prior art and provide a 2.5D packaging system based on FPGA architecture, which can improve the miniaturization and packaging density of packaging and effectively reduce the conflicts in FPGA configuration data.

[0005] According to the technical solution provided by the utility model, a 2.5D packaging system based on FPGA architecture, the 2.5D packaging system includes:

[0006] Package substrate;

[0007] A chip module is mounted on the first main surface of the packaging substrate and is electrically connected to the packaging substrate so as to lead the chip module out through the packaging substrate;

[0008] The chip module includes an intermediate substrate and a chip unit group laid flat on the intermediate substrate, wherein the chip unit group includes a communication interface module, a storage configuration module adapted to be connected to the communication interface module, and a chip selection signal control module adapted to be connected to the communication interface module;

[0009] The communication interface module includes an FPGA chip that can support multiple configuration modes.

[0010] The chip select signal control module is adaptively connected to the FPGA chip and the storage configuration module. Based on the chip select control of the chip select signal control module, the connection between the storage configuration module and the FPGA chip can be configured, and the connection state between the storage configuration module and the FPGA chip is adapted to the currently selected configuration mode.

[0011] A heat dissipation cover is arranged on the packaging substrate, so as to utilize the heat dissipation cover to package the chip module on the packaging substrate, wherein:

[0012] The heat dissipation cover contacts the chip unit group above the intermediate substrate.

[0013] A dummy sheet for balancing stress is also provided on the intermediate substrate, wherein:

[0014] The dummy chip, storage configuration module and chip selection control module are all located on the same side of the communication interface module;

[0015] The dummy chip is located between the storage configuration module and the chip selection control module, and the distance between the dummy chip and the chip selection control module is greater than the distance between the dummy chip and the storage configuration module.

[0016] The storage configuration module includes a Flash chip, and the chip selection signal control module includes a two-to-one signal selector, wherein:

[0017] The FPGA chip and the Flash chip are both connected to the module configuration interface;

[0018] The FPGA chip loads a chip selection signal to the two-to-one signal selector, and the two-to-one signal selector switches the working mode of the chip module between at least the Master SPI mode and the Master BPI mode based on the chip selection signal and the selection signal.

[0019] The FPGA chip, the Flash chip and the two-choice signal selector are flip-mounted on the intermediate substrate, wherein:

[0020] The FPGA chip, the Flash chip, and the one-to-one signal selector are assembled on the intermediate substrate through corresponding chip bump units, so as to be electrically connected to the intermediate substrate through corresponding chip bump units.

[0021] The chip unit group is plastic-sealed on the intermediate substrate by the unit group plastic sealing body, and the chip substrate bottom filling body is filled between the chip unit group and the intermediate substrate, wherein:

[0022] All chip bump units are sealed on the intermediate substrate through the chip substrate underfill.

[0023] The chip module is assembled on the first main surface of the packaging substrate through the module substrate bump unit;

[0024] A module substrate underfill is also disposed on the first main surface of the packaging substrate, wherein all module substrate bump units are sealed on the packaging substrate through the module substrate underfill.

[0025] A chip module assembly area adapted to the chip module is provided on the first main surface of the packaging substrate, wherein:

[0026] After the chip module is welded to the chip module assembly area, a resistor-capacitor unit group is further arranged on the first main surface of the packaging substrate;

[0027] The RC unit group includes a plurality of RC units. On the first main surface of the packaging substrate, the RC units in the RC unit group are distributed on both sides of the chip module assembly area.

[0028] A heat sink is also provided on the first main surface of the packaging substrate, wherein:

[0029] The heat sink is ring-shaped;

[0030] The resistor and capacitor unit group and the chip module assembly area are located in the inner circle of the heat sink.

[0031] A plurality of substrate bumps are implanted on the second main surface of the packaging substrate, wherein:

[0032] The substrate bumps are distributed in an array on the second main surface of the packaging substrate, and the substrate bumps include solder balls.

[0033] The utility model has the advantages that the chip module is stacked on the first main surface of the packaging substrate and electrically connected to the packaging substrate so as to lead out the chip module through the packaging substrate; the chip module includes an intermediate substrate and a chip unit group laid flat on the intermediate substrate, and adopts the current packaging form, which can effectively reduce the packaging area, improve the miniaturization of the packaging and the packaging density;

[0034] The communication interface module includes an FPGA chip that can support multiple configuration modes, so that the formed SiP system can support multiple configuration modes. The chip select signal control module is adapted to be connected with the FPGA chip. Based on the chip select control of the chip select signal control module, the storage configuration module and the FPGA chip can be configured to maintain independent data interaction, thereby effectively reducing conflicts in FPGA configuration data. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a system block diagram of an embodiment of the 2.5D packaging system of the utility model.

[0036] Figure 2This is a packaging schematic diagram of an embodiment of a 2.5D packaging system of the utility model.

[0037] Figure 3 The figure is a schematic diagram showing the distribution of a chip unit group on an intermediate substrate according to an embodiment of the present invention.

[0038] Figure 4 The figure is a schematic diagram of an embodiment of a packaging substrate of the utility model.

[0039] Figure 5 It is a side view of an embodiment of a packaging substrate of the utility model.

[0040] Figure 6 for Figure 5 Bottom view of .

[0041] Explanation of the accompanying drawings: 1-FPGA chip, 2-Flash chip, 3-two-choice signal selector, 4-module configuration interface, 5-FPGA chip input and output ports, 6-FPGA chip input and output lines, 7-SiP system, 8-selection signal line, 9-BPI chip select signal port, 10-configuration interface port, 11-unit group plastic package, 12-chip substrate bottom filling body, 13-intermediate substrate, 14-module substrate bottom filling body, 15-packaging substrate, 16-substrate bump, 17-chip bump unit, 18-module substrate bump unit, 19-dummy chip, 20-chip module assembly area, 21-heat sink, 22-resistance-capacitance unit, 23-heat sink cover. DETAILED DESCRIPTION

[0042] The utility model is further described below in conjunction with specific drawings and embodiments.

[0043] In order to improve the miniaturization and packaging density of the package and effectively reduce the conflicts in the FPGA configuration data, the utility model provides a 2.5D packaging system based on the FPGA architecture. Specifically, the 2.5D packaging system includes:

[0044] Packaging substrate 15;

[0045] A chip module is mounted on the first main surface of the packaging substrate 15 and is electrically connected to the packaging substrate 15 so as to lead the chip module out through the packaging substrate 15;

[0046] The chip module includes an intermediate substrate 13 and a chip unit group laid flat on the intermediate substrate 13, wherein the chip unit group includes a communication interface module, a storage configuration module adapted to be connected to the communication interface module, and a chip selection signal control module adapted to be connected to the communication interface module;

[0047] The communication interface module includes an FPGA chip 1 that can support multiple configuration modes.

[0048] The chip select signal control module is adaptively connected to the FPGA chip 1 and the storage configuration module. Based on the chip select control of the chip select signal control module, the connection between the storage configuration module and the FPGA chip 1 can be configured, and the connection state between the storage configuration module and the FPGA chip 1 is adapted to the currently selected configuration mode.

[0049] Specifically, the packaging substrate 15 can adopt the existing commonly used substrate form, and of course, can also adopt other forms, so as to adapt to the 2.5D packaging requirements of the present invention. Figure 2 and Figures 4 to 6 An embodiment of a packaging substrate 15 is shown in the figure, which shows that the packaging substrate 15 has a first main surface and a second main surface, wherein the first main surface and the second main surface are two main surfaces corresponding to the packaging substrate 15. In an embodiment of the utility model, a chip module is arranged above the first main surface of the packaging substrate 15. It can be understood that the chip module should be electrically connected to the packaging substrate 15 to lead out the chip module through the packaging substrate 15, wherein leading out the chip module through the packaging substrate 15 specifically includes realizing loading of external signals into the chip module, or exporting signals of the chip module, and the situation of leading out the chip module is related to the working state of the chip module, so as to meet the application scenario requirements of the entire SiP system 7.

[0050] The chip module is located above the first main surface of the packaging substrate 15. At this time, the chip module is stacked above the first main surface of the packaging substrate 15. In one embodiment of the utility model, the chip module includes an intermediate substrate 13 and a chip unit group laid flat on the intermediate substrate 13, wherein the intermediate substrate 13 can adopt an existing commonly used high-density substrate, and the form adopted by the intermediate substrate 13 is related to the 2.5D packaging requirements of the utility model. Specifically, the intermediate substrate 13 is above the first main surface of the packaging substrate 15, and the intermediate substrate 13 and the packaging substrate 15 are parallel to each other.

[0051] In one embodiment of the utility model, the chip unit group should include a communication interface module, a storage configuration module and a chip select signal control module. Therefore, the chip unit group is laid flat on the intermediate substrate 13, specifically, the communication interface module, the storage configuration module and the chip select signal control module are laid flat on the intermediate substrate 13. Figure 1 An embodiment in which the communication interface module adopts the FPGA chip 1 is shown. When the communication interface module adopts the FPGA chip 1, a SiP system 7 based on the FPGA architecture can be formed. From the working characteristics of the FPGA chip 1, it can be seen that the SiP system 7 based on the FPGA chip 1 can have the configuration capability to support multiple modes.

[0052] It can be seen from the above description that for the SiP system 7 based on the FPGA chip 1, when supporting the configuration capability of multiple modes, there will be configuration data conflicts, wherein the configuration data conflict is specifically a situation where the working mode of the storage configuration module is inconsistent with the working mode of the FPGA chip 1. In one embodiment of the utility model, chip selection control is performed by a chip selection signal control module, so that after the chip selection control is performed by the chip selection signal, the connection between the storage configuration module and the FPGA chip 1 can be configured, and the connection between the storage configuration module and the FPGA chip 1 is adapted to the currently selected configuration mode, that is, after the working mode of the SiP system 7 is configured, the connection between the storage configuration module and the FPGA chip 1 is adapted to the currently selected configuration mode. At this time, the configuration data conflict can be effectively avoided. For specific ways to avoid the configuration data conflict, please refer to the corresponding description below.

[0053] In one embodiment of the utility model, the storage configuration module includes a Flash chip 2, and the chip selection signal control module includes a two-to-one signal selector 3, wherein:

[0054] FPGA chip 1 and Flash chip 2 are both connected to the module configuration interface;

[0055] The FPGA chip 1 loads a chip selection signal to the two-to-one signal selector 3. The two-to-one signal selector 3 switches the working mode of the chip module between at least the Master SPI mode and the Master BPI mode based on the chip selection signal and the selection signal.

[0056] Figure 1 The figure shows a system block diagram of an embodiment in which the storage configuration module adopts a Flash chip 2 and the chip select signal control module adopts a two-to-one signal selector 3. The Flash chip 2 and the two-to-one signal selector 3 can be in existing commonly used forms, so as to meet the requirements of using the Flash chip 2 to provide storage capacity and using the two-to-one signal selector 3 to realize chip select signal control.

[0057] Figure 1 In the embodiment, both the FPGA chip 1 and the Flash chip 2 are adapted to be connected with the module configuration interface (CongigurattionInterface) 4. Meanwhile, the module configuration interface 4 is provided with a configuration interface port 10. The two-choice signal selector 3 is adapted to be connected with the FPGA chip 1 and the Flash chip 2. The two-choice signal selector 3 can receive the chip selection signal loaded by the FPGA chip 1. Meanwhile, the two-choice signal selector 3 also receives the selection signal. Figure 1 FIG. 8 shows an embodiment of simultaneously loading the selection signal into the FPGA chip 1 and the two-selection signal selector 3 through the selection signal line 8. Figure 1In the figure, the output end of the two-to-one signal selector 3 is connected to the BPI chip select signal port 9, and the two-to-one signal selector 3 is also connected to the Flash chip 2 so that the SPI chip select signal can be loaded to the Flash chip 2. The FPGA chip 1 is also connected to the FPGA chip input and output line 6, and the FPGA chip input and output line 6 is electrically connected to the FPGA chip input and output port 5.

[0058] In specific implementation, the module configuration interface 4 mostly adopts the SPI (Serial Peripheral Interface Bus) bus, that is, the Flash chip 2 can work in the Master SPI mode. In specific implementation, by selecting the selection signal loaded by the signal line 8, the mode of the FPGA chip 1 can be configured, such as the FPGA chip 1 can be configured to the Master BPI (Bus Peripheral Interface) mode or the Master SPI mode. Specifically, when it is necessary to configure the Master BPI mode, the Master BPI mode needs to be selected through the chip select signal and the selection signal through the two-choice signal selector 3.

[0059] The following example illustrates the situation of mode selection through the two-choice signal selector 3. A feasible mode selection method is: when the Master SPI mode is selected through the two-choice signal selector 3 based on the selection signal and the chip selection signal, at this time, the SPI chip selection signal output by the two-choice signal selector 3 is in a valid state, the Flash chip 2 can receive the SPI chip selection signal loaded by the two-choice signal selector 3, the Flash chip 2 is in an enabled working state, and the FPGA chip 1 can write data to the Flash chip 2 or read data in the Flash chip 2 through the module configuration interface 4. When a valid BPI chip selection signal is generated through the two-choice signal selector 3 based on the selection signal and the chip selection signal, at this time, the SiP system 7 is configured in the MasterBPI mode, the SPI chip selection signal is in an invalid state, and the Flash chip 2 is not selected to be enabled, then the FPGA chip 1 cannot write data to the Flash chip 2 or read data in the Flash chip 2 through the module configuration interface 4.

[0060] In a specific implementation, the chip select signal is a signal generated by the FPGA chip 1 and loaded into the two-to-one signal selector, such as Figure 1 As shown, the chip select signal and the selection signal may be in the same form as the prior art, so as to be able to generate a valid SPI chip select signal or a BPI chip select signal through the two-to-one signal selector 3 .

[0061] It can be seen that based on the chip select control of the chip select signal control module, the connection between the storage configuration module and the FPGA chip 1 can be configured, and the connection state between the storage configuration module and the FPGA chip 1 is adapted to the currently selected configuration mode; if the Master BPI mode is selected, the FPGA chip 1 cannot be adapted to the connection with the Flash chip 2; when it is in the Master SPI mode, the FPGA chip 1 can be adapted to the connection with the Flash chip 2, and data can be written to or read from the Flash chip 2.

[0062] It can be seen from the above description that the module configuration interface 4 can be brought out through the configuration interface port 10. At this time, it can be compatible with the functions of products on the market. At this time, the module configuration interfaces 4 interconnected between the Flash chip 2 and the FPGA chip 1 are all brought out to the outside. In order to avoid the signal conflict problem caused by the simultaneous output of data by the FLASH chip 2 when selecting other configuration modes, in one embodiment of the utility model, the SiP system 7 can be configured as the Master BPI mode or the Master SPI mode through the two-to-one signal selector 3. At this time, based on the chip select control of the chip select signal control module, the connection between the storage configuration module and the FPGA chip 1 can be configured, and the connection state between the storage configuration module and the FPGA chip 1 is adapted to the currently selected configuration mode, which can effectively solve the data conflict.

[0063] In one embodiment of the utility model, the FPGA chip 1, the Flash chip 2 and the two-to-one signal selector 3 are flip-mounted on the intermediate substrate 13, wherein:

[0064] The FPGA chip 1 , the Flash chip 2 , and the one-out-of-two signal selector 3 are assembled on the intermediate substrate 13 through corresponding chip bump units 17 , so as to be electrically connected to the intermediate substrate 13 through corresponding chip bump units 17 .

[0065] As can be seen from the above description, the FPGA chip 1, the Flash chip 2 and the two-choice signal selector 3 are all laid flat on the intermediate substrate 13. In order to form the required 2.5D packaging form, in one embodiment of the utility model, the FPGA chip 1, the Flash chip 2 and the two-choice signal selector 3 are all flip-mounted on the intermediate substrate 13. In order to be able to adapt to the connection between the intermediate substrate 3, Figure 2 , in which an FPGA chip 1, a Flash chip 2, and a two-choice signal selector 3 are assembled on an intermediate substrate 13 through corresponding chip bump units 17. Generally, the chip bump unit 17 may include a plurality of chip bumps, and the chip bumps may be used to realize corresponding electrical connection with the intermediate substrate 13.

[0066] Specifically, the FPGA chip 1 is assembled on the intermediate substrate 13 through a chip bump unit 17 adapted to the FPGA chip 1, the Flash chip 2 is assembled on the intermediate substrate 13 through a chip bump unit 17 adapted to the FLASH chip 1, and at the same time, the two-to-one signal selector 3 is assembled on the intermediate substrate 13 through a chip bump unit 17 adapted to the two-to-one signal selector 3, wherein the chip bump unit 17 adapted to the FPGA chip 1 is specifically capable of satisfying the electrical connection with the intermediate substrate 13. It can be understood that the FPGA chip 1, the Flash chip 2, and the two-to-one signal selector 3 are assembled on the intermediate substrate 13 through the corresponding chip bump units 17, and after being led out through the packaging substrate 15, at least Figure 1 The system block diagram shown in .

[0067] It is understandable that the number of chip bumps between different chip bump units 17 and the distribution positions on the intermediate substrate 13 may be different, and the specific requirements are subject to the ability to meet the adaptive electrical connection with the intermediate substrate 13, which will not be repeated here.

[0068] In one embodiment of the present invention, a dummy sheet 19 for balancing stress is further provided on the intermediate substrate 13, wherein:

[0069] The dummy chip 19, the storage configuration module and the chip selection control module are all located on the same side of the communication interface module;

[0070] The dummy chip 19 is located between the storage configuration module and the chip selection control module, and the distance between the dummy chip 19 and the chip selection control module is greater than the distance between the dummy chip 19 and the storage configuration module.

[0071] Figure 3 The figure shows a distribution diagram of an embodiment of an FPGA chip 1, a Flash chip 2 and a two-choice signal selector 3 on an intermediate substrate 13. In the figure, a dummy sheet 19 is also provided on the intermediate substrate 13. When the dummy sheet 19 is provided on the intermediate substrate 13, the dummy sheet 19 can be used to achieve stress balance. The dummy sheet 19 can adopt an existing commonly used form. It can be understood that the dummy sheet 19 also needs to be supported on the intermediate substrate 13 through the corresponding chip bump unit 17.

[0072] Figure 3 In the figure, the dummy chip 19, the storage configuration module and the chip selection control module are all located on the same side of the communication interface module; that is, the dummy chip 19, the Flash chip 2 and the two-choice signal selector are all located on the same side of the FPGA chip 1. In the figure, the dummy chip 19, the FLASH chip 2 and the two-choice signal selector 3 are all located on the right side of the FPGA chip 1. In addition, Figure 3Also shown is an embodiment in which the length of the FPGA chip 1 is greater than the arrangement length of the dummy chip 19, the Flash chip 2 and the two-choice signal selector 3, that is, when the dummy chip 19, the Flash chip 2 and the two-choice signal selector 3 are projected toward the FPGA chip 1, the projection area is all located inside the FPGA chip 1, and the dummy chip 19 is located between the Flash chip 2 and the two-choice signal selector 3. At this time, stress balance can be effectively achieved by using the dummy chip 19.

[0073] Specifically, the distance between the dummy chip 19 and the chip selection control module is greater than the distance between the dummy chip 19 and the storage configuration module; in one embodiment of the utility model, the distances between the FPGA chip 1 and the dummy chip 19 and the Flash chip 2 are all 150 μm, the distance between the dummy chip 19 and the Flash chip 2 may also be 150 μm, and the distance between the dummy chip 19 and the two-choice signal selector 3 is greater than 150 μm. By setting the corresponding distances between the FPGA chip 1, the dummy chip 19, the Flash chip 2 and the two-choice signal selector 3, the density of the tiles on the intermediate substrate 13 can be effectively improved while achieving stress balance, and the miniaturization and packaging density of the SiP system 7 can be improved.

[0074] In one embodiment of the utility model, the chip unit group is plastic-encapsulated on the intermediate substrate 13 by the unit group plastic-encapsulation body 11, and the chip substrate bottom filling body 12 is filled between the chip unit group and the intermediate substrate 13, wherein:

[0075] All chip bump units 17 are sealed on the interposer substrate 13 through the chip substrate underfill 12 .

[0076] In order to improve the stability and reliability of the FPGA chip 1, the Flash chip 2, the two-choice signal selector 3 and the dummy chip 19 on the intermediate substrate 13, in one embodiment of the utility model, the chip unit group is plastic-sealed on the intermediate substrate 13 using a unit group plastic sealing body 11, that is, the FPGA chip 1, the Flash chip 2, the two-choice signal selector 3 and the dummy chip 19 are plastic-sealed on the intermediate substrate 13 using the unit group plastic sealing body 11, and the unit group plastic sealing body 11 can be formed by using the existing commonly used plastic sealing process.

[0077] In addition, a chip substrate bottom filler 12 can be filled between the chip unit group and the intermediate substrate 13, and all chip bump units 17 can be sealed on the intermediate substrate 13 through the chip substrate bottom filler 12, wherein the chip substrate bottom filler 12 can be prepared by using the existing commonly used bottom filling process, and the chip substrate bottom filler 12 can be used to package and protect the chip bump units 17.

[0078] In one embodiment of the utility model, the chip module is assembled on the first main surface of the packaging substrate 15 through the module substrate bump unit 18;

[0079] A module substrate underfill 14 is also disposed on the first main surface of the packaging substrate 15 , wherein all module substrate bump units 18 are sealed on the packaging substrate 15 by the module substrate underfill 14 .

[0080] As can be seen from the above description, the intermediate substrate 13 is located above the first main surface of the packaging substrate 15. In order to adapt the chip module to the packaging substrate 15 for electrical connection and lead the chip module out through the packaging substrate 15, during specific implementation, a module substrate bump unit 18 may be provided on the intermediate substrate 13. Figure 2 An embodiment of the module substrate bump unit 18 is shown in the figure. The module substrate bump unit 18 and the chip unit group are distributed on two corresponding surfaces of the intermediate substrate 13. It can be understood that the module substrate bump unit 18 includes a plurality of module substrate bumps. The number of module substrate bumps and their distribution positions on the intermediate substrate 13 are based on satisfying the adaptive electrical connection between the intermediate substrate 13 and the packaging substrate 15.

[0081] In specific implementation, the module substrate bottom filler 14 can be used to perform bottom filling, so as to utilize the module substrate bottom filler 14 to encapsulate and protect the module substrate bump unit 18. The module substrate bottom filler 14 can be prepared using existing bottom filler materials and bottom filler processes, and the specific method is based on the ability to form the module substrate bottom filler 14.

[0082] In one embodiment of the present invention, a chip module assembly area 20 adapted to the chip module is provided on the first main surface of the packaging substrate 15, wherein:

[0083] After the chip module is welded to the chip module assembly area 20, a resistor-capacitor unit group is also arranged on the first main surface of the packaging substrate 15;

[0084] The RC unit group includes a plurality of RC units 22 . On the first main surface of the packaging substrate 15 , the RC units 22 in the RC unit group are distributed on both sides of the chip module assembly area 20 .

[0085] Figure 4 An embodiment of the first main surface of the packaging substrate 15 is shown in FIG. In the figure, a chip module assembly area 20 can be set in the central area of ​​the first main surface of the packaging substrate 15. The area of ​​the chip module assembly area 20 should be smaller than the area of ​​the first main surface of the packaging substrate 15. Figure 4 In the embodiment, the chip module assembly area 20 is square, and the area of ​​the chip module assembly area 20 is sufficient to accommodate the intermediate substrate 13 , and the module substrate bump unit 18 on the intermediate substrate 13 can be welded to the chip module assembly area 20 .

[0086] A resistor-capacitor unit group is also arranged outside the chip module assembly area 20. The resistor-capacitor unit group may include a plurality of resistor-capacitor units 22. Figure 42 shows an embodiment in which the RC units 22 are distributed on both sides of the chip module assembly area 20. Of course, in specific implementation, the number and distribution positions of the RC units 22 can be selected according to actual needs. Generally, the RC units 22 can be used to filter the power supply or perform pull-up or pull-down processing of the signal. After the chip module is welded to the chip module assembly area 20, it can be electrically connected to the corresponding RC units 22 through the wiring on the package substrate 15.

[0087] As can be seen from the above description, metal traces are distributed in the package substrate 15 and the intermediate substrate 13, wherein the metal traces can be prepared by the existing RDL process, or formed by other processes, specifically to meet the requirements of the adapted electrical connection and form Figure 1 The system block diagram in the table shall prevail.

[0088] In one embodiment of the present invention, a heat sink 21 is further provided on the first main surface of the packaging substrate 15, wherein:

[0089] The heat sink 21 is ring-shaped;

[0090] The RC unit group and chip module assembly area 20 are located in the inner circle of the heat sink 21 .

[0091] Figure 4 and Figure 5 Also shown is an embodiment in which a heat sink 21 is provided on the first main surface of the packaging substrate 15. In the figure, the heat sink 21 is ring-shaped. The heat sink 21 can adopt existing commonly used heat dissipation materials. The heat sink 21 is distributed on the outer edge of the first main surface of the packaging substrate 15, and the resistor-capacitor unit group and the chip module assembly area 20 are located in the inner circle of the heat sink 21. The resistor-capacitor unit group and the chip module assembly area 20 are placed in the inner circle of the heat sink 21 so as not to affect the subsequent packaging. Figure 5 In the embodiment, after the heat sink 21 is disposed on the first main surface of the packaging substrate 15 , the heat sink 21 protrudes from the first main surface of the packaging substrate 15 .

[0092] In one embodiment of the present invention, a plurality of substrate bumps 16 are implanted on the second main surface of the packaging substrate 15, wherein:

[0093] The substrate bumps 16 are distributed in an array on the second main surface of the package substrate 15 , and the substrate bumps 16 include solder balls.

[0094] Figure 6An embodiment of setting a plurality of substrate bumps 16 on the second main surface of the package substrate 15 is shown in the figure. In the figure, the substrate bumps 16 are distributed in an array. The number and distribution position of the substrate bumps 16 can be selected according to needs, so as to meet the requirements of leading out the chip module. In specific implementation, the substrate bumps 16 can be solder balls, and the substrate bumps 16 can be prepared on the second main surface of the package substrate 15 by a ball planting process. Of course, other processes can also be used to prepare the second main surface of the package substrate 15. The specific preparation process can be selected according to actual needs, so as to meet the preparation requirements of the substrate bumps 16.

[0095] From the above description, it can be seen that after a number of substrate bumps 16 are set on the second main surface of the packaging substrate 15, the substrate bumps 16 need to be electrically connected to the above-mentioned chip module. The specific electrical connection method can be selected according to needs to meet the connection requirements after being led out through the substrate bumps 15.

[0096] In one embodiment of the present invention, a heat dissipation cover 23 is provided on the packaging substrate 15, so as to utilize the heat dissipation cover 23 to package the chip module on the packaging substrate 15, wherein:

[0097] The heat dissipation cover 23 contacts the chip unit group above the intermediate substrate 13 .

[0098] Figure 2 An embodiment of packaging using a heat dissipation cover 23 is shown. The heat dissipation cover 23 can accommodate the chip module. The heat dissipation cover 23 can adopt an existing commonly used form. The lower end of the heat dissipation cover 23 should be placed on the heat sink 21, and the top of the heat dissipation cover 23 can contact the chip unit group so that the heat generated by the chip unit group can be dissipated in time to improve the heat dissipation efficiency.

[0099] The above is only the preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.

Claims

1. A 2.5D packaging system based on FPGA architecture, characterized in that: The 2.5D packaging system includes: Package substrate; A chip module is mounted on the first main surface of the packaging substrate and is electrically connected to the packaging substrate so as to lead the chip module out through the packaging substrate; The chip module includes an intermediate substrate and a chip unit group laid flat on the intermediate substrate, wherein the chip unit group includes a communication interface module, a storage configuration module adapted to be connected to the communication interface module, and a chip selection signal control module adapted to be connected to the communication interface module; The communication interface module includes an FPGA chip that can support multiple configuration modes. The chip select signal control module is adaptively connected to the FPGA chip and the storage configuration module. Based on the chip select control of the chip select signal control module, the connection between the storage configuration module and the FPGA chip can be configured, and the connection state between the storage configuration module and the FPGA chip is adapted to the currently selected configuration mode.

2. The 2.5D packaging system based on FPGA architecture according to claim 1, characterized in that: A heat dissipation cover is arranged on the packaging substrate, so as to utilize the heat dissipation cover to package the chip module on the packaging substrate, wherein: The heat dissipation cover contacts the chip unit group above the intermediate substrate.

3. The 2.5D packaging system based on FPGA architecture according to claim 1, characterized in that: The intermediate substrate is also provided with a dummy sheet for balancing stress, wherein: The dummy chip, storage configuration module and chip selection control module are all located on the same side of the communication interface module; The dummy chip is located between the storage configuration module and the chip selection control module, and the distance between the dummy chip and the chip selection control module is greater than the distance between the dummy chip and the storage configuration module.

4. The 2.5D packaging system based on FPGA architecture according to claim 3, characterized in that: The storage configuration module includes a Flash chip, and the chip selection signal control module includes a two-to-one signal selector, wherein: The FPGA chip and the Flash chip are both connected to the module configuration interface; The FPGA chip loads a chip selection signal to the two-to-one signal selector, and the two-to-one signal selector switches the working mode of the chip module between at least the Master SPI mode and the Master BPI mode based on the chip selection signal and the selection signal.

5. The 2.5D packaging system based on FPGA architecture according to claim 4, characterized in that: The FPGA chip, the Flash chip and the two-choice signal selector are flip-mounted on the intermediate substrate, wherein: The FPGA chip, the Flash chip, and the one-to-one signal selector are assembled on the intermediate substrate through corresponding chip bump units, so as to be electrically connected to the intermediate substrate through corresponding chip bump units.

6. The 2.5D packaging system based on FPGA architecture according to claim 5, characterized in that: The chip unit group is plastic-sealed on the intermediate substrate by the unit group plastic sealing body, and the chip substrate bottom filling body is filled between the chip unit group and the intermediate substrate, wherein: All chip bump units are sealed on the intermediate substrate through the chip substrate underfill.

7. The 2.5D packaging system based on FPGA architecture according to claim 5, characterized in that: The chip module is assembled on the first main surface of the packaging substrate through the module substrate bump unit; A module substrate underfill is also disposed on the first main surface of the packaging substrate, wherein all module substrate bump units are sealed on the packaging substrate through the module substrate underfill.

8. The 2.5D packaging system based on FPGA architecture according to any one of claims 1 to 7, characterized in that: A chip module assembly area adapted to the chip module is provided on the first main surface of the packaging substrate, wherein: After the chip module is welded to the chip module assembly area, a resistor-capacitor unit group is further arranged on the first main surface of the packaging substrate; The RC unit group includes a plurality of RC units. On the first main surface of the packaging substrate, the RC units in the RC unit group are distributed on both sides of the chip module assembly area.

9. The 2.5D packaging system based on FPGA architecture according to claim 8, characterized in that: A heat sink is also provided on the first main surface of the packaging substrate, wherein: The heat sink is ring-shaped; The resistor and capacitor unit group and the chip module assembly area are located in the inner circle of the heat sink.

10. The 2.5D packaging system based on FPGA architecture according to any one of claims 1 to 7, characterized in that: A plurality of substrate bumps are implanted on the second main surface of the packaging substrate, wherein: The substrate bumps are distributed in an array on the second main surface of the packaging substrate, and the substrate bumps include solder balls.

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