Chip reset circuit and chip reset device
By designing a chip reset circuit, using the same interface to output sampled signals and reset signals, the problem of insufficient number of IO pins is solved, the chip reset function is set, and the reset needs of the controlled chip is met.
Patent Information
- Application Number
- CN202421562138.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-03
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2034-07-03
AI Technical Summary
In the prior art, the number of IO pins is not enough to set the reset function of the functional chip, which affects the implementation of the solution.
Design a chip reset circuit, including a control module, a reset module and a voltage sampling module, output sampling signals and reset signals through the same interface, realizing multifunctional multiplexing of the interface, ensuring that the chip reset can be achieved even when the IO interface is insufficient.
It realizes that the chip reset function can be set when the IO interface is insufficient to meet the reset needs of the controlled chip and avoids the problem of affecting the implementation of the solution due to insufficient IO pins.
Smart Images
Figure CN222801113U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of equipment control, in particular to a chip reset circuit and a chip reset device. Background Art
[0002] In order to prevent the functional chip from falling into an infinite loop, a reset pin is usually set for the functional chip, and a reset signal is output to the reset pin through an MCU (Microcontroller Unit) to reset the functional chip.
[0003] Different MCUs provide different numbers of input and output IO pins. When the number of IO pins is insufficient to set the reset function, the implementation of the solution will be affected. Utility Model Content
[0004] The main purpose of the utility model is to provide a chip reset circuit and a chip reset device, aiming to solve the problem in the prior art that the number of IO pins is insufficient to set a reset function for a functional chip.
[0005] To achieve the above object, the utility model provides a chip reset circuit, which is connected to a controlled chip; the chip reset circuit comprises a control module, a reset module and a voltage sampling module; the first interface of the control module is connected to the reset interface of the controlled chip through the reset module, and the first interface of the control module is also connected to the second interface of the control module through the voltage sampling module; wherein:
[0006] The control module is used to output a reference voltage to the voltage sampling module through the first interface;
[0007] The voltage sampling module is used to sample the reference voltage to obtain a sampled voltage, and output the sampled voltage to the second interface of the control module;
[0008] The control module is further configured to receive the sampled voltage through the second interface;
[0009] The control module is further configured to output a reset signal through the first interface;
[0010] The reset module is used to output a reset trigger signal to the reset interface of the controlled chip after receiving the reset signal.
[0011] Optionally, the reset module includes a connection unit, a level conversion unit and a signal output unit; the input end of the connection unit is connected to the first interface of the control module, the output end of the connection unit is connected to the input end of the level conversion unit, the output end of the level conversion unit is connected to the control end of the signal output unit, and the output end of the signal output unit is connected to the reset interface of the controlled chip; wherein:
[0012] The connection unit is used to trigger the level conversion unit to turn on after receiving the reset signal;
[0013] The level conversion unit is used to send a trigger signal to the signal output unit when it is turned on;
[0014] The signal output unit is used to send the reset trigger signal to the reset module after receiving the trigger signal.
[0015] Optionally, the signal output unit includes a first switch tube and a first resistor; wherein:
[0016] The control end of the first switch tube is connected to the output end of the level conversion unit, the input end of the first switch tube is grounded, the output end of the first switch tube is connected to the reset interface of the reset module, and the output end of the first switch tube is also connected to the power supply through the first resistor.
[0017] Optionally, the first switch tube is an NMOS tube, wherein:
[0018] The control end of the first switch tube is the gate of the NMOS tube, the input end of the first switch tube is the drain of the NMOS tube, and the output end of the first switch tube is the source of the NMOS tube.
[0019] Optionally, the level conversion unit includes a second switch tube and a second resistor; wherein:
[0020] The output end of the second switch tube is connected to the input end of the signal output unit, the output end of the second switch tube is also grounded through the second resistor, the input end of the second switch tube is connected to the power supply, and the control end of the second switch tube is connected to the output end of the connection unit.
[0021] Optionally, the second switch tube is a PMOS tube, wherein:
[0022] The control end of the second switch tube is the gate of the PMOS tube, the input end of the second switch tube is the source of the PMOS tube, and the output end of the second switch tube is the drain of the PMOS tube.
[0023] Optionally, the connectivity unit includes a first capacitor and a third resistor, the first end of the first capacitor is connected to the first interface of the control module, the second end of the first capacitor is connected to the input end of the level conversion unit, and the second end of the first capacitor is also connected to the power supply through the third resistor.
[0024] Optionally, the voltage sampling module includes a fourth resistor and a fifth resistor; wherein:
[0025] A first end of the fourth resistor is connected to the first interface of the control module, a second end of the fourth resistor is connected to the second interface of the control module, and the second end of the fourth resistor is also grounded through the fifth resistor.
[0026] Optionally, the control module includes a plurality of corresponding first interfaces and second interfaces;
[0027] Setting the voltage sampling module for each corresponding first interface and second interface;
[0028] Each of the first interfaces is connected to a reset interface of the controlled chip through a reset module.
[0029] In addition, to achieve the above-mentioned purpose, the utility model also provides a chip reset device, the chip reset device includes a chip reset circuit, and the chip reset circuit is configured as the chip reset circuit as described above.
[0030] The utility model proposes a chip reset circuit and a chip reset device, wherein the chip reset circuit is connected to a controlled chip; the chip reset circuit includes a control module, a reset module and a voltage sampling module; the first interface of the control module is connected to the reset interface of the controlled chip through the reset module, and the first interface of the control module is also connected to the second interface of the control module through the voltage sampling module; wherein: the control module is used to output a reference voltage to the voltage sampling module through the first interface; the voltage sampling module is used to sample the reference voltage to obtain a sampling voltage, and output the sampling voltage to the second interface of the control module; the control module is also used to receive the sampling voltage through the second interface; the control module is also used to output a reset signal through the first interface; the reset module is used to output a reset trigger signal to the reset interface of the controlled chip after receiving the reset signal. The sampling signal and the reset signal are output through the same interface, thereby realizing the multi-functional multiplexing of the first interface, and even in the case of insufficient IO interface, the reset function can be set to meet the reset needs of the controlled chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.
[0032] Figure 1 This is a functional module diagram of an embodiment of a chip reset circuit of the utility model;
[0033] Figure 2 The chip reset circuit of the utility model is applied in Figure 1 Circuit structure diagram in the embodiment.
[0034] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings.
[0035] Description of Figure Numbers:
[0036] Label name Label name 100 Control Module R1~R5 The first resistor to the fifth resistor 200 Reset module Q1~Q2 The first switch tube ~ the second switch tube 210 Signal output unit C1 First capacitor 220 Level Shifter 300 Voltage sampling module 230 Connectivity Unit DETAILED DESCRIPTION
[0037] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0038] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0039] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0040] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.
[0041] The utility model provides a chip reset circuit, which is used in a chip reset device. Figure 1 , Figure 1 This is a functional module diagram of an embodiment of the chip reset circuit of the utility model. In this embodiment, the chip reset circuit is connected to the controlled chip; the chip reset circuit includes a control module 100, a reset module 200 and a voltage sampling module 300; the first interface P1 of the control module 100 is connected to the reset interface of the controlled chip through the reset module 200, and the first interface P1 of the control module 100 is also connected to the second interface P2 of the control module 100 through the voltage sampling module 300; wherein:
[0042] The control module 100 is used to output a reference voltage to the voltage sampling module 300 through the first interface P1;
[0043] The voltage sampling module 300 is used to sample the reference voltage to obtain a sampled voltage, and output the sampled voltage to the second interface P2 of the control module 100;
[0044] The control module 100 is further configured to receive the sampled voltage through the second interface P2;
[0045] The control module 100 is further configured to output a reset signal through the first interface P1;
[0046] The reset module 200 is used to output a reset trigger signal to the reset interface of the controlled chip after receiving the reset signal.
[0047] The specific types of the control module 100 and the controlled chip can be set based on actual needs.
[0048] The first interface P1 of the control module 100 is an IO interface, and the second interface P2 is an ADC interface.
[0049] When performing ADC sampling, the first interface P1 of the control module 100 outputs a reference voltage for the voltage sampling module 300 to collect to obtain a sampled voltage. The control module 100 receives the sampled voltage to complete ADC sampling.
[0050] When the controlled chip needs to be reset, the first interface P1 of the control module 100 outputs a reset signal to trigger the reset module 200 to output a reset trigger signal to the reset interface of the controlled chip.
[0051] It can be understood that since the input end of the reset module 200 and the output end of the voltage sampling module 300 are both connected to the first interface P1 of the control module 100, if the reference voltage may have a signal with the same characteristics as the reset signal, the reset of the controlled chip may be triggered by mistake during ADC sampling; therefore, in order to ensure that the ADC sampling and the reset function of the controlled chip can be correctly implemented, it is necessary to set the reference voltage to be different from the reset signal, so as to ensure that the reset module 200 only outputs the reset trigger signal to the reset end of the controlled chip after receiving the reset signal, thereby realizing the reset of the controlled chip.
[0052] This embodiment outputs the sampling signal and the reset signal through the same interface, thereby realizing the multifunctional multiplexing of the first interface P1. Even when the IO interface is insufficient, the reset function can be set to meet the reset requirement of the controlled chip.
[0053] Further, the reset module 200 includes a connection unit 230, a level conversion unit 220 and a signal output unit 210; the input end of the connection unit 230 is connected to the first interface P1 of the control module 100, the output end of the connection unit 230 is connected to the input end of the level conversion unit 220, the output end of the level conversion unit 220 is connected to the control end of the signal output unit 210, and the output end of the signal output unit 210 is connected to the reset interface of the controlled chip; wherein:
[0054] The connecting unit 230 is used to trigger the level conversion unit 220 to turn on after receiving the reset signal;
[0055] The level conversion unit 220 is used to send a trigger signal to the signal output unit 210 when turned on;
[0056] The signal output unit 210 is used to send the reset trigger signal to the reset module 200 after receiving the trigger signal.
[0057] The reset signal is a trigger signal of the reset module 200, and is used to trigger the reset module 200 to perform a reset operation on the controlled chip, that is, to send a reset trigger signal to the controlled chip.
[0058] The reset trigger signal is a signal that triggers the reset operation of the controlled chip, and is used to control the controlled chip to perform the reset operation.
[0059] The reset signal acts on the reset module 200, and the reset trigger signal acts on the controlled chip. The reset signal and the reset trigger signal act on different objects. Therefore, the reset signal and the reset trigger signal are not necessarily the same. The parameters of the specific reset signal and the reset trigger signal can be set based on actual needs.
[0060] The communication unit 230, as a trigger unit in the reset module 200, responds to the reception of the reset signal; after receiving the reset signal, the level conversion unit 220 is triggered to start. It can be understood that, limited by the operating characteristics of the device, the trigger signal of the signal trigger unit is not necessarily the reset signal sent by the control module 100. Therefore, in order to ensure the correct triggering of the signal trigger unit, the level conversion unit 220 is set to convert the reset signal into a trigger signal.
[0061] When receiving the trigger signal, the signal trigger unit outputs a reset trigger signal to the controlled chip.
[0062] Furthermore, the signal output unit 210 includes a first switch tube Q1 and a first resistor R1; wherein:
[0063] The control end of the first switch tube Q1 is connected to the output end of the level conversion unit 220, the input end of the first switch tube Q1 is grounded, the output end of the first switch tube Q1 is connected to the reset interface of the reset module 200, and the output end of the first switch tube Q1 is also connected to the power supply through the first resistor R1.
[0064] In this embodiment, the reset trigger signal is a low level signal.
[0065] When the control end of the first switch tube Q1 does not receive a trigger signal, the first switch tube Q1 is turned off; at this time, the reset interface of the controlled chip is connected to the power supply through the first resistor R1, and the reset interface of the controlled chip presents a high level, and reset is not triggered;
[0066] When the control end of the first switch tube Q1 receives a trigger signal, the first switch tube Q1 is turned on; at this time, the reset interface of the controlled chip is grounded through the first switch tube Q1, and the reset interface of the controlled chip presents a low level, triggering reset.
[0067] Furthermore, the first switch tube Q1 is an NMOS tube, wherein:
[0068] The control end of the first switch tube Q1 is the gate of the NMOS tube, the input end of the first switch tube Q1 is the drain of the NMOS tube, and the output end of the first switch tube Q1 is the source of the NMOS tube.
[0069] In this embodiment, an NMOS tube is used as the first switch tube Q1; in this embodiment, the trigger signal is a high-level signal. When the gate of the first switch tube Q1 receives a high-level signal, the first switch tube Q1 is turned on, and when the gate of the first switch tube Q1 receives a low-level signal, the first switch tube Q1 is turned off.
[0070] Furthermore, the level conversion unit 220 includes a second switch tube Q2 and a second resistor R2; wherein:
[0071] The output end of the second switch tube Q2 is connected to the input end of the signal output unit 210, and the output end of the second switch tube Q2 is also grounded through the second resistor R2. The input end of the second switch tube Q2 is connected to the power supply, and the control end of the second switch tube Q2 is connected to the output end of the connection unit 230.
[0072] When the control end of the second switch tube Q2 does not receive the reset signal, the second switch tube Q2 is turned off; at this time, the control end of the signal output unit 210 is grounded through the second resistor R2, and the control end of the signal output unit 210 presents a low level;
[0073] When the control end of the second switch tube Q2 receives the reset signal, the second switch tube Q2 is turned on; at this time, the control end of the signal output unit 210 is connected to the power supply through the second switch tube Q2, and the reset interface of the controlled chip presents a high level.
[0074] Furthermore, the second switch tube Q2 is a PMOS tube, wherein:
[0075] The control end of the second switch tube Q2 is the gate of the PMOS tube, the input end of the second switch tube Q2 is the source of the PMOS tube, and the output end of the second switch tube Q2 is the drain of the PMOS tube.
[0076] In this embodiment, a PMOS tube is used as the second switch tube Q2; in this embodiment, the reset signal is a high-level signal. When the gate of the second switch tube Q2 receives a low-level signal, the second switch tube Q2 is turned on, and when the gate of the second switch tube Q2 receives a high-level signal, the second switch tube Q2 is turned off.
[0077] Furthermore, the connection unit 230 includes a first capacitor C1 and a third resistor R3, the first end of the first capacitor C1 is connected to the first interface P1 of the control module 100, the second end of the first capacitor C1 is connected to the input end of the level conversion unit 220, and the second end of the first capacitor C1 is also connected to the power supply through the third resistor R3.
[0078] The first capacitor C1 and the third resistor R3 form a high-pass circuit.
[0079] When the first interface P1 of the control module 100 is at a high level, the first end of the first capacitor C1 is at a high level, and the second end of the first capacitor C1 is connected to the power supply through the third resistor R3 and is at a high level; at this time, the input end of the level conversion unit 220 is at a high level;
[0080] When the first interface P1 of the control module 100 outputs a low level, the first end and the second end of the first capacitor C1 both present a low level. At this time, the input end of the level conversion unit 220 presents a low level.
[0081] After the first interface P1 of the control module 100 stops outputting a low level, when no ADC sampling is performed, the first interface P1 of the control module 100 is in a high impedance state, and the power supply charges the first capacitor C1 through the third resistor R3. When the voltage at the second end of the first capacitor C1 is greater than the conduction voltage of the second switch tube Q2, the second switch tube Q2 is turned off and stops sending the trigger signal to the signal output unit 210. The specific conduction time of the second switch tube Q2 can be set by adjusting the parameters of the third resistor R3 and the first capacitor C1.
[0082] Furthermore, the voltage sampling module 300 includes a fourth resistor R4 and a fifth resistor R5; wherein:
[0083] The first end of the fourth resistor R4 is connected to the first interface P1 of the control module 100 , the second end of the fourth resistor R4 is connected to the second interface P2 of the control module 100 , and the second end of the fourth resistor R4 is also grounded through the fifth resistor R5 .
[0084] The fourth resistor R4 and the fifth resistor R5 form a voltage divider circuit. The reference voltage output by the first interface P1 of the control module 100 is divided by the fourth resistor R4 and the fifth resistor R5 to obtain a sampling voltage. The second interface P2 of the control module 100 receives the sampling voltage to implement ADC sampling.
[0085] Further, the control module 100 includes a plurality of corresponding first interfaces P1 and second interfaces P2;
[0086] The voltage sampling module 300 is set for each corresponding first interface P1 and second interface P2;
[0087] Each of the first interfaces P1 is connected to a reset interface of the controlled chip through a reset module 200 .
[0088] It is understandable that in the system, the control module 100 often needs to control multiple controlled chips, and when the number of IO interfaces is limited, multiple IO interfaces can be reused at the same time, thereby reducing the need for more IO interfaces; the specific number of multiplexing can be set based on actual needs.
[0089] The following is based on Figure 2 The complete implementation process of this application is described as follows:
[0090] ADC sampling:
[0091] The first interface P1 outputs a high level reference voltage;
[0092] The fourth resistor R4 and the fifth resistor R5 divide the reference voltage to obtain a sampling voltage, and the second interface P2 of the control module 100 receives the sampling voltage to implement ADC sampling;
[0093] The first end of the first capacitor C1 presents a high level, both ends of the first capacitor C1 are high levels, the gate of the second switch tube Q2 presents a high level, the second switch tube Q2 is turned off, the gate of the first switch tube Q1 is grounded through the second resistor R2, the first switch tube Q1 is turned off, the reset interface of the controlled chip is connected to the power supply through the first resistor R1, the reset interface of the controlled chip presents a high level, and the reset is not triggered;
[0094] The controlled chip is reset:
[0095] The first interface P1 outputs a low-level reset signal, and the ADC sampling part does not work;
[0096] The first end and the second end of the first capacitor C1 both present a low level, the gate of the second switch tube Q2 presents a low level, the second switch tube Q2 is turned on, the gate of the first switch tube Q1 is connected to the power supply through the second switch tube Q2, the first switch tube Q1 is turned on, the reset interface of the controlled chip is grounded through the first switch tube Q1, the reset interface of the controlled chip presents a low level, and reset is triggered;
[0097] After the first interface P1 stops outputting the reset signal:
[0098] The first interface P1 of the control module 100 is in a high impedance state, and the power supply charges the first capacitor C1 through the third resistor R3. When the voltage at the second end of the first capacitor C1 is greater than the turn-on voltage of the second switch tube Q2, the second switch tube Q2 is turned off.
[0099] The utility model also protects a chip reset device, which includes a chip reset circuit. The structure of the chip reset circuit can refer to the above embodiment and will not be described in detail here. As a matter of course, since the chip reset device of this embodiment adopts the technical solution of the above chip reset circuit, the chip reset device has all the beneficial effects of the above chip reset circuit.
[0100] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, article or system including the element. The serial numbers of the above-mentioned embodiments of the utility model are for description only and do not represent the advantages and disadvantages of the embodiments.
[0101] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A chip reset circuit, characterized in that: The chip reset circuit is connected to the controlled chip; the chip reset circuit includes a control module, a reset module and a voltage sampling module; the first interface of the control module is connected to the reset interface of the controlled chip through the reset module, and the first interface of the control module is also connected to the second interface of the control module through the voltage sampling module; wherein: The control module is used to output a reference voltage to the voltage sampling module through the first interface; The voltage sampling module is used to sample the reference voltage to obtain a sampled voltage, and output the sampled voltage to the second interface of the control module; The control module is further configured to receive the sampled voltage through the second interface; The control module is further configured to output a reset signal through the first interface; The reset module is used to output a reset trigger signal to the reset interface of the controlled chip after receiving the reset signal.
2. The chip reset circuit according to claim 1, characterized in that: The reset module includes a connection unit, a level conversion unit and a signal output unit; the input end of the connection unit is connected to the first interface of the control module, the output end of the connection unit is connected to the input end of the level conversion unit, the output end of the level conversion unit is connected to the control end of the signal output unit, and the output end of the signal output unit is connected to the reset interface of the controlled chip; wherein: The connection unit is used to trigger the level conversion unit to turn on after receiving the reset signal; The level conversion unit is used to send a trigger signal to the signal output unit when it is turned on; The signal output unit is used to send the reset trigger signal to the reset module after receiving the trigger signal.
3. The chip reset circuit according to claim 2, characterized in that: The signal output unit includes a first switch tube and a first resistor; wherein: The control end of the first switch tube is connected to the output end of the level conversion unit, the input end of the first switch tube is grounded, the output end of the first switch tube is connected to the reset interface of the reset module, and the output end of the first switch tube is also connected to the power supply through the first resistor.
4. The chip reset circuit as claimed in claim 3, characterized in that: The first switch tube is an NMOS tube, wherein: The control end of the first switch tube is the gate of the NMOS tube, the input end of the first switch tube is the drain of the NMOS tube, and the output end of the first switch tube is the source of the NMOS tube.
5. The chip reset circuit according to claim 2, characterized in that: The level conversion unit includes a second switch tube and a second resistor; wherein: The output end of the second switch tube is connected to the input end of the signal output unit, the output end of the second switch tube is also grounded through the second resistor, the input end of the second switch tube is connected to the power supply, and the control end of the second switch tube is connected to the output end of the connection unit.
6. The chip reset circuit as claimed in claim 5, characterized in that: The second switch tube is a PMOS tube, wherein: The control end of the second switch tube is the gate of the PMOS tube, the input end of the second switch tube is the source of the PMOS tube, and the output end of the second switch tube is the drain of the PMOS tube.
7. The chip reset circuit according to claim 2, characterized in that: The connection unit includes a first capacitor and a third resistor, the first end of the first capacitor is connected to the first interface of the control module, the second end of the first capacitor is connected to the input end of the level conversion unit, and the second end of the first capacitor is also connected to the power supply through the third resistor.
8. The chip reset circuit according to claim 1, characterized in that: The voltage sampling module includes a fourth resistor and a fifth resistor; wherein: A first end of the fourth resistor is connected to the first interface of the control module, a second end of the fourth resistor is connected to the second interface of the control module, and the second end of the fourth resistor is also grounded through the fifth resistor.
9. The chip reset circuit according to claim 1, characterized in that: The control module includes a plurality of corresponding first interfaces and second interfaces; The voltage sampling module is provided for each corresponding first interface and second interface; Each of the first interfaces is connected to a reset interface of the controlled chip through a reset module.
10. A chip resetting device, characterized in that: The chip reset device comprises a chip reset circuit as claimed in any one of claims 1 to 9.