SOC board card integration backboard
By designing the SOC board and card integration backplane, the problem of limited number of SOC boards in the existing technology is solved, efficient management and high-density integration of SOC boards are realized, and the energy efficiency and cost-effectiveness of the system are improved.
Patent Information
- Application Number
- CN202420618800.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2034-03-28
AI Technical Summary
In the design of existing blade servers, the number of integrated SOC boards in the chassis is limited, and it is impossible to achieve high energy efficiency, cost-effectiveness, and high density.
Design a SOC board integrated backplane, which realizes unified management, debugging and screen projection of SOC boards by setting up 26 pairs of pins and specific interface connections, and achieves high-density integration through Gigabit Ethernet and 2.5G Ethernet connections.
It realizes efficient management and high-density integration of SOC boards, improves the energy efficiency and cost-effectiveness of the system, and integrates more SOC boards in one rack-mounted chassis.
Smart Images
Figure CN222801160U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of blade servers, in particular to a SOC board integrated backplane. Background Art
[0002] Blade server (to be more precise, it should be called blade server) refers to a server unit that can be plugged into a standard height rack chassis to achieve high availability and high density. It is a low-cost server platform of HAHD (High Availability High Density), which is specially designed for special application industries and high-density computer environments. Its main structure is a large main chassis, in which many "blades" can be plugged, and each "blade" is actually a system motherboard. They can start their own operating systems, such as Windows NT / 2000, Linux, etc. through the "onboard" hard disk, similar to independent servers. In this mode, each motherboard runs its own system and serves different designated user groups, and there is no connection between them. However, administrators can use system software to group these motherboards into a server cluster. In cluster mode, all motherboards can be connected to provide a high-speed network environment, and at the same time share resources to serve the same user group. By inserting a new "blade" into the cluster, the overall performance can be improved. And because each "blade" is hot-swappable, the system can be easily replaced and maintenance time is reduced to a minimum.
[0003] In the server field, products based on X86 architecture have always dominated. In recent years, with the continuous growth of downstream demand for heterogeneous computing power and intelligent computing power, as well as the large-scale rise of Android native ecological applications such as cloud games, such as "Genshin Impact" and "Honkai Impact". However, in supporting cloud games on traditional X86 servers, there are problems such as poor compatibility and high costs. However, on ARM architecture servers, based on the natural compatibility with the Android ecosystem, the software architecture conversion from the server side to the application side and the performance loss during the conversion process are avoided.
[0004] In the prior art, in the process of using blade servers, a SOC array server based on the ARM architecture and built with a flexible blade architecture is proposed, which supports a total of 4 blade nodes, and a single blade can accommodate 24 SOC boards. Based on the principles of high energy efficiency, high cost performance and high density, up to 96 SOC boards can be integrated in a rack chassis; therefore, we make improvements on this and propose a SOC board integrated backplane. Utility Model Content
[0005] The purpose of the utility model is to solve the problem that the number of SOC boards integrated in the chassis of the current blade server design is limited and high energy efficiency, high cost performance and high density cannot be achieved.
[0006] In order to achieve the above-mentioned utility model purpose, the utility model provides the following technical solutions:
[0007] A SOC card integrated backplane is provided to improve the above problems.
[0008] The specific application is as follows:
[0009] A SOC board integrated backplane, comprising a backplane body, a YSJ_RC_GF_52P CON4 is arranged at the upper end of the backplane body, 26 pairs of pins are welded on the backplane body, and the 26 pairs of pins are numbered A1-A26 and B1-B26, the 26 pairs of pins are arranged on the backplane body at equal intervals, and the pins A1-A26 and the pins B1-B26 are arranged in a mirror image, and the outer end of the pin A1 is connected to the USB_VBUS 5V signal, the pins A3, A4, A5, A6, and A7 are RX+ and TX+ of USB3.0, the pins A10, A11, A10, and A13 are connected to USB3.0 signals TX+ and TX-, the pin B4 is the IO pin of eFUSE_En, the pins B5, B6, B7, and B8 are connected to the Gigabit Ethernet MDI signal with the pins B10, B11, B12, and B13, the pins A14 and A29 are connected to the DEBUG_UART serial port signal, the pin A17 is the RCV board system restoration, the pin A18 is connected to the USB_Loader_EN_N forced download mode, the pin A23 is the system alarm status output, the pin A24 is the system operation status light, the pin A26 board physical insertion identification signal, the pins B15, B16, B18, B19, B21, B22, B24, and B25 are connected to the 2.5G Ethernet MDI signal.
[0010] As a preferred technical solution of the present application, the pins A3, A4, A5, A6, A7 are interconnected with the serial port of D124, the pins A3, A4, A5, A6, A7 are interconnected with RS25E1012C, and the pins A3, A4, A5, A6, A7 are used for flashing, debugging and screen projection of the SOC board.
[0011] As a preferred technical solution of the present application, the backplane body controls the power-on timing of 5V_VBUS and uses a maximum of 200mA in conjunction with a forced download mode enable signal.
[0012] As a preferred technical solution of the present application, the pins A3, A4, A5, A6, A7 and the pins A10, A11, A10, A13 are used for SOC board ADB debugging and flashing.
[0013] As a preferred technical solution of the present application, the pins B1, B2, and B3 are 12V power supply inputs, and the pins B1, B2, and B3 are welded into one large Pin to increase the through-current capacity.
[0014] As a preferred technical solution of the present application, the pin B4 enables the signal, which is high and effective. When effective, the 12V power supply is turned on.
[0015] As a preferred technical solution of the present application, the pin A14 and the pin A29 are used for board debugging.
[0016] As a preferred technical solution of the present application, the pin A17 is used for receiving a signal remote system recovery function, and is effective at a low level, and the pin A18 is effective at a low level, and defaults to a high level.
[0017] As the preferred technical solution of the present application, the pin A23 is used to output a high level to light up the red indicator light on the baseboard when the SOC board system operates abnormally, and the pin A24 is used to output a high level to light up the green indicator light on the baseboard when the SOC board system operates normally.
[0018] As a preferred technical solution of the present application, the pin A26 is used to be grounded on the SOC board, and the backplane body determines whether the SOC board is in place through this signal.
[0019] Compared with the prior art, the utility model has the following beneficial effects:
[0020] In the scheme of this application:
[0021] 1. Control all SOC boards, debugging, flashing and other management functions by setting the selected USB, which is convenient for the unified management of SOC boards.
[0022] 2. By setting up a Gigabit network for heartbeat communication with the Agent in the SOC board, all the status of the Android operating system can be obtained at any time.
[0023] 3. Set up a single serial port to communicate with all boards, and use switching to connect the SOC board and the projection screen.
[0024] 4. By setting multiple STATUS_LEDs and FAIL_LEDs, it is convenient to monitor the abnormal status and operating status of the SOC board. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1The overall circuit structure schematic diagram of a SOC board integrated backplane provided in this application;
[0026] Figure 2 This is a schematic diagram of the integrated backplane interface structure of a SOC board integrated backplane provided in this application. DETAILED DESCRIPTION
[0027] To make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be described clearly and completely in conjunction with the accompanying drawings. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments.
[0028] Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the present invention to be protected, but only represents some embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. It should be noted that the embodiments of the present invention and the features and technical solutions in the embodiments can be combined with each other without conflict.
[0029] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0030] like Figure 1-2As shown, this embodiment proposes a SOC board integrated backplane, including a backplane body, the upper end of the backplane body is provided with a CON4 of YSJ_RC_GF_52P, the backplane body is welded with 26 pairs of pins, and the 26 pairs of pins are numbered A1-A26 and B1-B26, the 26 pairs of pins are arranged on the backplane body at equal intervals, and the pins A1-A26 and the pins B1-B26 are arranged in a mirror image, and the outer end of the pin A1 is connected to the USB_VBUS 5V signal, the pins A3, A4, A5, A6, and A7 are RX+ and TX+ of USB3.0, the pins A10, A11, A10, and A13 are connected to USB3.0 signals TX+ and TX-, the pin B4 is the IO pin of eFUSE_En, the pins B5, B6, B7, and B8 are connected to the Gigabit Ethernet MDI signal with the pins B10, B11, B12, and B13, the pins A14 and A29 are connected to the DEBUG_UART serial port signal, the pin A17 is the RCV board system restoration, the pin A18 is connected to the USB_Loader_EN_N forced download mode, the pin A23 is the system alarm status output, the pin A24 is the system operation status light, the pin A26 board physical insertion identification signal, the pins B15, B16, B18, B19, B21, B22, B24, and B25 are connected to the 2.5G Ethernet MDI signal.
[0031] The backplane body controls the power-on timing of 5V_VBUS, and uses a maximum of 200mA in conjunction with the forced download mode enable signal. The pins A3, A4, A5, A6, A7 and pins A10, A11, A10, A13 are used for SOC board ADB debugging and flashing. The pins B1, B2, and B3 are 12V power supply inputs, and the pins of pins B1, B2, and B3 are welded into a large Pin to increase the pass-through capacity. The pin B4 enable signal is high effective, and the 12V power supply is turned on when it is effective. The pins A14 and A29 are used for board debugging. The pin A17 is used to receive the signal remote system recovery function, and the low level is effective. The pin A18 is effective at a low level and defaults to a high level. The pin A23 is used for the SOC board system to output a high level to light up the red indicator light on the bottom board when the operation is abnormal, and the pin A24 is used for the SOC board system to output a high level to light up the green indicator light on the bottom board when the operation is normal. The pin A26 is used to be grounded on the SOC board, and the backplane body determines whether the SOC board is in place through this signal.
[0032] A23 and A24 pins STATUS_LED and FAIL_LED are used to monitor the abnormal status and operating status of the SOC board.
[0033] The pins A3, A4, A5, A6, and A7 are interconnected with the serial port of D124, and the pins A3, A4, A5, A6, and A7 are interconnected with RS25E1012C. The pins A3, A4, A5, A6, and A7 are used for flashing, debugging, and screen projection of the SOC board. The pins A20 and A21 are respectively connected to the system reset input and the power on / off signal of the SOC board. A high level resets the SOC board. The default is a low level. A high level turns on the board, and a low level turns off the board.
[0034] When the present application is used: by applying the present device in the SOC board server, the pins B5, B6, B7, B8 and the pins B10, B11, B12, B13 Gigabit Ethernet MDI signals and B15, B16, B18, B19 and B21, B22, B24, B25 are respectively connected to the management system network and the 2.5G network of the external switch module. During operation, the enable signal at pin B4 is high effective. When effective, the 12V power supply is turned on, and the 12V power supply input is through pins B1, B2, B3, and the pins of pins B1, B2, B3 are welded as a large Pin, which can well increase the through-retention capacity. Pin A23 is used for When the SOC board system runs abnormally, it outputs a high level to light up the red indicator light on the bottom plate. Pin A24 is used to output a high level to light up the green indicator light on the bottom plate when the SOC board system runs normally. Pin A26 is used to ground the SOC board, and the backplane body uses this signal to determine whether the SOC board is in place. Pin A14 and pin A29 are used for board debugging. Pins A3, A4, A5, A6, and A7 are used for flashing, debugging, and screen projection of the SOC board. Pins A20 and A21 are connected to the system reset input and the power on / off signal of the SOC board respectively. A high level resets the SOC board, which facilitates the unified management of the SOC board and the timely monitoring of abnormalities.
[0035] The above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. Although the present invention has been described in detail with reference to the above embodiments, the present invention is not limited to the above specific implementation methods. Therefore, any modification or equivalent replacement of the present invention; and all technical solutions and improvements thereof that do not depart from the spirit and scope of the present invention are included in the scope of the claims of the present invention.
Claims
1. A SOC board integrated backplane, comprising a backplane body, characterized in that: The upper end of the backplane body is provided with CON4 of YSJ_RC_GF_52P. The backplane body is welded with 26 pairs of pins, and the 26 pairs of pins are numbered A1-A26 and B1-B26. The 26 pairs of pins are arranged on the backplane body at equal intervals, and the pins A1-A26 and the pins B1-B26 are arranged in a mirror image. The outer end of the pin A1 is connected to USB_VBUS 5V signal, the pins A3, A4, A5, A6, and A7 are RX+ and TX+ of USB3.0, the pins A10, A11, A10, and A13 are connected to USB3.0 signals TX+ and TX-, the pin B4 is the IO pin of eFUSE_En, the pins B5, B6, B7, and B8 are connected to the Gigabit Ethernet MDI signal with the pins B10, B11, B12, and B13, the pins A14 and A29 are connected to the DEBUG_UART serial port signal, the pin A17 is the RCV board system restoration, the pin A18 is connected to the USB_Loader_EN_N forced download mode, the pin A23 is the system alarm status output, the pin A24 is the system operation status light, the pin A26 board physical insertion identification signal, the pins B15, B16, B18, B19, B21, B22, B24, and B25 are connected to the 2.5G Ethernet MDI signal.
2. The SOC board integrated backplane according to claim 1, characterized in that: The pins A3, A4, A5, A6, A7 are interconnected with the serial port of D124, the pins A3, A4, A5, A6, A7 are interconnected with RS25E1012C, and the pins A3, A4, A5, A6, A7 are used for flashing, debugging and screen projection of the SOC board.
3. The SOC board integrated backplane according to claim 1, characterized in that: The backplane body controls the power-on timing of 5V_VBUS, and uses a maximum of 200mA in conjunction with the forced download mode enable signal.
4. The SOC board integrated backplane according to claim 1, characterized in that: The pins A3, A4, A5, A6, A7 and the pins A10, A11, A10, A13 are used for SOC board ADB debugging and flashing.
5. The SOC board integrated backplane according to claim 1, characterized in that: The pins B1, B2, and B3 are 12V power supply inputs, and the pins B1, B2, and B3 are welded into one large pin to increase the through-current capacity.
6. The SOC board integrated backplane according to claim 1, characterized in that: The pin B4 is an enable signal, which is valid at high level. When it is valid, the 12V power supply is turned on.
7. The SOC board integrated backplane according to claim 1, characterized in that: The pin A14 and the pin A29 are used for board debugging.
8. The SOC board integrated backplane according to claim 1, characterized in that: The pin A17 is used for receiving a signal remote system recovery function and is effective at a low level. The pin A18 is effective at a low level and is high by default.
9. The SOC board integrated backplane according to claim 1, characterized in that: The pin A23 is used to output a high level to light up the red indicator light on the baseboard when the SOC board system is running abnormally. The pin A24 is used to output a high level to light up the green indicator light on the baseboard when the SOC board system is running normally. The pin A26 is used to be grounded on the SOC board, and the backplane body determines whether the SOC board is in place through this signal.
10. The SOC board integrated backplane according to claim 1, characterized in that: The pins A20 and A21 are connected to the system reset input and the power on / off signal of the SOC board respectively.