Mode selection circuit, driving chip and display

Abstract

The utility model discloses a mode selection circuit, a driving chip and a display. According to the embodiment of the utility model, the mode selection circuit comprises a control end which is used for receiving a control signal; the first output channel is connected with the control end so as to receive the control signal and output a first signal according to the control signal; and the second output channel is connected with the control end to receive the control signal and output a second signal according to the control signal, and instruction information is generated according to the first signal and the second signal. According to the mode selection circuit, the driving chip and the display provided by the embodiment of the utility model, the structure is simple, a built-in register is not needed, and the chip production cost is saved.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and in particular to a mode selection circuit, a driving chip and a display. Background Art

[0002] The driver chip is an important component of the display panel and is used to control and drive the LED lights or other light sources on the display panel.

[0003] In the prior art, the driver chip is often a constant current driver chip. The constant current driver chip can ensure that the output current is not affected by power supply voltage fluctuations or load changes, and provide a constant current output, thereby improving the stability and performance of the system. For constant current driver chips for LED displays, if you want to achieve different current outputs, you need to design multiple different chips, or add built-in registers to the same driver chip, and use different configurations of the internal registers to enable the driver chip to output currents of different sizes. However, whether it is redesigning the driver chip or adding built-in registers, the solutions of the prior art will increase the production cost of the driver chip.

[0004] Therefore, it is hoped that there will be a new mode selection circuit, a driving chip and a display that can overcome the above problems. Utility Model Content

[0005] In view of the above problems, the purpose of the present utility model is to provide a mode selection circuit, a driver chip and a display, in particular, a circuit and a chip that realize different functions by changing the connection of chip pins (PAD) in an LED display driver chip, thereby simplifying the structure and reducing costs.

[0006] According to one aspect of the present invention, a mode selection circuit is provided, comprising:

[0007] A control terminal, the control terminal is used to receive a control signal;

[0008] a first output channel, the first output channel being connected to the control end to receive the control signal and outputting a first signal according to the control signal; and

[0009] a second output channel, the second output channel being connected to the control end to receive the control signal and outputting a second signal according to the control signal,

[0010] Wherein, instruction information is generated according to the first signal and the second signal.

[0011] Optionally, the mode selection circuit further includes:

[0012] a voltage clamping module, the voltage clamping module being connected to the control terminal and the input node respectively, and generating an input signal at the input node according to the control signal;

[0013] The first output channel comprises:

[0014] A first inverter unit, wherein the first inverter unit is connected to the input node to obtain the input signal; the input signal is processed by the first inverter unit to obtain a first inverted signal, and the first inverted signal is transmitted to the first node;

[0015] a first comparing unit, wherein the first comparing unit is connected to the first node to obtain the first inverted signal, and compares and outputs the first signal according to the first inverted signal;

[0016] The second output channel comprises:

[0017] A second inverter unit, wherein the second inverter unit is connected to the input node to obtain the input signal; the input signal is processed by the second inverter unit to obtain a second inverted signal, and the second inverted signal is transmitted to the second node;

[0018] a second comparing unit, wherein the second comparing unit is connected to the second node to obtain the second inverted signal, and outputs the second signal according to the comparison of the second inverted signal,

[0019] Among them, different control signals correspond to different instruction information, and different instruction information corresponds to different output modes.

[0020] Optionally, the control signal received by the control terminal includes at least one selected from a floating signal, a power supply voltage and a ground voltage;

[0021] A power supply voltage terminal is connected to the input node via the voltage clamp module, and a ground terminal is connected to the input node via the voltage clamp module;

[0022] The power supply voltage terminal is connected to the first comparison unit to provide the power supply voltage to the first comparison unit;

[0023] The ground terminal is connected to the second comparing unit to provide the ground voltage to the second comparing unit.

[0024] Wherein, when the control signal is the floating signal, the voltage value at the input node is determined according to the power supply voltage, the voltage value output by the first comparison unit is determined according to the ground voltage, and the voltage value output by the second comparison unit is determined according to the power supply voltage;

[0025] When the control signal is the power supply voltage, the voltage value at the input node is determined according to the power supply voltage, the voltage value output by the first comparison unit is determined according to the power supply voltage, and the voltage value output by the second comparison unit is determined according to the power supply voltage;

[0026] When the control signal is the ground voltage, the voltage value at the input node is determined according to the ground voltage, the voltage value output by the first comparison unit is determined according to the ground voltage, and the voltage value output by the second comparison unit is determined according to the ground voltage.

[0027] Optionally, a flip threshold of the first inverter unit is greater than half of the voltage value of the power supply voltage; a flip threshold of the second inverter unit is less than half of the voltage value of the power supply voltage.

[0028] Wherein, the flip threshold of the first inverter unit is determined according to the carrier mobility of the transistor in the first inverter unit and the width-to-length ratio of the transistor;

[0029] The flip threshold of the second inverter unit is determined according to the carrier mobility of the transistor in the second inverter unit and the width-to-length ratio of the transistor.

[0030] Optionally, the voltage clamping module includes:

[0031] a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage terminal, and a second terminal of the first transistor is connected to the control terminal,

[0032] A second transistor, wherein a first terminal of the second transistor is connected to the control terminal, and a second terminal of the second transistor is connected to the ground terminal.

[0033] Optionally, the first inverter unit includes:

[0034] a third transistor, wherein a control terminal of the third transistor is connected to the input node, and a second terminal of the third transistor is connected to the first node;

[0035] a fourth transistor, wherein a control terminal of the fourth transistor is connected to the input node, and a first terminal of the fourth transistor is connected to the first node;

[0036] The second inverter unit comprises:

[0037] a fifth transistor, wherein a control terminal of the fifth transistor is connected to the input node, and a second terminal of the fifth transistor is connected to the second node;

[0038] A sixth transistor, wherein a control terminal of the sixth transistor is connected to the input node, and a first terminal of the sixth transistor is connected to the second node.

[0039] Optionally, the first comparing unit includes:

[0040] a first output terminal, the first output terminal being used to output the first signal;

[0041] a seventh transistor, wherein a control terminal of the seventh transistor is used to receive a first bias voltage, and a second terminal of the seventh transistor is connected to the first output terminal;

[0042] an eighth transistor, wherein a control terminal of the eighth transistor is connected to the first node, and a first terminal of the eighth transistor is connected to the first output terminal;

[0043] The second comparison unit comprises:

[0044] a second output terminal, the second output terminal being used to output the second signal;

[0045] a ninth transistor, wherein a control terminal of the ninth transistor is connected to the second node, and a second terminal of the ninth transistor is connected to the second output terminal;

[0046] A tenth transistor, wherein the control terminal of the tenth transistor is used to receive a second bias voltage, and the first terminal of the tenth transistor is connected to the second output terminal.

[0047] Optionally, the mode selection circuit includes:

[0048] a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage terminal, a second terminal of the first transistor is connected to the control terminal, and the control terminal of the first transistor is connected to the second terminal of the first transistor;

[0049] a second transistor, wherein a first end of the second transistor is connected to the control end, a second end of the second transistor is connected to a ground end, and a control end of the second transistor is connected to the first end of the second transistor;

[0050] an input node, the input node being connected to the second end of the first transistor and the first end of the second transistor respectively;

[0051] a third transistor, wherein a first terminal of the third transistor is connected to the power supply voltage terminal, and a control terminal of the third transistor is connected to the input node;

[0052] a fourth transistor, wherein a second terminal of the fourth transistor is connected to the ground terminal, and a control terminal of the fourth transistor is connected to the input node;

[0053] a first node connected to the second end of the third transistor and the first end of the fourth transistor respectively;

[0054] a fifth transistor, wherein a first terminal of the fifth transistor is connected to the power supply voltage terminal, and a control terminal of the fifth transistor is connected to the input node;

[0055] a sixth transistor, wherein a second terminal of the sixth transistor is connected to the ground terminal, and a control terminal of the sixth transistor is connected to the input node;

[0056] a second node connected to the second end of the fifth transistor and the first end of the sixth transistor respectively;

[0057] a seventh transistor, wherein a first terminal of the seventh transistor is connected to the power supply voltage terminal, a second terminal of the seventh transistor is connected to the first output terminal, and a control terminal of the seventh transistor is connected to the first bias voltage terminal to receive a first bias voltage;

[0058] an eighth transistor, wherein a first terminal of the eighth transistor is connected to the first output terminal, a second terminal of the eighth transistor is connected to the ground terminal, and a control terminal of the eighth transistor is connected to the first node;

[0059] a ninth transistor, wherein a first terminal of the ninth transistor is connected to the power supply voltage terminal, a second terminal of the ninth transistor is connected to the second output terminal, and a control terminal of the ninth transistor is connected to the second node;

[0060] A tenth transistor, wherein a first terminal of the tenth transistor is connected to the second output terminal, a second terminal of the tenth transistor is connected to the ground terminal, and a control terminal of the tenth transistor is connected to the second bias voltage terminal to receive a second bias voltage.

[0061] According to another aspect of the present invention, a driver chip is provided, comprising:

[0062] A mode selection circuit as described above; and

[0063] A driving circuit is connected to the mode selection circuit to receive the instruction information and output a driving signal according to an output mode corresponding to the instruction information.

[0064] According to another aspect of the present invention, there is provided a display, comprising:

[0065] display panel; and

[0066] The driving chip as described above is connected to the display panel to drive the display panel.

[0067] Optionally, the display panel is at least one selected from a sub-millimeter diode light-emitting display panel, a micron diode light-emitting display panel and a quantum dot diode light-emitting display panel.

[0068] The mode selection circuit, driving chip and display provided by the embodiment of the utility model can obtain instruction information corresponding to different output modes according to the control signal of the control end, have a simple structure, do not need built-in registers, and save chip production costs.

[0069] Furthermore, one control signal corresponds to two output channels, and two signal outputs are obtained. The two signal outputs are directly used as instruction information for selecting an output mode. The control method is simple and there is no need to add registers or redesign circuits.

[0070] Furthermore, the setting of the flip threshold of the inverter unit ensures that a control signal can accurately realize the selection of the output mode, and the circuit is efficient and reliable.

[0071] Furthermore, the pins / pads of the driver chip can be used as control terminals, and the rest of the mode selection circuit can be packaged in the driver chip. The output mode selection of the packaged chip can be achieved through pin control, thereby enhancing the applicability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0073] Figure 1 A schematic diagram of the structure of a mode selection circuit according to Embodiment 1 of the present utility model is shown;

[0074] Figure 2 A schematic diagram showing the structure of a mode selection circuit according to a second embodiment of the present utility model is shown;

[0075] Figure 3 A schematic diagram of the structure of a mode selection circuit according to Embodiment 3 of the present utility model is shown;

[0076] Figure 4 A circuit diagram of a mode selection circuit according to a fourth embodiment of the present utility model is shown. DETAILED DESCRIPTION

[0077] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0078] The specific implementation of the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. Many specific details of the utility model are described below, such as the structure, material, size, processing technology and technology of the components, so as to more clearly understand the utility model. However, as those skilled in the art can understand, the utility model can be implemented without following these specific details.

[0079] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0080] Figure 1 FIG. 1 shows a schematic diagram of the structure of a mode selection circuit according to Embodiment 1 of the present utility model. Figure 1 As shown, the mode selection circuit according to the first embodiment of the present invention includes a control terminal 300 , a first output channel 100 and a second output channel 200 .

[0081] Specifically, the control terminal 300 is used to receive a control signal.

[0082] The first output channel 100 is connected to the control terminal 300 to receive a control signal, and outputs a first signal (VOUT1) according to the control signal.

[0083] The second output channel 200 is connected to the control terminal 300 to receive a control signal, and outputs a second signal (VOUT2) according to the control signal.

[0084] The instruction information is generated according to the first signal and the second signal. Optionally, different instruction information corresponds to different output modes; different control signals correspond to different instruction information. The instruction information is, for example, information about the instruction executed by the chip, which may be an operand in binary form, and the first signal and the second signal constitute the operand.

[0085] Alternatively, if Figure 1 As further shown in FIG. 1 , the first output channel 100 includes a first inverter unit 110 and a first comparison unit 120 , and the second output channel 200 includes a second inverter unit 210 and a second comparison unit 220 .

[0086] The first inverter unit 110 obtains a first inverted signal according to a control signal provided by the control terminal 300, and the first inverted signal is transmitted to the first node Vb. The first comparison unit 120 is connected to the first node Vb to obtain the first inverted signal, and compares and outputs a first signal according to the first inverted signal.

[0087] The second inverter unit 210 obtains a second inverted signal according to the control signal provided by the control terminal 300, and the second inverted signal is transmitted to the second node Vc. The second comparison unit 220 is connected to the second node Vc to obtain the second inverted signal, and compares and outputs the second signal according to the second inverted signal.

[0088] In an optional embodiment of the utility model, the mode selection circuit is, for example, used for a chip or is a part of a chip. Optionally, the mode selection circuit is at least a part of a display driver chip, and the control terminal 300 is a pin / pad of the display driver chip. Optionally, when the mode selection circuit is applied to an LED display driver chip, different output modes are different constant current drives. The pin / pad of the driver chip can be used as a control terminal, and the rest of the mode selection circuit can be packaged in the driver chip, and the output mode selection of the packaged chip can be realized by pin control. For a driver chip that applies this mode selection circuit, it can adapt to a variety of different output requirements, and there is no need to design different types of chips for different requirements.

[0089] Figure 2 FIG. 2 shows a schematic diagram of the structure of a mode selection circuit according to Embodiment 2 of the present utility model. Figure 2 As shown, the mode selection circuit according to the second embodiment of the present utility model includes a control terminal 300 , a voltage clamping module 400 , a first output channel 100 and a second output channel 200 .

[0090] Specifically, the voltage clamp module 400 is connected to the control terminal 300 and the input node Va, respectively. The voltage clamp module 400 is connected to the control terminal 300 to receive a control signal, and generates an input signal at the input node Va according to the control signal. Optionally, a part of the voltage clamp module 400 belongs to the first output channel 100, and a part belongs to the second output channel 200.

[0091] The first inverter unit 110 is connected to the input node Va to obtain an input signal. The input signal is processed by the first inverter unit 110 to obtain a first inverted signal, which is transmitted to the first node Vb.

[0092] The first comparison unit 120 is connected to the first node Vb to obtain the first inverted signal, and compares and outputs a first signal according to the first inverted signal.

[0093] The second inverter unit 210 is connected to the input node Va to obtain the input signal; the input signal is processed by the second inverter unit 210 to obtain a second inverted signal, and the second inverted signal is transmitted to the second node Vc.

[0094] The second comparison unit 220 is connected to the second node Vc to obtain the second inverted signal, and outputs the second signal according to the comparison of the second inverted signal.

[0095] Figure 3 FIG. 2 shows a schematic diagram of the structure of a mode selection circuit according to Embodiment 3 of the present utility model. Figure 3 As shown, based on the second embodiment, the voltage clamping module 400, the first inverter unit 110 and the first comparison unit 120 are respectively connected to the power supply voltage terminal (VDD), and the voltage clamping module 400, the first inverter unit 110 and the first comparison unit 120 are respectively connected to the ground terminal (VSS). The power supply voltage terminal (VDD) provides a power supply voltage, for example, and the ground terminal (VSS) provides a ground voltage, for example.

[0096] Specifically, the control signal received by the control terminal 300 includes at least one selected from a floating signal, a power supply voltage and a ground voltage. Optionally, the power supply voltage received by the control terminal 300 is provided by the power supply voltage terminal (VDD), and the ground voltage received by the control terminal 300 is provided by the ground terminal (VSS).

[0097] The power supply voltage terminal is connected to the input node Va via the voltage clamp module 400 , and the ground terminal is connected to the input node Va via the voltage clamp module 400 .

[0098] The power voltage terminal is connected to the first inverter unit 110 to provide a power voltage to the first inverter unit 110 .

[0099] The ground terminal is connected to the second inverter unit 210 to provide a ground voltage to the second inverter unit 210 .

[0100] The power supply voltage terminal is connected to the first comparing unit 120 to provide a power supply voltage to the first comparing unit 120 .

[0101] The ground terminal is connected to the second comparing unit 220 to provide a ground voltage to the second comparing unit 220 .

[0102] When the control signal is a floating signal, the voltage value at the input node Va is determined according to the power supply voltage, the voltage value compared and output by the first comparison unit 120 is determined according to the ground voltage, and the voltage value compared and output by the second comparison unit 220 is determined according to the power supply voltage. In a specific embodiment, the voltage value at the input node Va is half of the voltage value of the power supply voltage. The voltage value compared and output by the first comparison unit 120 is the voltage value of the ground voltage, and the voltage value compared and output by the second comparison unit 220 is the voltage value of the power supply voltage. When the control signal is the power supply voltage, the voltage value at the input node Va is determined according to the power supply voltage, the voltage value compared and output by the first comparison unit 120 is determined according to the power supply voltage, and the voltage value compared and output by the second comparison unit 220 is determined according to the power supply voltage. In a specific embodiment, the voltage value at the input node Va is the voltage value of the power supply voltage, the voltage value compared and output by the first comparison unit 120 is the voltage value of the power supply voltage, and the voltage value compared and output by the second comparison unit 220 is the voltage value of the power supply voltage.

[0103] When the control signal is a ground voltage, the voltage value at the input node Va is determined according to the ground voltage, the voltage value compared and output by the first comparison unit 120 is determined according to the ground voltage, and the voltage value compared and output by the second comparison unit 220 is determined according to the ground voltage. In a specific embodiment, the voltage value at the input node Va is the voltage value of the ground voltage, the voltage value compared and output by the first comparison unit 120 is the voltage value of the ground voltage, and the voltage value compared and output by the second comparison unit 120 is the voltage value of the ground voltage.

[0104] According to the mode selection circuit of the embodiment of the utility model, it is applied to a (drive) chip, for example, a pad / pin selection circuit in a constant current drive chip. For the same chip, different packaging schemes, that is, different connections of pads / pins are used to implement different control signals to output different currents. The present application proposes a new pad / pin selection circuit, which includes a voltage clamping module, two inverter units, and two comparison units; before the chip is packaged, a current setting welding operation is performed, that is, the pad / pin is floated (floating), electrically connected to VDD by welding, and electrically connected to VSS by welding. Corresponding to these three connection conditions, the values ​​generated by the first signal (VOUT1) and the second signal (VOUT2) are 01, 11, and 00, respectively. Three instruction signals, and then three current outputs are realized through three instruction signals. The circuit architecture of the present application can realize three control signals, without the need to design three chips separately, and without built-in register control, which can effectively save chip production costs.

[0105] In an optional embodiment of the present invention, the flip threshold of the first inverter unit 110 is greater than half of the voltage value of the power supply voltage; the flip threshold of the second inverter unit 210 is less than half of the voltage value of the power supply voltage. The flip threshold of the first inverter unit 110 is determined according to the carrier mobility of the transistor in the first inverter unit 110 and the width-to-length ratio of the transistor; the flip threshold of the second inverter unit 210 is determined according to the carrier mobility of the transistor in the second inverter unit 210 and the width-to-length ratio of the transistor.

[0106] Figure 4 FIG. 4 shows a circuit diagram of a mode selection circuit according to a fourth embodiment of the present utility model. Figure 4 As shown, the mode selection circuit according to the fourth embodiment of the utility model includes a first transistor PCH1, a second transistor NCH1, a third transistor PCH2, a fourth transistor NCH2, a fifth transistor PCH3, a sixth transistor NCH3, a seventh transistor PCH4, an eighth transistor NCH4, a ninth transistor PCH5 and a tenth transistor NCH5. Optionally, PCH represents a PMOS transistor, and NCH represents an NMOS transistor; PCH (P-Channel High-Side MOSFET) refers to, for example, a P-channel high-side MOSFET used in a high-side switch circuit.

[0107] Combination Figure 3 and Figure 4 As shown, the voltage clamp module 400 includes a first transistor PCH1 and a second transistor NCH1. The first end of the first transistor PCH1 is connected to the power supply voltage end, and the second end of the first transistor PCH1 is connected to the control end 300. The first end of the second transistor NCH1 is connected to the control end 300, and the second end of the second transistor NCH1 is connected to the ground end.

[0108] The first inverter unit 110 includes a third transistor PCH2 and a fourth transistor NCH2. The control end of the third transistor PCH2 is connected to the input node Va, and the second end of the third transistor PCH2 is connected to the first node Vb. The control end of the fourth transistor NCH2 is connected to the input node Va, and the first end of the fourth transistor NCH2 is connected to the first node Vb.

[0109] The second inverter unit 210 includes a fifth transistor PCH3 and a sixth transistor NCH3. The control end of the fifth transistor PCH3 is connected to the input node Va, and the second end of the fifth transistor PCH3 is connected to the second node Vc. The control end of the sixth transistor NCH3 is connected to the input node Va, and the first end of the sixth transistor NCH3 is connected to the second node Vc.

[0110] The first comparison unit 120 includes a first output terminal (VOUT1), a seventh transistor PCH4 and an eighth transistor NCH4. The first output terminal is used to output a first signal. The control terminal of the seventh transistor PCH4 is used to receive a first bias voltage (VBP), and the second terminal of the seventh transistor PCH4 is connected to the first output terminal. The control terminal of the eighth transistor NCH4 is connected to the first node Vb, and the first terminal of the eighth transistor NCH4 is connected to the first output terminal.

[0111] The second comparison unit 220 includes a second output terminal (VOUT2), a ninth transistor PCH5 and a tenth transistor NCH5. The second output terminal is used to output a second signal. The control terminal of the ninth transistor PCH5 is connected to the second node Vb, and the second terminal of the ninth transistor PCH5 is connected to the second output terminal. The control terminal of the tenth transistor NCH5 is used to receive a second bias voltage (VBN), and the first terminal of the tenth transistor NCH5 is connected to the second output terminal.

[0112] Combination Figure 4 As shown, in a specific embodiment of the present invention, the mode selection circuit includes first to tenth transistors and an input node Va, a first node Vb and a second node Vc.

[0113] Specifically, a first terminal of the first transistor PCH1 is connected to the power supply voltage terminal (VDD), a second terminal of the first transistor PCH1 is connected to the control terminal 300, and a control terminal of the first transistor PCH1 is connected to the second terminal of the first transistor PCH1.

[0114] A first terminal of the second transistor NCH1 is connected to the control terminal 300 , a second terminal of the second transistor NCH1 is connected to the ground terminal (VSS), and a control terminal of the second transistor NCH1 is connected to the first terminal of the second transistor NCH1 .

[0115] The input node Va is connected to the second end of the first transistor PCH1 and the first end of the second transistor NCH1, respectively.

[0116] A first terminal of the third transistor PCH2 is connected to the power supply voltage terminal, and a control terminal of the third transistor PCH2 is connected to the input node Va.

[0117] A second terminal of the fourth transistor NCH2 is connected to the ground terminal, and a control terminal of the fourth transistor NCH2 is connected to the input node Va.

[0118] The first node Vb is connected to the second end of the third transistor PCH2 and the first end of the fourth transistor NCH2, respectively.

[0119] A first terminal of the fifth transistor PCH3 is connected to the power supply voltage terminal, and a control terminal of the fifth transistor PCH3 is connected to the input node Va.

[0120] A second terminal of the sixth transistor NCH3 is connected to the ground terminal, and a control terminal of the sixth transistor NCH3 is connected to the input node Va.

[0121] The second node Vb is connected to the second end of the fifth transistor PCH3 and the first end of the sixth transistor NCH3, respectively.

[0122] A first end of the seventh transistor PCH4 is connected to the power supply voltage end, a second end of the seventh transistor PCH4 is connected to the first output end (VOUT1), and a control end of the seventh transistor PCH4 is connected to the first bias voltage end (VBP end) to receive the first bias voltage (VBP).

[0123] A first terminal of the eighth transistor NCH4 is connected to the first output terminal, a second terminal of the eighth transistor NCH1 is connected to the ground terminal, and a control terminal of the eighth transistor NCH4 is connected to the first node Vb.

[0124] A first terminal of the ninth transistor PCH5 is connected to the power supply voltage terminal, a second terminal of the ninth transistor PCH5 is connected to the second output terminal (VOUT2), and a control terminal of the ninth transistor PCH5 is connected to the second node Vb.

[0125] A first terminal of the tenth transistor NCH5 is connected to the second output terminal, a second terminal of the tenth transistor NCH5 is connected to the ground terminal, and a control terminal of the tenth transistor NCH5 is connected to the second bias voltage terminal (VBN terminal) to receive the second bias voltage (VBN).

[0126] In this specific embodiment of the present application, PCH1 and NCH1 form a voltage clamp unit, PCH2, NCH2, PCH3, and NCH3 form two groups of inverter units, and PCH4, NCH4, PCH5, and NCH5 form two groups of (current) comparison units. VBP and VBN are constant current bias voltages, and the output current of PCH4 is compared with the output current of NCH4. When Vb=VDD, the NCH4 current is greater than the PCH4 current, and VOUT1=VSS at this time; when Vb=VSS, the NCH4 current is less than the PCH4 current, and VOUT1=VDD at this time. The current comparison method of PCH5 and NCH5 is the same.

[0127] The specific process is as follows: when the control terminal 300 is left floating, the Va node voltage is obtained by dividing the voltages of PCH1 and NCH1, and the Va node voltage is VDD / 2. PCH2 and NCH2 form an inverter unit. By changing the width-to-length ratio of PCH2 and NCH2, the flip threshold (of the inverter unit) is changed so that when Va=VDD / 2, PCH2 drives Vb=VDD. After passing through the comparison unit (current selection circuit) composed of PCH4 and NCH4, because the gate voltage Vb of NCH4 is VDD, NCH4 drives the VOUT1 node to make VOUT1=0. Similarly, VOUT2=1.

[0128] When the control terminal 300 is connected to VDD, Va=VDD, and after passing through the inverter unit composed of PCH2 and NCH2, Vb=VSS. The VSS voltage turns off NCH4, and PCH4 drives the VOUT1 node to make VOUT1=1. Similarly, VOUT2=1.

[0129] When the control terminal 300 is connected to VSS, Va=VSS, and through the inverter unit composed of PCH2 and NCH2, Vb=VDD, and NCH4 drives the VOUT1 node to make VOUT1=0. Similarly, VOUT2=0.

[0130] Optionally, when designing an inverter unit composed of PCH2 and NCH2, it is necessary to ensure that the flip threshold VM of the inverter unit is greater than VDD / 2, where VM is expressed as follows:

[0131]

[0132]

[0133] Among them, μ p is the carrier mobility of PMOS, μ n is the carrier mobility of NMOS, is the width-to-length ratio of PMOS, is the width-to-length ratio of NMOS; when r=1, VM=VDD / 2, so increasing the width-to-length ratio of PCH2 or reducing the width-to-length ratio of NCH2 can achieve VM>VDD / 2. Similarly, when designing the inverter unit composed of PCH3 and NCH3, the width-to-length ratio of PCH3 will be reduced or the width-to-length ratio of NCH3 will be increased to achieve VM <VDD / 2。

[0134] According to another aspect of the present invention, a (display) driver chip is provided. The driver chip includes the mode selection circuit and the driver circuit as described above. The driver circuit is connected to the mode selection circuit to receive instruction information and output a drive signal according to an output mode corresponding to the instruction information.

[0135] According to another aspect of the utility model, a display is provided. The display comprises a display panel and a (display) driver chip as described above. The driver chip is connected to the display panel to drive the display panel. Optionally, the display panel is at least one selected from a sub-millimeter diode light-emitting display panel, a micron diode light-emitting display panel, and a quantum dot diode light-emitting display panel.

[0136] When used, the mode selection circuit according to the embodiment of the utility model comprises the following steps:

[0137] Step 1: Get the control signal;

[0138] The control signal is obtained via the control terminal. The obtained control signal is, for example, at least one selected from a floating signal, a power supply voltage, and a ground voltage.

[0139] Step 2: outputting a first signal via a first output channel according to the control signal;

[0140] The first output channel outputs a first signal according to the acquired control signal.

[0141] Step 3: outputting a second signal via a second output channel according to the control signal;

[0142] The second output channel outputs a second signal according to the acquired control signal.

[0143] Step 4: Generate instruction information according to the first signal and the second signal,

[0144] The command information is generated according to the first signal and the second signal, wherein different control signals correspond to different command information; and different command information corresponds to different output modes.

[0145] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0146] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A mode selection circuit, comprising: A control terminal, the control terminal is used to receive a control signal; a first output channel, the first output channel being connected to the control end to receive the control signal and outputting a first signal according to the control signal; as well as a second output channel, the second output channel being connected to the control end to receive the control signal and outputting a second signal according to the control signal, Wherein, instruction information is generated according to the first signal and the second signal.

2. The mode selection circuit according to claim 1, wherein: The mode selection circuit also includes: a voltage clamping module, the voltage clamping module being connected to the control terminal and the input node respectively, and generating an input signal at the input node according to the control signal; The first output channel comprises: A first inverter unit, wherein the first inverter unit is connected to the input node to obtain the input signal; the input signal is processed by the first inverter unit to obtain a first inverted signal, and the first inverted signal is transmitted to the first node; a first comparing unit, wherein the first comparing unit is connected to the first node to obtain the first inverted signal, and compares and outputs the first signal according to the first inverted signal; The second output channel comprises: A second inverter unit, wherein the second inverter unit is connected to the input node to obtain the input signal; the input signal is processed by the second inverter unit to obtain a second inverted signal, and the second inverted signal is transmitted to the second node; a second comparing unit, wherein the second comparing unit is connected to the second node to obtain the second inverted signal, and outputs the second signal according to the comparison of the second inverted signal, Among them, different control signals correspond to different instruction information, and different instruction information corresponds to different output modes.

3. The mode selection circuit according to claim 2, wherein: The control signal received by the control terminal includes at least one selected from a floating signal, a power supply voltage and a ground voltage; A power supply voltage terminal is connected to the input node via the voltage clamp module, and a ground terminal is connected to the input node via the voltage clamp module; The power supply voltage terminal is connected to the first comparison unit to provide the power supply voltage to the first comparison unit; The ground terminal is connected to the second comparing unit to provide the ground voltage to the second comparing unit. Wherein, when the control signal is the floating signal, the voltage value at the input node is determined according to the power supply voltage, the voltage value output by the first comparison unit is determined according to the ground voltage, and the voltage value output by the second comparison unit is determined according to the power supply voltage; When the control signal is the power supply voltage, the voltage value at the input node is determined according to the power supply voltage, the voltage value output by the first comparison unit is determined according to the power supply voltage, and the voltage value output by the second comparison unit is determined according to the power supply voltage; When the control signal is the ground voltage, the voltage value at the input node is determined according to the ground voltage, the voltage value output by the first comparison unit is determined according to the ground voltage, and the voltage value output by the second comparison unit is determined according to the ground voltage.

4. The mode selection circuit according to claim 3, wherein: The flip threshold of the first inverter unit is greater than half of the voltage value of the power supply voltage; the flip threshold of the second inverter unit is less than half of the voltage value of the power supply voltage, Wherein, the flip threshold of the first inverter unit is determined according to the carrier mobility of the transistor in the first inverter unit and the width-to-length ratio of the transistor; The flip threshold of the second inverter unit is determined according to the carrier mobility of the transistor in the second inverter unit and the width-to-length ratio of the transistor.

5. The mode selection circuit according to claim 2, wherein: The voltage clamping module comprises: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage terminal, and a second terminal of the first transistor is connected to the control terminal, A second transistor, wherein a first terminal of the second transistor is connected to the control terminal, and a second terminal of the second transistor is connected to the ground terminal.

6. The mode selection circuit according to claim 2, wherein: The first inverter unit comprises: a third transistor, wherein a control terminal of the third transistor is connected to the input node, and a second terminal of the third transistor is connected to the first node; a fourth transistor, wherein a control terminal of the fourth transistor is connected to the input node, and a first terminal of the fourth transistor is connected to the first node; The second inverter unit comprises: a fifth transistor, wherein a control terminal of the fifth transistor is connected to the input node, and a second terminal of the fifth transistor is connected to the second node; A sixth transistor, wherein a control terminal of the sixth transistor is connected to the input node, and a first terminal of the sixth transistor is connected to the second node.

7. The mode selection circuit according to claim 2, wherein: The first comparison unit comprises: a first output terminal, the first output terminal being used to output the first signal; a seventh transistor, wherein a control terminal of the seventh transistor is used to receive a first bias voltage, and a second terminal of the seventh transistor is connected to the first output terminal; an eighth transistor, wherein a control terminal of the eighth transistor is connected to the first node, and a first terminal of the eighth transistor is connected to the first output terminal; The second comparison unit comprises: a second output terminal, the second output terminal being used to output the second signal; a ninth transistor, wherein a control terminal of the ninth transistor is connected to the second node, and a second terminal of the ninth transistor is connected to the second output terminal; A tenth transistor, wherein the control terminal of the tenth transistor is used to receive a second bias voltage, and the first terminal of the tenth transistor is connected to the second output terminal.

8. The mode selection circuit according to claim 1, wherein: The mode selection circuit comprises: a first transistor, wherein a first terminal of the first transistor is connected to a power supply voltage terminal, a second terminal of the first transistor is connected to the control terminal, and the control terminal of the first transistor is connected to the second terminal of the first transistor; a second transistor, wherein a first end of the second transistor is connected to the control end, a second end of the second transistor is connected to a ground end, and a control end of the second transistor is connected to the first end of the second transistor; an input node, the input node being connected to the second end of the first transistor and the first end of the second transistor respectively; a third transistor, wherein a first terminal of the third transistor is connected to the power supply voltage terminal, and a control terminal of the third transistor is connected to the input node; a fourth transistor, wherein a second terminal of the fourth transistor is connected to the ground terminal, and a control terminal of the fourth transistor is connected to the input node; a first node connected to the second end of the third transistor and the first end of the fourth transistor respectively; a fifth transistor, wherein a first terminal of the fifth transistor is connected to the power supply voltage terminal, and a control terminal of the fifth transistor is connected to the input node; a sixth transistor, wherein a second terminal of the sixth transistor is connected to the ground terminal, and a control terminal of the sixth transistor is connected to the input node; a second node connected to the second end of the fifth transistor and the first end of the sixth transistor respectively; a seventh transistor, wherein a first terminal of the seventh transistor is connected to the power supply voltage terminal, a second terminal of the seventh transistor is connected to the first output terminal, and a control terminal of the seventh transistor is connected to the first bias voltage terminal to receive a first bias voltage; an eighth transistor, wherein a first terminal of the eighth transistor is connected to the first output terminal, a second terminal of the eighth transistor is connected to the ground terminal, and a control terminal of the eighth transistor is connected to the first node; a ninth transistor, wherein a first terminal of the ninth transistor is connected to the power supply voltage terminal, a second terminal of the ninth transistor is connected to the second output terminal, and a control terminal of the ninth transistor is connected to the second node; A tenth transistor, wherein a first terminal of the tenth transistor is connected to the second output terminal, a second terminal of the tenth transistor is connected to the ground terminal, and a control terminal of the tenth transistor is connected to the second bias voltage terminal to receive a second bias voltage.

9. A driver chip, comprising: The mode selection circuit according to any one of claims 1 to 8; as well as A driving circuit is connected to the mode selection circuit to receive the instruction information and output a driving signal according to an output mode corresponding to the instruction information.

10. A display comprising: Display panel; as well as The driving chip as claimed in claim 9, wherein the driving chip is connected to the display panel to drive the display panel.

11. The display according to claim 10, wherein: The display panel is at least one selected from a sub-millimeter diode light-emitting display panel, a micron diode light-emitting display panel and a quantum dot diode light-emitting display panel.

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