Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device, which are used for a special-shaped display screen and comprise a plurality of gate lines, the gate lines are electrically connected with the gates of the transistors of the corresponding pixel units respectively; the gate lines penetrate through a frame area of a Notch area at the top of the special-shaped display screen, and the gate line parts in the Notch area are located on different metal layers. According to the display device, the gate lines are manufactured by adopting different metal layer wiring in the frame area of the Notch area of the display device, so that the distance of the staggered gate lines in the frame area of the Notch area can be designed to be shorter, short circuit is avoided, the frame can be narrower, the effective display area is increased, and the display quality is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of display devices, and in particular to an array substrate and a display device. Background Art

[0002] Flat display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used. However, the shapes of existing display screens are becoming more and more diverse, such as the notch screen and water drop screen in the full screen that pursues screen-to-body ratio. The development idea of ​​this type of display screen is to dig a hole in the screen, place the front camera, and hide the camera module in the panel. The in-plane hole technology came into being. It will enlarge the effective display area and increase the screen-to-body ratio of the display. For example, the blind hole screen that pursues function sacrifices part of the screen-to-body ratio in order to make a certain performance stronger.

[0003] With the development of panel technology, narrow-border display panels that pursue a larger screen-to-body ratio have gradually become mainstream, and are moving towards borderless display. Currently, the borderless display panels on the market have a narrow black outer border on the periphery, under which the display driver circuit such as GIP (Gate Driver In Panel) is distributed.

[0004] The gate wiring in the top Notch area of ​​the irregular screen uses the same layer of metal, namely the Gate layer metal (M1 metal). If the space in the irregular area is too small, the gate wiring may not be able to fit in, and the pixels in the effective display area AA can only be sacrificed, that is, the pixels are reduced to make room for the gate wiring in the top Notch area. Utility Model Content

[0005] In the existing special-shaped display screen, the special-shaped area sacrifices the pixels in the effective display area for placing the gate lines, thereby reducing the display effect.

[0006] In view of the above problems, an array substrate and a display device are proposed, in which the gate lines are made of different metal layers in the border area of ​​the Notch area of ​​the display device, so that the distance between the staggered gate lines in the border area of ​​the Notch area can be designed to be shorter without short circuit, thereby making the border narrower, increasing the effective display area, and improving the display quality.

[0007] In a first aspect, an array substrate is provided for a special-shaped display screen, comprising:

[0008] a plurality of gate lines;

[0009] The gate lines are electrically connected to the gates of the transistors of the corresponding pixel units respectively;

[0010] The gate line passes through the border area of ​​the top Notch area of ​​the special-shaped display screen, and the gate line portion in the Notch area is in a different metal layer.

[0011] In combination with the array substrate of the present utility model, in a first possible implementation manner, the gate line includes:

[0012] a first gate line;

[0013] a second gate line;

[0014] The first gate line and the second gate line are arranged in an interlaced manner; a frame portion of the first gate line and a frame portion of the second gate line are arranged in different metal layers.

[0015] In combination with the first possible implementation manner of the utility model, in a second possible implementation manner, the first gate line includes:

[0016] a first display unit;

[0017] a first frame portion;

[0018] The first display portion and the first frame portion are formed by manufacturing a metal pattern on a gate metal layer.

[0019] In combination with the second possible implementation manner of the utility model, in a third possible implementation manner, the second gate line includes:

[0020] a second display unit;

[0021] a second frame portion;

[0022] First via;

[0023] The second display portion is formed by making a metal pattern on a gate metal layer;

[0024] The second frame portion is formed by making a metal pattern on the SD layer;

[0025] The second display portion and the second frame portion are overlapped through a first via hole.

[0026] In combination with the third possible implementation manner of the utility model, in a fourth possible implementation manner, the second gate line further includes:

[0027] a third display unit;

[0028] Second via;

[0029] The third display portion is formed by making a metal pattern on the gate metal layer;

[0030] The second frame portion and the third display portion are overlapped through a second via hole.

[0031] In combination with the fourth possible implementation manner of the utility model, in a fifth possible implementation manner, the staggered arrangement of the first gate lines and the second gate lines shrinks from both ends to the middle frame portion.

[0032] In a second aspect, a display device adopts the array substrate described in the first aspect.

[0033] By implementing the array substrate and display device described in the utility model, the gate lines are made of different metal layers in the frame area of ​​the Notch area of ​​the display device, so that the distance between the staggered gate lines in the frame area of ​​the Notch area can be designed to be shorter without short circuit, thereby making the frame narrower, increasing the effective display area, and improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of the gate line wiring of the array substrate in this application;

[0036] Figure 2 A schematic diagram of the gate line wiring in the Notch border area of ​​the array substrate in this application;

[0037] Figure 3 It is a partially enlarged schematic diagram of the gate line wiring in the Notch border area of ​​the array substrate in the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the utility model to clearly and completely describe the technical solution in the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the utility model.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0041] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] In the existing special-shaped display screen, the special-shaped area sacrifices the pixels in the effective display area for placing the gate lines, thereby reducing the display effect.

[0044] In view of the above problems, an array substrate and a display device are proposed.

[0045] In a first aspect, an array substrate, such as Figure 1 , Figure 1 The present invention is a schematic diagram of the gate line wiring of the array substrate in the present application; it is used for a special-shaped display screen, and includes a plurality of gate lines; the gate lines are electrically connected to the gates of the transistors of the corresponding pixel units respectively; the gate lines pass through the border area of ​​the top Notch area of ​​the special-shaped display screen, and the gate line parts in the Notch area are in different metal layers. By making the gate lines in the border area of ​​the Notch area of ​​the display device with different metal layers, the distance between the staggered gate lines in the border area of ​​the Notch area can be designed to be shorter without short circuit, so that the border can be narrower, the effective display area is increased, and the display quality is improved.

[0046] Generally speaking, the gate line array of a display device includes gate lines in the effective display area AA and gate lines in the irregular-shaped area.

[0047] In this embodiment, it mainly refers to the gate lines passing through the top Notch area, where the gate lines are staggered, and the staggered arrangement means that adjacent gate lines are not on the same metal layer in the top Notch border area. In the display area, they are all wired on the gate metal layer.

[0048] Furthermore, the gate line includes a first gate line 100 and a second gate line 200; the first gate line 100 and the second gate line 200 are interlaced; the frame portion of the first gate line 100 and the Notch frame portion of the second gate line 200 are arranged in different metal layers. The first gate line 100 is wired in the gate metal layer, and the Notch frame portion of the second gate line 200 is wired in the SD layer metal.

[0049] Furthermore, the first gate line 100 includes a first display portion 110 and a first frame portion 120 (Notch frame portion); the first display portion 110 and the first frame portion 120 (Notch frame portion) are formed by making a metal pattern on a gate metal layer.

[0050] Preferably, if Figure 2 , Figure 2 Schematic diagram of gate line wiring in the Notch border area of ​​the array substrate in the present application; the second gate line 200 includes a second display portion 210, a second border portion 220 (Notch border portion), and a first via 230; the second display portion 210 is formed by making a metal pattern on the gate metal layer; the second border portion 220 (Notch border portion) is formed by making a metal pattern on the SD layer; the second display portion 210 and the second border portion 220 (Notch border portion) are overlapped through the first via 230.

[0051] Furthermore, the second gate line 200 also includes a third display portion 240 and a second via hole 250 ; the third display portion 240 is formed by making a metal pattern on the gate metal layer; the second frame portion 220 (Notch frame portion) is overlapped with the third display portion 240 through the second via hole 250 .

[0052] like Figure 3 , Figure 3 The schematic diagram is a partial enlarged diagram of the gate line wiring in the Notch border area of ​​the array substrate in the present application. The staggered arrangement of the first gate line 100 and the second gate line 200 shrinks from both ends to the middle border part.

[0053] In a second aspect, a display device adopts the array substrate of the first aspect.

[0054] By implementing the array substrate and display device of the utility model, the gate lines are made of different metal layers in the frame area of ​​the Notch area of ​​the display device, so that the distance between the staggered gate lines in the frame area of ​​the Notch area can be designed to be shorter without short circuit, thereby making the frame narrower, increasing the effective display area, and improving the display quality.

[0055] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate for a special-shaped display screen, characterized in that it comprises: a plurality of gate lines; The gate lines are electrically connected to the gates of the transistors of the corresponding pixel units respectively; The gate line passes through the border area of ​​the top Notch area of ​​the special-shaped display screen, and the gate line portion in the Notch area is in a different metal layer.

2. The array substrate according to claim 1, characterized in that: The gate line comprises: a first gate line; a second gate line; The first gate line and the second gate line are arranged in an interlaced manner; a frame portion of the first gate line and a frame portion of the second gate line are arranged in different metal layers.

3. The array substrate according to claim 2, characterized in that: The first gate line comprises: a first display unit; a first frame portion; The first display portion and the first frame portion are formed by manufacturing a metal pattern on a gate metal layer.

4. The array substrate according to claim 3, characterized in that: The second gate line comprises: a second display unit; a second frame portion; First via; The second display portion is formed by making a metal pattern on a gate metal layer; The second frame portion is formed by making a metal pattern on the SD layer; The second display portion and the second frame portion are overlapped through a first via hole.

5. The array substrate according to claim 4, characterized in that: The second gate line further includes: a third display unit; Second via; The third display portion is formed by making a metal pattern on the gate metal layer; The second frame portion and the third display portion are overlapped through a second via hole.

6. The array substrate according to claim 5, characterized in that: The staggered arrangement of the first gate lines and the second gate lines shrinks from both ends to the middle frame portion.

7. A display device, characterized in that: An array substrate as described in any one of claims 1 to 6 is used.

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