Display device

Abstract

A display device may include: a pixel circuit layer; a partition wall over the pixel circuit layer; a protruding member spaced apart from the partition wall in a planar direction and defining an opening; a planarization layer in the opening; a first electrode having at least a portion over the planarization layer; a light emitting member having at least a portion over the first electrode; and a second electrode having at least a portion over the light emitting part.

Description

Technical Field

[0001] The present disclosure relates generally to a display device, and to a method of manufacturing a display device. Background Art

[0002] Recently, with the increase of interest in information displays, research and development of display devices have been continuously carried out. For example, with the increase of demand for high-quality display devices, discussions on display devices including light-emitting elements having micrometer-level or nanometer-level sizes have been actively carried out. The light-emitting element may include an anode electrode, a light-emitting component, and a cathode electrode.

[0003] A display device including a light-emitting element having a micrometer-scale or nanometer-scale size may include a plurality of inter-pixel partition walls, which define an area where the light-emitting component is located. The light-emitting component may be deposited between the plurality of inter-pixel partition walls. When the light-emitting component is deposited between the plurality of inter-pixel partition walls, a shadow effect may occur due to the structure of the pixel partition walls, and therefore, the light-emitting component may not be formed in at least part of the area. This may narrow the area where the light-emitting component is deposited. In addition, the light emitted from the light-emitting component is blocked by the structure of the inter-pixel partition walls, and therefore, the luminous efficiency of the display device may be reduced.

[0004] Therefore, there is a need for a display device in which a light emitting member can be properly formed in a relatively wide area, thereby improving the light emitting efficiency of the display device. Summary of the invention

[0005] The embodiment provides a display device and a method of manufacturing the display device capable of improving light emitting efficiency of the display device while forming a light emitting part in a relatively wide area.

[0006] According to one aspect of the present disclosure, a display device is provided, which includes a pixel circuit layer, a partition wall above the pixel circuit layer, a protruding component separated from the partition wall in a planar direction and defining an opening, a planarization layer in the opening, a first electrode having at least a portion above the planarization layer, a light-emitting component having at least a portion above the first electrode, and a second electrode having at least a portion above the light-emitting component.

[0007] The partition wall may include a first partition wall layer over the pixel circuit layer and a second partition wall layer over the first partition wall layer.

[0008] A width of the first partition wall layer may be smaller than a width of the second partition wall layer.

[0009] The first partition wall layer may include aluminum (Al) or molybdenum (Mo), and the second partition wall layer may include titanium (Ti).

[0010] The protruding part may have the same height as the first partition wall layer.

[0011] The protruding part and the first partition wall layer may include the same material.

[0012] The protrusion part may include a first protrusion part over the pixel circuit layer and a second protrusion part over the first protrusion part, wherein the first protrusion portion has the same height as the first partition wall layer, and wherein the second protrusion part has the same height as the second partition wall layer.

[0013] The first protrusion part and the first partition wall layer may include the same material, and the second protrusion part and the second partition wall layer may include the same material.

[0014] The planarization layer may fill the opening, the planarization layer may include a planar surface, and the planarization layer may include an organic material.

[0015] The difference between the thickness of the planarization layer and the thickness of the protruding member may be approximately to approximately

[0016] The first electrode and the protrusion part may be electrically connected to each other.

[0017] According to another aspect of the present disclosure, a display device is provided, which includes a pixel circuit layer, a partition wall above the pixel circuit layer and including a first partition wall layer and a second partition wall layer above the first partition wall layer, a protruding component separated from the partition wall in a planar direction and having a flat surface separated from the pixel circuit layer, a first electrode having at least a portion above the protruding component, a light-emitting component having at least a portion above the first electrode, and a second electrode having at least a portion above the light-emitting component.

[0018] The protruding part and the dividing wall may be located in the same plane.

[0019] The first partition wall layer and the protrusion part may include aluminum (Al), and the first electrode completely overlaps the protrusion part in a plan view.

[0020] According to yet another aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising: in a single process, forming a partition wall and a protrusion component above a pixel circuit layer and spaced apart in a planar direction; forming a first electrode above the protrusion component; forming a light-emitting component above the first electrode; and forming a second electrode above the light-emitting component.

[0021] The formation of the partition wall and the protrusion component may include: depositing a first auxiliary layer above the pixel circuit layer; depositing a second auxiliary layer above the first auxiliary layer; etching the first auxiliary layer to form a first partition wall layer and the protrusion component on the pixel circuit layer; and etching the second auxiliary layer to form a second partition wall layer above the first partition wall layer, wherein the partition wall includes a first partition wall layer and a second partition wall layer, and wherein the first partition wall layer is etched inward than the second partition wall layer.

[0022] The formation of the partition wall and the protruding component may include: depositing a first auxiliary layer above the pixel circuit layer; depositing a second auxiliary layer above the first auxiliary layer; etching the first auxiliary layer to form a first partition wall layer and a first protruding component above the pixel circuit layer; and etching the second auxiliary layer to form a second partition wall layer above the first partition wall layer and to form a second protruding component on the first protruding component, and wherein the first protruding component and the second protruding component define an opening.

[0023] The method may further include forming a planarization layer by depositing a planarization layer in the opening defined by the protruding member so that the planarization layer and the protruding member have approximately To about The thickness difference.

[0024] Forming the first electrode may include depositing the first electrode over the protrusion part such that at least a portion of one surface of the first electrode is spaced apart from the pixel circuit layer.

[0025] The method may further include: forming a pixel defining layer including an inorganic material over the first electrode by depositing the pixel defining layer over the first electrode; and etching the pixel defining layer to expose at least a portion of the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic plan view showing a display device according to one or more embodiments of the present disclosure.

[0027] Figure 2 is a schematic cross-sectional view illustrating a display device according to one or more embodiments of the present disclosure.

[0028] Figure 3 is a schematic cross-sectional view showing a light emitting element according to one or more embodiments of the present disclosure.

[0029] Figure 4 is a schematic block diagram showing an electrical connection structure of a light emitting element according to one or more embodiments of the present disclosure.

[0030] Figure 5 is a schematic cross-sectional view showing a display device according to a first embodiment of the present disclosure.

[0031] Figure 6 is a schematic plan view of a positional relationship between a protruding member and a planarization layer according to a first embodiment of the present disclosure.

[0032] Figure 7 is a schematic cross-sectional view showing a display device according to a second embodiment of the present disclosure.

[0033] Figure 8 is a schematic cross-sectional view showing a display device according to a third embodiment of the present disclosure.

[0034] Fig. 9 is a flowchart illustrating a method of manufacturing the display device according to each of the first and second embodiments of the present disclosure.

[0035] Figures 10 to 16 2 is a schematic cross-sectional view illustrating a process operation according to a method of manufacturing the display device according to the first embodiment of the present disclosure.

[0036] Fig.17 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] By referring to the detailed description and the accompanying drawings of the embodiments, it is possible to more easily understand the various aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a complete understanding of the various aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof refer to the same elements, and therefore, repeated descriptions thereof can be omitted.

[0038] The described embodiments may have various modifications and may be implemented in different forms, and should not be understood as being limited to the embodiments shown herein. When describing an embodiment, the use of "can", "may" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, each feature of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another or may be implemented together in association.

[0039] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other features, characteristics, properties, etc. of the elements.

[0040] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances can be expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structures or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the illustrated elements, layers, or regions, but will include shape deviations caused by, for example, the manufacturing process.

[0041] For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is made.

[0042] For ease of explanation, spatially relative terms (such as "below", "below", "lower", "under", "under", "above", "on", and "upper", etc.) may be used herein to describe the relationship between an element or feature shown in the drawings and (multiple) elements or another (multiple) features. It will be understood that in addition to the orientations described in the drawings, spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements described as "below", "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the example terms "below" and "under" can cover both "above" and "below". The device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used in this article should be interpreted accordingly. Similarly, when a first portion is described as being disposed “on” a second portion, this indicates that the first portion is disposed at an upper side or a lower side of the second portion without being limited to the upper side thereof based on the gravity direction.

[0043] In addition, the phrase "in a plan view" means when the target portion is observed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross section intercepted by vertically cutting the target portion is observed from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object or on one side of the second object, and vice versa. In addition, the term "overlap" can include stacking, facing or facing, extending above / overall, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will understand and understand. The expression "non-overlap" can include meanings such as "away from" or "separate" or "deviate" and any other suitable equivalent meanings that a person of ordinary skill in the art will understand and understand. The terms "facing" and "facing" can mean that the first object can be directly or indirectly relative to the second object. In the case where a third object is between the first object and the second object, although the first object and the second object are still facing each other, the first object and the second object can be understood to be indirectly relative to each other.

[0044] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled / coupled to" another element, layer, region, or component, the element, layer, region, or component may be formed directly on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or coupled to the other element, layer, region, or component, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively represent direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled / coupled" to another layer, region, or component, it may be directly electrically connected or directly coupled / coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, resistors, and / or capacitors, etc. In describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled / directly coupled" or "directly on..." means that one component is directly connected or directly coupled / coupled to another component or directly on another component, with no intervening components.

[0045] In addition, in this specification, when a part of a layer, film, zone or plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, zone or plate, etc. is formed "under" another part, this not only includes the case where the part is "directly below" the other part, but also includes the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts such as "between...", "immediately between...", "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or two layers, the element or layer can be the only element or the only layer between the two elements or two layers, or one or more intermediate elements or intermediate layers may also be present.

[0046] For the purposes of this disclosure, expressions such as “at least one of…” or “any one of…” or “one or more of…” when following a list of elements modify the entire list of elements and do not modify the individual elements in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as X only, Y only, Z only, any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ, or any variation thereof. Similarly, expressions such as “at least one of A and B” may include A, B, or A and B. As used herein, “or” generally means “and / or,” and the term “and / or” includes any and all combinations of one or more of the relevant listed items. Similarly, other prepositional phrases, such as “at least one of,” “a plurality of,” “one of,” and the like, when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0047] It will be understood that, although the terms "first", "second", "third" and the like can be used herein to describe each element, component, zone, layer and / or interval, these elements, components, zones, layers and / or intervals should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, component, member, zone, region, layer, interval or part from another element, component, member, zone, region, layer, interval or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, zone, layer or interval described below can be referred to as the second element, component, zone, layer or interval. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second" and the like can also be used herein to distinguish between elements of different categories or groups. For the sake of brevity, the terms "first", "second" and the like can represent "first class (or first group)", "second class (or second group)" and the like, respectively. In this article, expressions such as depositing a certain element or layer, a certain element or layer being deposited means depositing the material used to form the element or layer.

[0048] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2 and / or the third direction DR3.

[0049] The terms used in this article are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "one" and "one (person / kind)" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It will also be understood that when used in this specification, the terms "comprises / comprising", "have / having" and "includes / including" illustrate the existence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0050] When one or more embodiments can be implemented in different ways, the specific process order can be performed in a different order than described. For example, two processes described in succession can be performed substantially simultaneously or in a reverse order to the described order.

[0051] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of +5% / -5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "approximately" or "approximately" includes the stated values ​​and means within an acceptable range of deviations of the particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0052] In some embodiments, known structures and devices may be described in the accompanying drawings involving one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. It will be understood by those skilled in the art that these functional blocks, units and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and can be selectively driven by hardware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or by combining dedicated hardware that performs some functions with a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from dedicated hardware. In addition, without departing from the scope of the present disclosure, in some embodiments, blocks, units and / or modules can be physically separated into two or more mutually interacting single blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have substantially the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their context in the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense.

[0054] The present disclosure generally relates to a display device and a method for manufacturing the display device. A display device and a method for manufacturing the display device according to one or more embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0055] Figure 1 is a schematic plan view showing a display device according to one or more embodiments of the present disclosure.

[0056] refer to Figure 1 The display device DD may be configured to emit light. The display device DD may include a light emitting element LD (see Figure 2 ). In some embodiments, the display device DD may be a device that displays a moving image or a still image. The display device DD may be used as a display screen not only for portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, and watch phones, but also for various products such as televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and micro displays. However, the application field of the display device DD is not limited to the specific examples.

[0057] The display device DD may be formed in a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The angle at which the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be formed in a circular arc shape to have a curvature (e.g., a predetermined curvature), or may be formed at a substantially right angle. The planar shape of the display device DD is not limited to a quadrangular shape, and the display device DD may be formed in a shape such as another polygonal shape, a circular shape, or an elliptical shape. The display device DD may be formed to be flat, but the present disclosure is not limited thereto. For example, the display device DD may include a curved portion formed at the left / right end and having a constant curvature or a varying curvature. In addition, the display device DD may be formed to be flexible enough to be twistable, bendable, bendable, foldable, or rollable.

[0058] In the present disclosure, the first direction DR1 may be a "horizontal" direction as a row direction of the pixels PXL. The second direction DR2 may be a "vertical" direction as a column direction of the pixels PXL. The third direction DR3 may be a display direction of the display device DD, or a normal direction of a plane where the base layer BSL is located.

[0059] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may mean an area not including the display area DA. The non-display area NDA may surround at least a portion of the display area DA (eg, in a plan view).

[0060] The display area DA may mean an area where the pixels PXL are located. The non-display area NDA may mean an area where the pixels PXL are not located. Driving circuits, wires, and pads connected to the pixels PXL of the display area DA may be located in the non-display area NDA.

[0061] In some embodiments, each pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 may constitute a pixel unit PXU capable of emitting light of various colors. Figure 1 , it is shown that each pixel PXL includes three sub-pixels SPX1 , SPX2 , and SPX3 (eg, a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 ). The present disclosure is not limited thereto.

[0062] In some embodiments, the pixel PXL (or sub-pixel SPX) may be arranged in a stripe structure or Arrangement structure (for example, RGBG matrix structure, Matrix structure, structure or RGBG structure, is a registered trademark of Samsung Display Co., Ltd. in the Republic of Korea) etc. However, the present disclosure is not limited thereto.

[0063] The first sub-pixel SPX1 may emit a first light, the second sub-pixel SPX2 may emit a second light, and the third sub-pixel SPX3 may emit a third light. The first light may be light of a red band, the second light may be light of a green band, and the third light may be light of a blue band. The red band may be a band of about 600nm to about 750nm, the green band may be a band of about 480nm to about 560nm, and the blue band may be a band of about 370nm to about 460nm. However, the present disclosure is not limited thereto.

[0064] Each of the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may include an inorganic light emitting diode or an organic light emitting diode (OLED) including an inorganic semiconductor as a light emitting element emitting light. However, the present disclosure is not limited to a specific example.

[0065] Figure 2 is a schematic cross-sectional view illustrating a display device according to one or more embodiments of the present disclosure. Figure 3 A schematic cross-sectional view of a light emitting element according to one or more embodiments of the present disclosure is shown.

[0066] Reference Figure 2 and Figure 3, the display device DD includes a pixel circuit layer PCL and a light emitting element layer LEL.

[0067] The pixel circuit layer PCL may include a pixel circuit PXC for driving the light emitting element LD (see Figure 4 ). The pixel circuit layer PCL may include a base layer BSL, a conductive layer for forming the pixel circuit PXC, and an insulating layer located on the conductive layer.

[0068] In some embodiments, the pixel circuit PXC may include a thin film transistor, and may be electrically connected to the light emitting element LD to provide an electrical signal for allowing the light emitting element LD to emit light.

[0069] The light emitting element layer LEL may be located on the pixel circuit layer PCL. In some embodiments, the light emitting element layer LEL may include a protrusion part PRU, a planarization layer PL, a light emitting element LD, a pixel defining layer PDL, and an encapsulation layer TFE.

[0070] The protrusion part PRU and the planarization layer PL may be located on the pixel circuit layer PCL. The protrusion part PRU and the planarization layer PL may be located directly on the pixel circuit layer PCL. The protrusion part PRU and the planarization layer PL may protrude in the thickness direction (eg, third direction DR3) of the base layer BSL.

[0071] The protruding part PRU and the planarization layer PL can allow the light emitting element LD (eg, the light emitting part EL) to be located at a higher position. The structural features related to this will be referred to later. Figure 5 The following is a description of the drawings.

[0072] The protrusion part PRU may include a conductive material. For example, the protrusion part PRU may include at least one selected from the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). The protrusion part PRU includes a conductive material as a conductive material for receiving the pixel circuit PXC (see Figure 4 ) provides a conduction path for an anode signal to the light-emitting element LD.

[0073] The light emitting element LD may be located on the pixel circuit layer PCL. The light emitting element LD may be located on the protrusion part PRU and the planarization layer PL. In a plan view, the light emitting element LD may overlap the protrusion part PRU and may overlap the planarization layer PL.

[0074] In some embodiments, the light emitting element LD may include a first electrode ELT1, a light emitting part EL, and a second electrode ELT2.

[0075] One surface of the light emitting part EL may be electrically connected to the first electrode ELT1 , and the other surface of the light emitting part EL may be electrically connected to the second electrode ELT2 .

[0076] The first electrode ELT1 may be an anode electrode ANO with respect to the light emitting part EL, and the second electrode ELT2 may be a cathode electrode CAT with respect to the light emitting part EL. In some embodiments, the first electrode ELT1 and the second electrode ELT2 may include a conductive material. For example, the first electrode ELT1 may include a conductive material including reflectivity, and the second electrode ELT2 may include a transparent conductive material. However, the present disclosure is not necessarily limited thereto. The first electrode ELT1 may be a cathode electrode CAT with respect to the light emitting part EL, and the second electrode ELT2 may be an anode electrode ANO with respect to the light emitting part EL.

[0077] The light emitting component EL may have a multilayer thin film structure including a light generating layer (e.g., an emission layer EML). The light emitting component EL may include a hole injection layer HIL for injecting holes, a hole transport layer HTL excellent in hole transport performance for increasing the chance of hole recombination by suppressing the movement of electrons not bound to the emission layer EML, an emission layer EML for emitting light by recombination of injected electrons and holes, an electron transport layer ETL for smoothly transporting electrons to the light generating layer, and an electron injection layer EIL for injecting electrons. The light emitting component EL may emit light based on an electrical signal provided from an anode electrode ANO (e.g., a first electrode ELT1) and a cathode electrode CAT (e.g., a second electrode ELT2).

[0078] At least a portion of the first electrode ELT1 may be located on the protrusion part PRU and the planarization layer PL.

[0079] At least a portion of the first electrode ELT1 may be directly located on the protrusion part PRU and the planarization layer PL.

[0080] At least a portion of the first electrode ELT1 may cover the protrusion part PRU and the planarization layer PL.

[0081] The pixel defining layer PDL may be located on the first electrode ELT1. The pixel defining layer PDL may be located on (e.g., above) the protruding part PRU. The pixel defining layer PDL may be located on the protruding part PRU to define the position where the light emitting part EL is located. For example, the pixel defining layer PDL may cover one end of the protruding part PRU and may define the position where the light emitting element EL is located on the planarization layer PL. The pixel defining layer PDL may expose at least a portion of the first electrode ELT1. In a plan view, the pixel defining layer PDL may not overlap at least a portion of the protruding part PRU.

[0082] The pixel defining layer PDL may include an inorganic material. For example, the inorganic material may include a material selected from silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) is at least one of the group consisting of. However, the present disclosure is not limited thereto. The pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include at least one selected from the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0083] At least a portion of the second electrode ELT2 may be located on the light emitting component EL. At least a portion of the second electrode ELT2 may be located directly on the light emitting component EL. At least a portion of the second electrode ELT2 may cover the light emitting component EL.

[0084] The encapsulation layer TFE may be located above the light emitting element LD (e.g., the second electrode ELT2). The encapsulation layer TFE may reduce or eliminate the step difference caused by the light emitting element LD and the pixel defining layer PDL. The encapsulation layer TFE may include a plurality of insulating layers covering the light emitting element LD. In some embodiments, the encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked. In some embodiments, the encapsulation layer TFE may be a thin film encapsulation layer.

[0085] Figure 4 is a schematic block diagram showing the electrical connection structure of a light emitting element according to one or more embodiments of the present disclosure. For example, Figure 4 An electrical connection structure including a pixel circuit PXC corresponding to each sub-pixel SPX may be shown.

[0086] refer to Figure 4 , the sub-pixel SPX may include a pixel circuit PXC configured to drive the light emitting element LD.

[0087] The pixel circuit PXC may include at least one circuit element. For example, the pixel circuit PXC may include a transistor and a storage capacitor. For example, the pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor. However, the present disclosure is not necessarily limited thereto.

[0088] The pixel circuit PXC may be electrically connected to a scan line SL and a data line DL. The scan line SL may provide a scan signal to the pixel circuit PXC. In some embodiments, the scan line SL may be electrically connected to a gate electrode of a switching transistor of the pixel circuit PXC. The light emitting element LD may be configured to emit light corresponding to a data signal provided from the data line DL.

[0089] The pixel circuit PXC may be electrically connected to the first power line PL1 and the second power line PL2. For example, the first electrode ELT1 of the light emitting element LD may be electrically connected to the pixel circuit PXC and the first power line PL1, and the second electrode ELT2 of the light emitting element LD may be electrically connected to the second power line PL2. In some embodiments, the second power line PL2 may be formed in the pixel circuit layer PCL in the display area DA. Alternatively, in other embodiments, the second power line PL2 may be located in the non-display area NDA. Therefore, the second power line PL2 may be configured to provide a second power source to the light emitting element LD.

[0090] The power supply of the first power line PL1 and the power supply of the second power line PL2 may have different potentials. For example, the power supply of the first power line PL1 may be a high potential pixel power supply powered by a power supply having a first voltage potential VDD, and the power supply of the second power line PL2 may be a low potential pixel power supply powered by a power supply having a second voltage potential VSS. The potential difference between the power supply of the first power line PL1 and the power supply of the second power line PL2 may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0091] The first power line PL1 may be electrically connected to the pixel circuit PXC (eg, a driving transistor). The second power line PL2 may be electrically connected to a cathode electrode (eg, a second electrode ELT2) of the light emitting element LD.

[0092] In some embodiments, the first power line PL1 may be electrically connected to the first electrode ELT1 through the pixel circuit PXC and the protrusion part PRU. In some embodiments, the protrusion part PRU may serve as a conductive path for supplying an anode signal provided from the pixel circuit PXC. For example, the protrusion part PRU may electrically connect the first electrode ELT1 to the pixel circuit layer PCL (see Figure 2 ) pixel circuit PXC.

[0093] In some embodiments, the second power line PL2 may be electrically connected to the second electrode ELT2 through a partition wall PW. In some embodiments, the partition wall PW may serve as a conductive path for supplying a cathode signal provided from the second electrode ELT2. For example, the partition wall PW may electrically connect the second electrode ELT2 and the second power line PL2 to each other. Figure 5 Describe the partition wall PW.

[0094] Each of the plurality of light emitting elements LD may be forwardly connected between the first power line PL1 and the second power line PL2 to form a respective effective light source, and these effective light sources together constitute the light emitting element LD of the sub-pixel SPX.

[0095] The light emitting element LD may emit light of brightness corresponding to the driving current supplied by the pixel circuit PXC. The pixel circuit PXC may supply the driving current corresponding to the data signal to the light emitting element LD during each frame. The light emitting element LD may emit light of brightness corresponding to the current flowing through the light emitting element LD.

[0096] In the following, reference will be made to Figure 5 and Figure 6 The structural features of the partition wall PW and the protruding part PRU of the display device DD according to the first embodiment of the present disclosure are described. Figure 5 and Figure 6 The parts that are repeated in the above description will not be repeated.

[0097] Figure 5 is a schematic cross-sectional view showing a display device according to a first embodiment of the present disclosure. Figure 6 is a schematic plan view of a positional relationship between a protruding member and a planarization layer according to a first embodiment of the present disclosure.

[0098] refer to Figure 5 The light emitting element layer LEL of the display device DD according to the first embodiment of the present disclosure may include a protruding part PRU, a planarization layer PL, a light emitting element LD, a pixel defining layer PDL, and an encapsulation layer TFE, and may further include a partition wall PW.

[0099] The partition wall PW may be located on the pixel circuit layer PCL. In some embodiments, the partition wall PW may have a multilayer structure. For example, the partition wall may have a multilayer structure including a first partition wall layer PW1 and a second partition wall layer PW2 located on the first partition wall layer PW1. Hereinafter, for the convenience of description, one or more embodiments in which the partition wall PW has a double-layer structure including the first partition wall layer PW1 and the second partition wall layer PW2 will be mainly described. However, the present disclosure is not limited thereto.

[0100] The partition wall PW may have a structure in which the second partition wall layer PW2 protrudes outwardly from the first partition wall layer PW1. For example, the partition wall PW may have a "T"-shaped structure. The first partition wall layer PW1 may have a width narrower than that of the second partition wall layer PW2. The first partition wall layer PW1 may have a thickness thicker than that of the second partition wall layer PW2.

[0101] In the present disclosure, the width can be defined with respect to a direction extending in a plane (e.g., in a plane direction) where the pixel circuit layer PCL is located (e.g., a first direction DR1 and / or a second direction DR2), and the thickness can be defined with respect to a thickness direction (e.g., a third direction DR3) of the pixel circuit layer PCL.

[0102] The partition wall PW may include a metal material. For example, the metal material may include at least one selected from the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). In some embodiments, the first partition wall layer PW1 may include aluminum (Al) or molybdenum (Mo). In some embodiments, the second partition wall layer PW2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0103] The protruding part PRU may be located on the pixel circuit layer PCL. The protruding part PRU may be spaced apart from the partition wall PW in the width direction of the partition wall PW. The protruding part PRU may be located on the same plane as the partition wall PW. The protruding part PRU and the partition wall PW may contact one surface (e.g., the top surface) of the pixel circuit layer PCL.

[0104] refer to Figure 6 , the protruding part PRU may include (e.g., may define) an opening H. For example, when viewed from the upper direction (e.g., the third direction DR3) of the display device DD, the protruding part PRU may have a circular shape including / defining the opening H. For example, the protruding part PRU may have a ring shape in a plan view. However, the present disclosure is not limited thereto. The protruding part PRU may have a polygonal shape including the opening H.

[0105] The protrusion part PRU may be formed by the same process as the first partition wall layer PW1. The protrusion part PRU may have substantially the same thickness as the first partition wall layer PW1. The protrusion part PRU may include the same material as the first partition wall layer PW1. The protrusion part PRU may include a metal layer. In some embodiments, the protrusion part PRU may include aluminum (Al) or molybdenum (Mo).

[0106] The protrusion part PRU may contact the first electrode ELT1. The protrusion part PRU may electrically connect the pixel circuit PXC of the pixel circuit layer PCL and the first electrode ELT1 to each other. Therefore, any contact hole connecting the pixel circuit PXC and the first electrode ELT1 does not need to be separately formed between the protrusion part PRU and the first electrode ELT1.

[0107] The planarization layer PL may be located inside the protrusion part PRU. The planarization layer PL may be located in the opening H of the protrusion part PRU. The planarization layer PL may fill the opening H of the protrusion part PRU. The planarization layer PL may contact the protrusion part PRU. The protrusion part PRU may surround the planarization layer PL.

[0108] The planarization layer PL may include an organic material. In some embodiments, the planarization layer PL may include at least one selected from the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0109] If a relatively high temperature (e.g., about 200° C. or higher) is applied to the layer after the layer is deposited, the layer including the organic material may have fluidity or flowability. When there is no protruding part PRU, the organic layer may melt at a high temperature and may flow in the direction where the partition wall PW is located. When the organic layer flows, there is no component (such as the protruding part PRU) that supports the flowing organic layer, and thus the organic layer may form an inclination. For example, the surface of the organic layer may not be flat.

[0110] Furthermore, if there is no component that supports reducing or preventing the flow of the organic layer, the organic layer may continue to flow, and thus, the organic layer may be difficult to be finely patterned. When the organic layer cannot be finely patterned, it may be difficult for the display to have a high resolution.

[0111] According to the display device DD described so far, the planarization layer PL may be located in the opening H of the protruding part PRU. Therefore, the protruding part PRU may surround the planarization layer PL and may support the planarization layer PL. Therefore, if a relatively high temperature heat is applied to the planarization layer PL after the planarization layer PL is deposited, the planarization layer PL does not overflow outward (for example, in the direction where the partition wall PW is located). Therefore, the surface of the planarization layer PL does not form an inclination. Therefore, the surface of the planarization layer PL can be formed to be flat.

[0112] Since the planarization layer PL can be made flat, according to the presently described display device DD, there is no need to separately perform chemical mechanical polishing (CMP) for allowing the surface of the planarization layer PL to be substantially flat.

[0113] Experimentally, if the light emitting element LD is formed, the first electrode ELT1 is suitable for being located on a substantially flat surface. According to the conventional display structure, since there is no structure corresponding to the protruding part PRU and the flattening layer PL of the present disclosure, the first electrode ELT1 is directly located on the pixel circuit layer PCL including the insulating layer formed of the inorganic layer at the outermost portion. Because the flatness of the inorganic layer is relatively poor, the first electrode ELT1 is positioned after the CMP process for allowing the surface of the inorganic layer to be flat is performed. In contrast, the first electrode ELT1 of the display device DD described herein is located on the flattening layer PL, so that there is no need to perform any CMP process for setting the first electrode ELT1.

[0114] The planarization layer PL may have substantially the same thickness as the protrusion part PRU, or may have a thickness thicker than that of the protrusion part PRU. The planarization layer PL and the protrusion part PRU may have thicknesses similar to each other. For example, the difference between the thickness of the planarization layer PL and the thickness of the protrusion part PRU may be within about 1000 nm. To about within the range.

[0115] The first electrode ELT1 may be located on the protrusion part PRU and the planarization layer PL. The first electrode ELT1 may completely cover the protrusion part PRU and the planarization layer PL. In a plan view, the first electrode ELT1 may overlap the protrusion part PRU and the planarization layer PL. The first electrode ELT1 may contact the protrusion part PRU and the planarization layer PL.

[0116] The two surfaces of the first electrode ELT1 may include inclined surfaces, respectively. Since each surface of the first electrode ELT1 has an inclined surface, the first electrode ELT1 can be positioned relatively high (e.g., relatively elevated) with respect to the pixel circuit layer PCL compared to a conventional display structure. For example, in a conventional display structure, the first electrode ELT1 is directly located on the pixel circuit layer PCL. One surface of the first electrode ELT1 is completely in contact with the pixel circuit layer PCL, and the one surface of the first electrode ELT1 is flat.

[0117] On the other hand, at least part of the one surface of the presently described first electrode ELT1 of the display device DD can be physically separated from the pixel circuit layer PCL. Therefore, compared with the conventional display structure, the first electrode ELT1 can be relatively elevated. In addition, since each surface of the electrode ELT1 is inclined, the surface area of ​​the first electrode ELT1 can be increased.

[0118] The first electrode ELT1 may have a single-layer structure or a multi-layer structure including a conductive material having reflectivity. For example, the first electrode ELT1 may have a multi-layer structure in which aluminum (Al), silver (Ag), and indium tin oxide (ITO) are sequentially located. Experimentally, according to the physical properties of aluminum (Al), if aluminum (Al) contacts the planarization layer PL, the first electrode ELT1 may have a high adhesion property compared to if silver (Ag) contacts the planarization layer PL.

[0119] The pixel defining layer PDL may be located on the protruding part PRU to define the position of the light emitting part EL on the protruding part PRU. The pixel defining layer PDL may be located on the first electrode ELT1. The pixel defining layer PDL may expose at least a portion of the first electrode ELT1. The pixel defining layer PDL may cover one end and the other end of the first electrode ELT1.

[0120] The pixel defining layer PDL may include an inorganic material. For example, the inorganic material may include a material selected from silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ) is selected from the group consisting of at least one.

[0121] At least part of the light emitting component EL may be located on the first electrode ELT1, the pixel defining layer PDL, and the second partition wall layer PW2. The light emitting component EL may include a (1-1)th light emitting component EL1-1 located on the protruding component PRU and a (1-2)th light emitting component EL1-2 located on the second partition wall layer PW2. The (1-1)th light emitting component EL1-1 and the (1-2)th light emitting component EL1-2 may be spaced apart from each other. The (1-1)th light emitting component EL1-1 and the (1-2)th light emitting component EL1-2 may not be connected to each other (for example, they may be electrically insulated from each other or spaced apart from each other). The (1-1)th light emitting component EL1-1 may completely cover the first electrode ELT1 and the pixel defining layer PDL. The (1-2)th light emitting component EL1-2 may completely contact one surface of the second partition wall layer PW2. In a plan view, the (1-2)th light emitting component EL1-2 may overlap the second partition wall layer PW2.

[0122] The light emitting part EL may be in full contact with the pixel defining layer PDL. For example, the light emitting part EL may be in contact with one side surface of the pixel defining layer PDL. The light emitting part EL may expose at least part of the side surface of the partition wall PW. For example, the light emitting part EL may expose at least part of the side surface of the first partition wall layer PW1.

[0123] Since the light-emitting component EL is located on the first electrode ELT1 which is relatively elevated compared to the conventional display structure, the light-emitting component EL itself may also be relatively elevated compared to the conventional display structure. For example, in a plan view, the height of the light-emitting component EL overlapping the planarization layer PL may be higher than the height of the first partition wall layer PW1. In the present disclosure, the height of the components of the display device DD may be defined in the thickness direction of the base layer BSL (e.g., the third direction DR3). Since the light-emitting component EL completely covers the pixel defining layer PDL, the surface area of ​​the light-emitting component EL may be increased compared to the conventional display structure. Since the surface area of ​​the light-emitting component EL can be increased, the light-emitting area can be increased, and the life of the display device DD can be increased. In addition, since the light-emitting component EL having a wide surface area and the first electrode ELT1 are connected to each other, the light-emitting area can be increased at the same current value.

[0124] In a conventional display structure, the height of the light emitting component EL overlapping the planarization layer PL in a plan view is lower than the height of the first partition wall layer PW1. Therefore, if the light emitting component EL is deposited, it is difficult to form the deposited material of the light emitting component EL in at least a partial area due to the tip structure or overhang of the second partition wall layer PW2. In addition, the light emitted from the light emitting component EL is blocked by the structure of the second partition wall layer PW2. In addition, because the light emitting component EL is deposited only in the pixel defining layer PDL, the surface area of ​​the light emitting component EL is relatively small compared to the display device DD of the present disclosure.

[0125] Since the first electrode ELT1 of the present disclosure is located high (e.g., raised to a greater extent) compared to the conventional display structure, if the light-emitting component EL is deposited on the first electrode ELT1, the shadow effect caused by the second partition wall layer PW2 can be reduced. Therefore, compared to the conventional display structure, the area where the light-emitting component EL is deposited can be increased, and the area where the light-emitting component EL can emit light can be increased. In addition, the risk that the light emitted from the light-emitting component EL will be blocked by the structure of the partition wall PW can be reduced. In the present disclosure, the shadow effect may refer to an effect that if a deposition material is deposited, the deposition material is not formed in at least a partial area due to an obstacle overlapping with the deposition material in the deposition direction.

[0126] The second electrode ELT2 may be located on the light emitting part EL. The second electrode ELT2 may include a (2-1)th electrode ELT2-1 located on the (1-1)th light emitting part EL1-1 and a (2-2)th electrode ELT2-2 located on the (1-2)th light emitting part EL1-2. The (2-1)th electrode ELT2-1 and the (2-2)th electrode ELT2-2 may be spaced apart from each other. The (2-1)th electrode ELT2-1 and the (2-2)th electrode ELT2-2 may not be connected to each other (for example, they may be electrically insulated from each other or spaced apart from each other). The second electrode ELT2 may completely cover the light emitting part EL. For example, the (2-1)th electrode ELT2-1 may contact the (1-1)th light emitting part EL1-1 located on the protruding part PRU, the planarization layer PL, and the pixel defining layer PDL. For example, the (2-2)th electrode ELT2-2 may contact one surface of the (1-2)th light emitting part EL1-2 located on the second partition wall layer PW2. In a plan view, the (2-2)th electrode ELT2-2 may overlap the (1-2)th light emitting part EL1-2 located on the second partition wall layer PW2.

[0127] The encapsulation layer TFE may be located above the light emitting element LD (eg, the second electrode ELT2) and the partition wall PW. The encapsulation layer TFE may eliminate or planarize a step difference caused by the partition wall PW and the light emitting element LD.

[0128] In the following, reference will be made to Figure 7 Structural features of the partition wall PW and the protrusion part PRU of the display device DD according to the second embodiment of the present disclosure are described. Figure 7 is a schematic cross-sectional view showing a display device according to a second embodiment of the present disclosure.

[0129] The second embodiment is different from the first embodiment in that the protruding part PRU has a multi-layer structure. Figure 7 In the description, the parts that are repeated with the above contents will not be repeated.

[0130] The protrusion part PRU according to the second embodiment of the present disclosure may include a first protrusion part PRU1 and a second protrusion part PRU2. The first protrusion part PRU1 may be located on the pixel circuit layer PCL. The first protrusion part PRU1 may contact the pixel circuit layer PCL. The second protrusion part PRU2 may be located on the first protrusion part PRU1. The second protrusion part PRU2 may contact the first protrusion part PRU1.

[0131] The first protruding part PRU1 may be formed by the same process as the first partition wall layer PW1. In some embodiments, the first protruding part PRU1 may be located on the same plane as the first partition wall layer PW1. The first protruding part PRU1 may have substantially the same thickness as the first partition wall layer PW1. The first protruding part PRU1 may include the same material as the first partition wall layer PW1. The first protruding part PRU1 may include a metal material. In some embodiments, the first protruding part PRU1 may include aluminum (Al) or molybdenum (Mo).

[0132] The second protruding part PRU2 may be formed by the same process as the second partition wall layer PW2. In some embodiments, the second protruding part PRU2 may be located on the same plane as the second partition wall layer PW2. The second protruding part PRU2 may have substantially the same thickness as the second partition wall layer PW2. The second protruding part PRU2 may include the same material as the second partition wall layer PW2. The second protruding part PRU2 may include a metal material. In some embodiments, the second protruding part PRU2 may include titanium (Ti).

[0133] The thickness obtained by adding the thickness of the first protruding part PRU1 and the thickness of the second protruding part PRU2 may be equal to or greater than the thickness of the planarization layer PL. The thickness obtained by adding the thickness of the first protruding part PRU1 and the thickness of the second protruding part PRU2 may be similar to the thickness of the planarization layer PL. For example, the difference between the thickness obtained by adding the thickness of the first protruding part PRU1 and the thickness of the second protruding part PRU2 and the thickness of the planarization layer PL may be included in about to approximately within the range.

[0134] Since the protruding part PRU of the display device DD according to the second embodiment of the present disclosure also includes a second protruding part PRU2, the protruding part PRU can further protrude from the pixel circuit layer PCL. Since the protruding part PRU further protrudes from the pixel circuit layer PCL, the planarization layer PL can be deposited without overflowing outward. In addition, since the protruding part PRU further protrudes from the pixel circuit layer PCL, in the display device DD according to the second embodiment of the present disclosure, the light-emitting part EL can also be relatively high (for example, relatively elevated) compared with the conventional display structure. Therefore, if the light-emitting part EL is deposited, the shadow effect caused by the structure of the second partition wall layer PW2 can be reduced. In addition, since the position of the light-emitting part EL becomes higher, the risk that the light emitted from the light-emitting part EL will be blocked by the second partition wall layer PW2 can be reduced. In addition, the planarization layer PL is supported by the protruding part PRU, so that the surface of the planarization layer PL can be formed to be flat.

[0135] Next, we will refer to Figure 8 Structural features of the partition wall PW and the protrusion part PRU of the display device DD according to the third embodiment of the present disclosure are described. Figure 8 is a schematic cross-sectional view showing a display device according to a third embodiment of the present disclosure.

[0136] The third embodiment is different from the first embodiment in that the protruding member PRU does not include an opening H (see Figure 7 ) and does not include the planarization layer PL. Figure 8 In the description, the parts that are repeated with the above description will be omitted.

[0137] The protrusion part PRU according to the third embodiment of the present disclosure may not include the opening H. Therefore, the planarization layer PL may not be located inside the protrusion part PRU. The planarization layer PL may not be located in the opening H of the protrusion part PRU.

[0138] For example, in the display device DD according to the third embodiment of the present disclosure, compared with the above embodiments, the protrusion part PRU may be located in the region where the planarization layer PL is located. In the display device DD according to the third embodiment of the present disclosure, the surface where the first electrode ELT1 and the light emitting part EL contact each other may completely overlap with the protrusion part PRU.

[0139] The protruding part PRU may include a flat surface at which the opening H is not formed. For example, the protruding part PRU may include a flat upper surface (e.g., a surface not in contact with the pixel circuit layer PCL and a surface opposite to the surface in contact with the pixel circuit layer PCL) at which the opening H is not formed.

[0140] The protrusion part PRU may be formed by the same process as the first partition wall layer PW1. The protrusion part PRU may have substantially the same thickness as the first partition wall layer PW1. The protrusion part PRU may include the same material as the first partition wall layer PW1. The protrusion part PRU may include a metal material. In some embodiments, the protrusion part PRU may include aluminum (Al) or molybdenum (Mo).

[0141] The first electrode ELT1 may be in full contact with the protrusion part PRU. In a plan view, the first electrode ELT1 may be in full overlap with the protrusion part PRU. In a plan view, the light emitting part EL may be in full overlap with the protrusion part PRU. The surface where the first electrode ELT1 and the light emitting part EL contact each other may correspond to or may substantially correspond to the flat upper surface of the protrusion part PRU.

[0142] In the display device DD according to the third embodiment of the present disclosure, since the protruding part PRU protrudes from the pixel circuit layer PCL, the light emitting part EL can be raised compared with the conventional display structure. Therefore, if the light emitting part EL is deposited, the shadow effect due to the second partition wall layer PW2 can be reduced. In addition, the risk of light emitted from the light emitting part EL being blocked by the structure of the second partition wall layer PW2 can also be reduced. In addition, since the protruding part PRU includes a flat upper surface, the first electrode ELT1 can be formed on a substantially flat surface.

[0143] In the following, reference will be made to Figures 9 to 16 A method of manufacturing the display device according to the first embodiment and the second embodiment of the present disclosure is described. Fig. 9 is a flowchart illustrating a method of manufacturing the display device according to each of the first and second embodiments of the present disclosure. Figures 10 to 16 2 is a schematic cross-sectional view illustrating a process operation according to a method of manufacturing the display device according to the first embodiment of the present disclosure.

[0144] refer to Fig. 9 , manufacturing a display device DD (see Figure 5 and Figure 7 ) may include an operation S100 of forming a partition wall and a protruding part on a pixel circuit layer, an operation S200 of forming a planarization layer, an operation S300 of forming a first electrode, an operation S400 of forming a pixel defining layer, an operation S500 of forming a light emitting part, and an operation S600 of forming a second electrode.

[0145] refer to Fig. 9 , Fig.10 and Fig.11 In the operation S100 of forming the partition wall and the protruding member on the pixel circuit layer, a method for driving the light emitting element LD (see Figure 5) may be formed on the base layer BSL. The pixel circuit layer PCL may be formed to include a conductive layer and an insulating layer between the conductive layers.

[0146] In some embodiments, components on the base layer BSL may be formed by a patterning process (eg, a photolithography process, etc.) using a mask.

[0147] After the pixel circuit layer PCL is formed, the partition wall PW and the protrusion part PRU may be formed on the pixel circuit layer PCL. The partition wall PW and the protrusion part PRU may be formed by the same process. Therefore, according to the method of manufacturing the display device DD of the present disclosure, the process may be simplified.

[0148] Operation S100 of forming the partition wall PW and the protrusion part PRU may include depositing a first auxiliary layer L1 on the pixel circuit layer PCL, depositing a second auxiliary layer L2, etching the first auxiliary layer L1, and etching the second auxiliary layer L2.

[0149] The operation of depositing the first auxiliary layer L1 may include an operation of depositing a material for forming the first partition wall layer PW1 and the protruding part PRU. In the present disclosure, at least one of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be used as a process for depositing components of the display device DD. However, the present disclosure is not limited to a specific example.

[0150] The first auxiliary layer L1 may be deposited on the pixel circuit layer PCL. The first auxiliary layer L1 may include the same material as the first partition wall layer PW1 and the protrusion part PRU. For example, the first auxiliary layer L1 may include aluminum (Al) or molybdenum (Mo).

[0151] The operation of depositing the second auxiliary layer L2 may include an operation of depositing a material for forming the second partition wall layer PW2. The second auxiliary layer L2 may be deposited on the first auxiliary layer L1. The second auxiliary layer L2 may include the same material as the second partition wall layer PW2. For example, the second auxiliary layer L2 may include titanium (Ti).

[0152] The operation of etching the second auxiliary layer L2 may include an operation of etching at least a portion of the second auxiliary layer L2. The second auxiliary layer L2 may be etched to expose at least a portion of the first auxiliary layer L1. The second auxiliary layer L2 may be etched to form a second partition wall layer PW2. The second auxiliary layer L2 may be etched so as not to be located on the protruding part PRU. The second auxiliary layer L2 may not be included on the protruding part PRU. In the present disclosure, at least one of wet etching and dry etching may be used as an etching process. However, the present disclosure is not limited to a specific example.

[0153] The operation of etching the first auxiliary layer L1 may include an operation of etching at least a portion of the first auxiliary layer L1. The first auxiliary layer L1 may be etched to expose at least a portion of the pixel circuit layer PCL. The first auxiliary layer L1 may be etched to form a first partition wall layer PW1 and a protruding part PRU. The first partition wall layer PW1 and the protruding part PRU may be formed by the same process. Therefore, the process of forming the first partition wall layer PW1 and the protruding part PRU may be simplified.

[0154] The first partition wall layer PW1 may be etched relatively deeper or to a greater extent than the second partition wall layer PW2 (e.g., in the first direction DR1 and / or the second direction DR2). Since the first partition wall layer PW1 is etched deeper than the second partition wall layer PW2, the first partition wall layer PW1 may have a structure that is retracted inwardly than the second partition wall layer PW2. The first partition wall layer PW may be etched so that the second partition wall layer PW2 forms a tip (e.g., an overhang above the first partition wall layer PW1).

[0155] The first auxiliary layer L1 may be etched so that the protrusion part PRU forms an opening H. The first auxiliary layer L1 may be etched so that the partition wall PW and the protrusion part PRU are spaced apart from each other in a direction (eg, first direction DR1 and / or second direction DR2 ) extending relative to a plane where the pixel circuit layer PCL is located.

[0156] refer to Fig. 9 and Fig.12 In operation S200 of forming the planarization layer, a planarization layer PL may be formed in the opening H of the protruding part PRU. The planarization layer PL may be deposited in or at the opening H of the protruding part PRU. The planarization layer PL may be deposited to have a thickness range similar to that of the protruding part PRU. For example, the planarization layer PL may be deposited so that the planarization layer PL and the protruding part PRU have a thickness range included in about To about The thickness difference is within the range of .

[0157] The planarization layer PL may include an organic material. Experimentally, if an organic layer including a polyimide resin is etched, the organic layer may be easily removed through a photo exposure process.

[0158] refer to Fig. 9 and Fig.13 In operation S300 of forming the first electrode, the first electrode ELT1 may be formed on the protrusion part PRU and the planarization layer PL. The first electrode ELT1 may be deposited to completely cover the protrusion part PRU and the planarization layer PL. At least a portion of the first electrode ELT1 may be etched to expose at least a portion of the pixel circuit layer PCL.

[0159] In some embodiments, the first electrode ELT1 may be formed to have a single layer structure or a multilayer structure. For example, the first electrode ELT1 may be deposited to have a multilayer structure in which aluminum (Al), silver (Ag), and indium tin oxide (ITO) are sequentially located. However, the present disclosure is not limited thereto.

[0160] According to the method of manufacturing a display device DD described in the present invention, the first electrode ELT1 is deposited on the protrusion part PRU and the planarization layer PL is further raised compared to the conventional display structure. Each of one surface and the other surface of the first electrode ELT1 may be deposited to form an inclined surface.

[0161] refer to Fig. 9 and Fig.14 In operation S400 of forming a pixel defining layer, a pixel defining layer PDL may be formed on the first electrode ELT1. The pixel defining layer PDL may be deposited to completely cover the first electrode ELT1. The pixel defining layer PDL may be etched to expose at least a portion of the first electrode ELT1. The pixel defining layer PDL may be etched to cover one end and the other end of the first electrode ELT1.

[0162] refer to Fig. 9 and Fig.15 In operation S500 of forming the light emitting component, the light emitting component EL may be deposited on the first electrode ELT1. The light emitting component EL may be deposited on the planarization layer PL and the second partition wall layer PW2. The light emitting component EL may be deposited to contact one surface of the first electrode ELT1 and one surface of the second partition wall layer PW2. The light emitting component EL may be deposited to expose at least a portion of a side surface of the first partition wall PW1.

[0163] Since the light emitting component EL is deposited on the first electrode ELT1 which is positioned high (e.g., raised to a large extent) compared to the conventional display structure, the light emitting component EL may also be positioned high compared to the conventional display structure. For example, the light emitting component EL overlapping with the planarization layer PL in a plan view may be deposited to a position higher than the first partition wall layer PW1. Therefore, the shadow effect of the area where the light emitting component EL is deposited being covered by the second partition wall layer PW2 may be reduced. In addition, if light is emitted from the light emitting component EL, the risk that the light emitted from the light emitting component EL will be blocked by the structure of the second partition wall layer PW2 may be reduced.

[0164] refer to Fig. 9 and Fig.16In operation S600 of forming the second electrode, the second electrode ELT2 may be formed on the light emitting part EL. The second electrode ELT2 may be deposited on the light emitting part EL. At least a portion of the second electrode ELT2 may contact the light emitting part EL located on the second partition wall layer PW2.

[0165] In the following, reference will be made to Figure 7 , Fig. 9 and Fig.10 A method for manufacturing a display device DD according to a second embodiment of the present disclosure is described. The method for manufacturing a display device DD according to the second embodiment is different from the method for manufacturing a display device DD according to the first embodiment in that the second auxiliary layer L2 is etched to form at least a portion of the protrusion part PRU. Hereinafter, the description of the parts that are repeated with the above content will not be repeated.

[0166] refer to Figure 7 , Fig. 9 and Fig.10 In operation S100 of forming the partition wall and the protrusion part on the pixel circuit layer, the protrusion part PRU may be formed to have a multi-layer structure including a first protrusion part PRU1 and a second protrusion part PRU2 located on the first protrusion part PRU1.

[0167] The first auxiliary layer L1 may be deposited on the pixel circuit layer PCL. The second auxiliary layer L2 may be deposited on the first auxiliary layer L1. The second auxiliary layer L2 may be etched to form a second partition wall layer PW2 and a second protruding part PRU2. The second partition wall layer PW2 and the second protruding part PRU2 may be formed by the same process. Therefore, the process of forming the second partition wall layer PW2 and the second protruding part PRU2 may be simplified.

[0168] In the following, reference will be made to Figure 8 , Fig.10 and Fig.17 A method of manufacturing the display device DD according to the third embodiment of the present disclosure is described. Fig.17 1 is a flowchart showing a method of manufacturing a display device according to one or more embodiments of the present disclosure. The method of manufacturing the display device DD according to the third embodiment is different from the method of manufacturing the display device DD according to the first embodiment in that if the first auxiliary layer L1 is etched, the first auxiliary layer L1 is etched so that the protruding part PRU does not form an opening H (see Figure 7 ). Hereinafter, the description of the parts that are repeated with the above contents will not be repeated.

[0169] refer to Fig.17 The method for manufacturing the display device DD according to the third embodiment of the present disclosure may omit the operation S200 of forming the planarization layer (see Fig. 9 ).

[0170] refer to Figure 8 , Fig.10 and Fig.17 In operation S100 of forming the partition wall and the protrusion part on the pixel circuit layer, when the first auxiliary layer L1 is etched to form the protrusion part PRU, the protrusion part PRU may not be etched to form the opening H. The protrusion part PRU may be formed to include a flat upper surface.

[0171] Since the protrusion part PRU does not form the opening H, in the operation S300 of forming the first electrode, the first electrode ELT1 may be deposited to completely contact the protrusion part PRU. For example, the first electrode ELT1 may completely contact the flat upper surface of the protrusion part PRU (for example, the entire upper surface of the protrusion part PRU may be contacted by the first electrode ELT1). In addition, in the operation S500 of forming the light emitting part, the light emitting part EL may be deposited to completely overlap with the protrusion part PRU in a plan view.

[0172] According to the present disclosure, a display device and a method of manufacturing the display device can be provided, which can improve the light emitting efficiency of the display device while forming a light emitting member in a relatively wide area.

[0173] Some embodiments are disclosed herein, and although specific terms are used, these terms are used and interpreted only in a general and descriptive sense and are not for limiting purposes. In some cases, as is readily apparent to those of ordinary skill in the art when submitting this application, unless otherwise specifically noted, the various aspects described in connection with the embodiments may be used alone or in combination with aspects described in connection with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made with the functional equivalents included in the claims without departing from the spirit and scope of the present disclosure as defined in the accompanying claims.

Claims

1. A display device, characterized in that: The display device comprises: Pixel circuit layer; A partition wall, above the pixel circuit layer; a protruding member spaced apart from the partition wall in a planar direction and defining an opening; a planarization layer in the opening; a first electrode having at least a portion above the planarization layer; a light emitting member having at least a portion above the first electrode; and The second electrode has at least a portion above the light emitting component.

2. The display device according to claim 1, characterized in that The partition wall comprises: A first partition wall layer, above the pixel circuit layer; and The second partition wall layer is above the first partition wall layer.

3. The display device according to claim 2, characterized in that: The width of the first partition wall layer is smaller than the width of the second partition wall layer.

4. The display device according to claim 2, characterized in that: The protruding part has the same height as the first partition wall layer.

5. The display device according to claim 2, characterized in that: The protruding component comprises: A first protruding member, above the pixel circuit layer; and a second protruding member, above the first protruding member, wherein the first protruding part and the first partition wall layer have the same height, and Wherein, the second protruding component and the second partition wall layer have the same height.

6. The display device according to claim 1, characterized in that: The planarization layer fills the opening, and the planarization layer includes a flat surface, The difference between the thickness of the planarization layer and the thickness of the protruding part is to and Wherein, the first electrode and the protruding part are electrically connected to each other.

7. A display device, characterized in that: The display device comprises: Pixel circuit layer; A partition wall, above the pixel circuit layer, and the partition wall includes a first partition wall layer and a second partition wall layer above the first partition wall layer; a protruding member spaced apart from the partition wall in a plane direction, and having a flat surface spaced apart from the pixel circuit layer; a first electrode having at least a portion above the protruding member; a light emitting member having at least a portion above the first electrode; and The second electrode has at least a portion above the light emitting component.

8. The display device according to claim 7, characterized in that: The protruding part and the partition wall are located in the same plane, The first electrode completely overlaps with the protruding part in a plan view.

Images