Detection equipment for on-off structure

Abstract

The embodiment of the utility model provides an on-off structure detection device, which comprises a first signal assembly, an on-off assembly and a processor, and is characterized in that the on-off assembly comprises N on-off structures, and each on-off structure is connected with a signal transmission port; and the processor is connected with the N on-off structures or the first signal assembly. Through the method and the device, the problem of resource waste caused when the on-off state of the on-off structure is detected in the prior art is solved, and the effect of saving detection resources is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of circuit detection, and in particular, to a detection device for a switch structure. Background Art

[0002] In the prior art, the detection of the on-off state of the on-off structure usually requires the setting of a detection circuit. The detection circuit is provided with input / output (I / O) ports corresponding to the number of on-off structures. That is, one on-off structure corresponds to one I / O port. For example, four switches in the switch detection circuit require four I / O ports for detection, wasting the resources of the I / O ports. In addition, the switch detection circuit requires multiple read operations to store the switch state, which also causes a waste of resources. Utility Model Content

[0003] The embodiment of the present application provides a detection device for an on-off structure, so as to at least solve the problem of waste of resources when detecting the on-off state of the on-off structure in the related art.

[0004] According to an embodiment of the present application, a detection device for an on-off structure is provided, comprising: a first signal component, an on-off component and a processor, wherein the first signal component comprises N signal transmission ports, wherein N is a natural number greater than 1; the on-off component comprises N on-off structures, wherein each of the on-off structures is connected to one of the signal transmission ports; the processor is connected to the N on-off structures or to the first signal component; wherein when the first signal component is working, N shift signals are output through the N signal transmission ports, the N signal transmission ports transmit the N shift signals to the corresponding N on-off structures, the processor respectively detects the level signal generated when each on-off structure transmits the corresponding shift signal, and detects the on-off state of each on-off structure based on the level signal generated by each on-off structure; or, when the on-off component is working, a target signal is transmitted to the processor through the N signal transmission ports, the processor detects the on-off state of each on-off structure based on the target signal, and the target signal is a signal determined based on the level signal generated by the N on-off structures.

[0005] In an exemplary embodiment, the first signal component is a first shift register, wherein the first shift register, the on-off component and the processor are connected in sequence, the first shift register is used to generate N of the shift signals, and transmit the N shift signals in parallel to the N on-off structures through the N signal transmission ports, and the waveforms of the N shift signals are used to determine the detection order of the N on-off structures.

[0006] In an exemplary embodiment, the first shift register further includes a waveform adjustment component, wherein the waveform adjustment component is used to adjust the waveforms of the N shift signals to adjust the detection sequence of the N on-off structures.

[0007] In an exemplary embodiment, the detection device further includes: N first current regulating components, wherein one end of each of the first current regulating components is connected to a corresponding one of the signal transmission ports, and the other end is connected to a corresponding one of the on-off structures, wherein the N first current regulating components are used to adjust the current transmitted by the first shift register so that the current transmitted to the on-off components is within a preset current range.

[0008] In an exemplary embodiment, the detection device further includes: a second current regulating component, wherein one end of the second current regulating component is connected to the N on-off components, and the other end is connected to the processor, wherein the second current regulating component is used to regulate the current transmitted from the on-off components to the processor.

[0009] In an exemplary embodiment, the detection device of the on-off structure further includes: a prompt component, wherein the prompt component is connected to the first shift register, wherein when the first shift register operates under the power supply of the first power module, the prompt component is driven to start, and the prompt component includes a light emitting diode LED light and / or a sounder.

[0010] In an exemplary embodiment, the above-mentioned first signal component is a second shift register, wherein the above-mentioned second shift register is connected between the above-mentioned on-off component and the above-mentioned processor, and the above-mentioned second shift register is used to receive N target level signals transmitted by N above-mentioned on-off structures through N above-mentioned signal transmission ports, and convert the N above-mentioned target level signals into the above-mentioned target signal, wherein the above-mentioned target level signal is a signal determined by the above-mentioned on-off component based on the level signal generated by each above-mentioned on-off structure.

[0011] In an exemplary embodiment, the detection device further includes: N third current regulating components, wherein one end of each of the third current regulating components is connected to the second power supply module, and the other end is connected to a corresponding one of the on-off structures, wherein the N third current regulating components are used to regulate the current transmitted from the second power supply module to the on-off components.

[0012] In an exemplary embodiment, the detection device further includes: N fourth current regulating components, wherein one end of each of the fourth current regulating components is connected to a corresponding one of the on-off structures, and the other end is connected to a corresponding one of the signal transmission ports, wherein the N fourth current regulating components are used to regulate the current transmitted by the on-off components to the second shift register.

[0013] In an exemplary embodiment, the processor includes a detection unit, wherein the detection unit is used to respectively detect the level signal generated by each of the on-off structures, and determine the on-off state of each of the on-off structures based on the level signal of each of the on-off structures, wherein when the level signal is a high level, the on-off structure is in an on state, and when the level signal is a low level, the on-off structure is in an off state; or, the detection unit is used to detect an N-bit signal value in the target signal, wherein one bit of the signal value corresponds to one on-off structure, and when the signal value is a first preset value, the on-off structure is in an on state, and when the signal value is a second preset value, the on-off structure is in an off state.

[0014] Through the present application, since the detection device of the on-off structure includes a first signal component, an on-off component and a processor, the first signal component includes N signal transmission ports, the on-off component includes N on-off structures, and each on-off structure is connected to a signal transmission port, the processor can detect the on-off state of multiple on-off structures through multiple signals transmitted by a first signal component, that is, only one detection interface corresponding to the first signal component needs to be set to realize the detection of the on-off state of multiple on-off structures. Thereby, resources for detecting the on-off state are saved. Therefore, the problem of waste of resources when detecting the on-off state of the on-off structure in the related art can be solved, and the effect of saving detection resources can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The structural framework of the on-off structure detection device according to the embodiment of the present application Figure 1 ;

[0016] Figure 2 The structural framework of the on-off structure detection device according to the embodiment of the present application Figure 2 ;

[0017] Figure 3 Schematic diagram of the connection relationship between the serial-to-parallel shift register, K2 and MISO according to an embodiment of the present application Figure 1 ;

[0018] Figure 4 is a waveform diagram of an output signal of a serial-to-parallel shift register according to an embodiment of the present application;

[0019] Figure 5 is a waveform diagram of the MISO port output according to an embodiment of the present application;

[0020] Figure 6 Schematic diagram of the connection relationship between the serial-to-parallel shift register, K2 and MISO according to an embodiment of the present application Figure 2 ;

[0021] Figure 7 Schematic diagram of the connection relationship between the parallel-to-serial shift register, K2 and MISO according to an embodiment of the present application Figure 1 . DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] In this embodiment, a detection device for an on-off structure is provided, and the detection device includes:

[0025] A first signal component, an on-off component and a processor, wherein:

[0026] The first signal component includes N signal transmission ports, where N is a natural number greater than 1;

[0027] The switch component includes N switch structures, wherein each switch structure is connected to a signal transmission port;

[0028] A processor connected to the N on-off structures or to the first signal component;

[0029] Among them, when the first signal component is working, N shift signals are output through N signal transmission ports, and the N signal transmission ports transmit the N shift signals to the corresponding N on-off structures. The processor detects the level signals generated when each on-off structure transmits the corresponding shift signals, and detects the on-off state of each on-off structure based on the level signals generated by each on-off structure; or, when the on-off component is working, the target signal is transmitted to the processor through the N signal transmission ports, and the processor detects the on-off state of each on-off structure based on the target signal, and the target signal is a signal determined based on the level signals generated by the N on-off structures.

[0030] In this embodiment, when the processor is connected to N on-off structures, the connection between the first signal component, the on-off component and the processor is as follows: Figure 1When the processor is connected to the first signal component, the connection between the first signal component, the on-off component and the processor is as follows: Figure 2 described.

[0031] Optionally, the first signal component includes but is not limited to a device capable of generating a signal, for example, a serial-to-parallel shift register or a parallel-to-serial shift register.

[0032] Optionally, the on-off component includes but is not limited to a component including multiple on-off structures, which is mainly used to encapsulate multiple on-off structures. The on-off structure refers to a device that controls the current in the circuit. The on-off structure includes two states: power on and power off. In the power-on state, the current can pass through the circuit smoothly to achieve normal operation of the circuit; in the power-off state, the current cannot pass through the circuit and the circuit cannot work. By controlling the on-off structure, the switch control of the circuit can be achieved, and the start and stop of the circuit can be achieved.

[0033] The on-off structure includes: Relay: A relay is an electrical control device that can be used to control the switch of a circuit. It has a function similar to that of a switch. By controlling the contact state of the relay, the circuit can be opened or closed. Transistor: A transistor is a semiconductor device that can be used as a switch in a circuit to control the flow of current. By controlling the on or off state of the transistor, a function similar to that of a switch can be achieved. Field effect transistors can also be used as switches in circuits. By adjusting the gate voltage of the field effect transistor, its on or off state can be controlled to achieve a function similar to that of a switch. Electronic switch: An electronic switch is a device specially designed to control the switch of a circuit. It can be controlled by an electronic signal to achieve a switching function. Common electronic switches include field effect transistor (FET) switches, relay switches, etc.

[0034] Optionally, the processor in this embodiment is a device with a signal or waveform detection function. For example, MISO (Multiple Input Single Output) with a multiple-input single-output function, MISO is a multiple-input single-output communication method, usually used in data transmission or communication systems. The MISO output waveform depends on the characteristics of the input signal and the system design. The output waveform of MISO may be a superposition or mixture of multiple input signals. For example, if the input signal is a plurality of sinusoidal wave signals, the output waveform may be a superposition or mixture of these sinusoidal wave signals. In addition, MISO can also realize signal separation and demodulation, extracting and outputting multiple input signals separately.

[0035] For example, the connection between the first signal component, the on / off component and the processor is as follows: Figure 1As shown, the first signal component is a serial-to-parallel shift register, and the serial-to-parallel shift register includes 8 signal transmission ports, the on-off component includes 8 switches K2, and the processor is a device with MISO function. The connection relationship between the serial-to-parallel shift register, K2 and MISO is as follows: Figure 3 When the serial-to-parallel shift register is working, ID_0~ID_7 are the signals output by the serial-to-parallel shift register. The waveforms of ID_0~ID_7 are as shown in Figure 4 As shown, it is output to the corresponding 8 switches in K2 through 8 signal transmission ports. When ID_0 is a high-level signal, the on-off state of the first switch in K2 is detected. Similarly, when ID_7 is a high-level signal, the on-off state of the eighth switch of K2 is detected. The MISO port can receive a set of eight-bit data signals with eight switch states. For example, if the switch state is that the first switch of the K2 switch is on (K2.1 is uniformly represented as on in this embodiment), K2.2 is on, K2.3 is off, K2.4 is off, K2.5 is on, K2.6 is on, K2.7 is on, and K2.8 is off, then the MISO port outputs a waveform as shown. Figure 5 As shown, it is 11001110.

[0036] Through the above detection device, since the detection device of the on-off structure includes a first signal component, an on-off component and a processor, the first signal component includes N signal transmission ports, the on-off component includes N on-off structures, and each on-off structure is connected to a signal transmission port, the processor can detect the on-off state of multiple on-off structures through multiple signals transmitted by a first signal component, that is, only one detection interface corresponding to the first signal component needs to be set to realize the detection of the on-off state of multiple on-off structures. Thereby, resources for detecting the on-off state are saved. Therefore, the problem of waste of resources when detecting the on-off state of the on-off structure in the related art can be solved, and the effect of saving detection resources can be achieved.

[0037] In an exemplary embodiment, the first signal component is a first shift register, wherein the first shift register, the on-off component and the processor are connected in sequence, the first shift register is used to generate N shift signals, and transmit the N shift signals in parallel to N on-off structures through N signal transmission ports, and the waveforms of the N shift signals are used to determine the detection order of the N on-off structures.

[0038] Optionally, the first shift register may be the serial-to-parallel shift register in the above embodiment. Figure 3The serial-to-parallel shift register is connected to K2 and MISO. The ID_0 to ID_7 signals output by the serial-to-parallel shift register are output to the corresponding 8 switches in K2 through 8 signal transmission ports, and MISO detects the on-off status of the eight switches of K2. It should be noted that the waveforms of the N shift signals are shifted, that is, Figure 4 As shown, the waveforms of the eight signals are all staggered, so that the eight switches can be detected simultaneously in the order of the waveforms. In this embodiment, the multiple waveform signals output by a first shift register can detect the on-off states of multiple on-off structures, effectively saving detection resources.

[0039] Among them, the serial-to-parallel shift register is a digital logic circuit used to convert serial input signals into parallel output signals. In this circuit, the input signal enters each storage unit in the register in turn, and the input signal is passed to the next storage unit in each clock cycle. When all input signals are loaded into the register, the data can be passed to other circuits or devices through the parallel output port.

[0040] Optionally, the first shift register further includes a waveform adjustment component, wherein the waveform adjustment component is used to adjust the waveforms of the N shift signals to adjust the detection order of the N on-off structures. In this embodiment, the waveform adjustment component is an electronic component used to adjust the signal waveform, which can change the amplitude, frequency, phase or waveform shape of the signal to meet the needs of the detection switch. The waveform adjustment component includes but is not limited to an amplifier, a filter, a phase adjuster, a frequency adjuster, etc. For example, Figure 4 The figure shows the misaligned waveform after adjustment by the waveform adjustment component, and other misaligned waveforms are also possible.

[0041] Optionally, the detection device also includes: N first current regulating components, wherein one end of each first current regulating component is connected to a corresponding signal transmission port, and the other end is connected to a corresponding on-off structure, wherein the N first current regulating components are used to adjust the current transmitted by the first shift register so that the current transmitted to the on-off component is within a preset current range. In this embodiment, the first current regulating component includes but is not limited to resistors, potentiometers, variable resistors, resistor networks and other devices, which are mainly used to limit current, adjust voltage, divide voltage, etc. These devices can adjust the resistance value to change the characteristics and performance of the circuit. For example, Figure 6 As shown, eight resistors R19-R26 are arranged between the shift register and K2 to adjust the current transmitted to each switch to protect the switch.

[0042] Optionally, the detection device further includes: a second current regulating component, wherein one end of the second current regulating component is connected to the N on-off components, and the other end is connected to the processor, wherein the second current regulating component is used to regulate the current transmitted from the on-off components to the processor. Figure 6 As shown, a resistor R35 is set at MISO to adjust the current transmitted to MISO to protect MISO.

[0043] Optionally, the detection device of the on-off structure also includes: a prompt component, wherein the prompt component is connected to the first shift register, wherein when the first shift register works under the power supply of the first power module, the prompt component is driven to start, and the prompt component includes a light-emitting diode LED lamp and / or a sounder. In this embodiment, the first shift register is a register of the multiplexed prompt component. For example, if there is an LED lamp drive in the application, the signal from the serial transfer and shift register will be used to drive the LED lamp, and these signals are multiplexed to detect the on-off state of the switch.

[0044] Optionally, in order to drive the LED lamp, the parallel output port of the serial-to-parallel shift register can be connected to the control circuit of the LED. Each storage unit corresponds to an LED lamp. When the input signal is loaded into the register, the state of each storage unit will determine whether the corresponding LED lamp is lit. By controlling the content of the input signal and the frequency of the clock signal, different display effects of the LED lamp can be achieved, such as running lights, breathing lights, etc. In general, the serial-to-parallel shift register can be used as a signal driver to control the on and off of the LED lamp to achieve different lighting effects.

[0045] Optionally, the first shift register can detect multiple switches when generating a regular waveform, that is, an initialization process or an external button is required to realize the state detection of the 8-bit dip switch, thereby identifying the address code of the dip switch. The purpose of detecting the eight-bit address code of an I / O port is achieved, and the practicability is strong.

[0046] In this embodiment, the 8-bit DIP switch is a switch device with 8 switch positions, each of which can select one of two states (usually on or off). This switch is usually used to control different functions or settings of a circuit, and different configurations or operating modes are achieved by changing the state of each switch position. 8-bit DIP switches are often used in electronic equipment, control systems, and communication equipment to achieve parameter settings or function selection.

[0047] In an exemplary embodiment, the first signal component is a second shift register, wherein,

[0048] The second shift register is connected between the on-off component and the processor, and is used to receive N target level signals transmitted by N on-off structures through N signal transmission ports, and convert the N target level signals into target signals, wherein the target level signal is a signal determined by the on-off component based on the level signal generated by each on-off structure.

[0049] Optionally, the second shift register may be Figure 7 The parallel-to-serial shift register shown is suitable for scenarios requiring real-time address coding recognition. For example, when the switch states are K2.1 on, K2.2 on, K2.3 off, K2.4 off, K2.5 on, K2.6 on, K2.7 on, and K2.8 off, through the conversion of the parallel-to-serial shift register, MISO outputs an 8-bit signal of 11001110.

[0050] Optionally, the detection device further includes: N third current regulating components, wherein one end of each third current regulating component is connected to the second power module, and the other end is connected to a corresponding on-off structure, wherein the N third current regulating components are used to regulate the current transmitted from the second power module to the on-off component. In this embodiment, the third current regulating component includes but is not limited to devices such as resistors, potentiometers, variable resistors, and resistor networks, and is mainly used to limit current, adjust voltage, divide voltage, etc. For example, Figure 7 R36-R43 shown can regulate the current transmitted from the power module to the switch, thereby protecting the switch.

[0051] Optionally, the detection device further includes: N fourth current regulating components, wherein one end of each fourth current regulating component is connected to a corresponding on-off structure, and the other end is connected to a corresponding signal transmission port, wherein the N fourth current regulating components are used to adjust the current transmitted from the on-off component to the second shift register. In this embodiment, the fourth current regulating component includes but is not limited to devices such as resistors, potentiometers, variable resistors, and resistor networks, which are mainly used to limit current, adjust voltage, divide voltage, etc. These devices can adjust the resistance value to change the characteristics and performance of the circuit. For example, Figure 7 R52-R59 shown can regulate the current transmitted from the power module to the switch, thereby protecting the switch.

[0052] In an exemplary embodiment, the processor includes a detection unit, wherein the detection unit is used to respectively detect the level signal generated by each on-off structure, and determine the on-off state of each on-off structure based on the level signal of each on-off structure, wherein when the level signal is a high level, the on-off structure is in an on state, and when the level signal is a low level, the on-off structure is in an off state; or, the detection unit is used to detect an N-bit signal value in a target signal, wherein one bit of the signal value corresponds to one on-off structure, and when the signal value is a first preset value, the on-off structure is in an on state, and when the signal value is a second preset value, the on-off structure is in an off state.

[0053] Optionally, the detection unit detects the level signal generated by each on-off structure respectively, and determines the on-off state of each on-off structure based on the level signal of each on-off structure, which is suitable for Figure 1 In the scenario shown in FIG. 1 , the detection unit detects the N-bit signal value in the target signal and is suitable for Figure 2 In the scenario shown, a single I / O port is able to detect the closed state of multiple switches.

[0054] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0055] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0056] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A detection device for an on-off structure, characterized in that: include: A first signal component, an on-off component and a processor, wherein: The first signal component includes N signal transmission ports, wherein N is a natural number greater than 1; The switch component includes N switch structures, wherein each of the switch structures is connected to one of the signal transmission ports; The processor is connected to the N on-off structures or to the first signal component; Among them, when the first signal component is working, N shift signals are output through the N signal transmission ports, and the N signal transmission ports transmit the N shift signals to the corresponding N on-off structures. The processor respectively detects the level signals generated when each on-off structure transmits the corresponding shift signal, and detects the on-off state of each on-off structure based on the level signal generated by each on-off structure; or, when the on-off component is working, the target signal is transmitted to the processor through the N signal transmission ports, and the processor detects the on-off state of each on-off structure based on the target signal, and the target signal is a signal determined based on the level signal generated by the N on-off structures.

2. The device according to claim 1, characterized in that The first signal component is a first shift register, wherein The first shift register, the on-off component and the processor are connected in sequence, the first shift register is used to generate N shift signals, and transmit the N shift signals in parallel to the N on-off structures through the N signal transmission ports, and the waveforms of the N shift signals are used to determine the detection order of the N on-off structures.

3. The device according to claim 2, characterized in that The first shift register also includes a waveform adjustment component, wherein the waveform adjustment component is used to adjust the waveforms of the N shift signals to adjust the detection sequence of the N on-off structures.

4. The device according to claim 2, characterized in that The detection device further includes: N first current regulating components, wherein: One end of each of the first current regulating components is connected to a corresponding signal transmission port, and the other end is connected to a corresponding on-off structure, wherein the N first current regulating components are used to regulate the current transmitted by the first shift register so that the current transmitted to the on-off component is within a preset current range.

5. The device according to claim 2, characterized in that The detection device further includes: a second current regulating component, wherein: One end of the second current regulating component is connected to the N on-off components, and the other end is connected to the processor, wherein the second current regulating component is used to regulate the current transmitted from the on-off components to the processor.

6. The device according to claim 2, characterized in that The detection device of the on-off structure further includes: a prompt component, wherein: The prompt component is connected to the first shift register, wherein when the first shift register works under the power supply of the first power module, the prompt component is driven to start, and the prompt component includes a light emitting diode LED lamp and / or a sounder.

7. The device according to claim 1, characterized in that The first signal component is a second shift register, wherein The second shift register is connected between the on-off component and the processor, and is used to receive N target level signals transmitted by N on-off structures through N signal transmission ports, and convert the N target level signals into the target signal, wherein the target level signal is a signal determined by the on-off component based on the level signal generated by each on-off structure.

8. The device according to claim 7, characterized in that The detection device further includes: N third current regulating components, wherein: One end of each of the third current regulating components is connected to the second power module, and the other end is connected to a corresponding on-off structure, wherein the N third current regulating components are used to regulate the current transmitted from the second power module to the on-off component.

9. The device according to claim 7, characterized in that The detection device further includes: N fourth current regulating components, wherein: One end of each of the fourth current regulating components is connected to a corresponding one of the on-off structures, and the other end is connected to a corresponding one of the signal transmission ports, wherein the N fourth current regulating components are used to regulate the current transmitted by the on-off component to the second shift register.

10. The device according to claim 1, characterized in that The processor includes a detection unit, wherein: The detection unit is used to respectively detect the level signal generated by each of the on-off structures, and determine the on-off state of each of the on-off structures based on the level signal of each of the on-off structures, wherein when the level signal is at a high level, the on-off structure is in an on state, and when the level signal is at a low level, the on-off structure is in an off state; or The detection unit is used to detect the N-bit signal value in the target signal, wherein one bit of the signal value corresponds to one on-off structure, and when the signal value is a first preset value, the on-off structure is in an on state, and when the signal value is a second preset value, the on-off structure is in an off state.

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