Silicon optical chip and 400G DR4 silicon optical module

Abstract

The utility model relates to a silicon optical chip, which comprises a 2 * 2 coupler and two 1 * 2 couplers which are integrated in the chip, and a light inlet waveguide, four light outlet waveguides and a test waveguide which are integrated in the chip and located on the same side, and the four light outlet waveguides and the test waveguide are distributed side by side in a mode of inclining by 8 degrees. Two input waveguides of the 2 * 2 coupler are respectively connected with the light inlet waveguide and the test waveguide, two output waveguides of the 2 * 2 coupler are respectively connected with input waveguides of the two 1 * 2 couplers, and four output waveguides of the two 1 * 2 couplers are respectively butted with the four light outlet waveguides one by one. The 400G DR4 silicon optical module comprises the silicon optical chip. The beneficial effects are that one optical fiber array can be reduced during testing, the testing efficiency is effectively improved, and mass production testing is facilitated.

Description

Technical Field

[0001] The utility model relates to the technical field of silicon photonic modules, and in particular to a silicon photonic chip and a 400G DR4 silicon photonic module. Background Art

[0002] The mainstream solution of traditional 400G DR4 silicon photonic modules adopts a 1-to-4 solution, that is, the light beam emitted by the laser chip in an optical transmitter enters a silicon photonic chip, and the silicon photonic chip divides the 1 incoming light into 4 outgoing light, and then the 4 outgoing light is coupled into a four-channel 8° inclined optical fiber array. The mainstream of this type of 400G DR4 silicon photonic modules adopts an edge coupling solution. Figure 1 As shown, since there is an optical isolator in the optical emitting component and in order to ensure the coupling efficiency of the laser chip in the optical emitting component, the light input waveguide of the silicon photonic chip is designed to be 0°. In order to reduce the light reflection when the light output of the silicon photonic chip is coupled with the optical fiber array, the four light output waveguides of the silicon photonic chip are designed to be tilted 8°.

[0003] Since the manufacturing process of silicon photonic chips is not particularly mature at present, a certain proportion of silicon photonic chips produced will have a large insertion loss problem. The insertion loss includes: chip internal waveguide insertion loss and waveguide end face edge coupling insertion loss. In order to test whether the silicon photonic chip insertion loss is qualified, it is limited by the structure of the silicon photonic chip. It is necessary to equip two fiber arrays, namely a single-channel fiber array and a four-channel fiber array. The single-channel fiber array is a 0° fiber array, which is coupled with the input waveguide edge of the silicon photonic chip and is externally connected to a light source to input light into the input waveguide of the silicon photonic chip. The four-channel fiber array is a four-channel inclined 8° fiber array, which is coupled with the four output waveguide edges of the silicon photonic chip and is externally connected to an optical power meter. Figure 2 As shown, the end-to-end insertion loss (including edge coupling insertion loss and chip internal waveguide insertion loss) is tested. This type of silicon photonic chip testing efficiency is low and difficult to mass-produce. Utility Model Content

[0004] The technical problem to be solved by the present invention is to provide a silicon photonic chip and a 400G DR4 silicon photonic module to overcome the deficiencies in the above-mentioned prior art.

[0005] The utility model solves the above-mentioned technical problem with the following technical solution: a silicon photonic chip, comprising: a 2×2 coupler and two 1×2 couplers integrated inside the chip, and an input light waveguide, four output light waveguides and a test waveguide integrated inside the chip and on the same side, wherein the four output light waveguides and the test waveguide are arranged side by side at an angle of 8°; the two input waveguides of the 2×2 coupler are respectively connected to the input light waveguide and the test waveguide, the two output waveguides of the 2×2 coupler are respectively connected to the input waveguides of the two 1×2 couplers, and the four output waveguides commonly possessed by the two 1×2 couplers are respectively connected to the four output light waveguides one by one.

[0006] The beneficial effects of the utility model are:

[0007] If the insertion loss of a single silicon photonic chip is tested to be qualified, a five-channel 8° inclined fiber array is equipped. Four optical fibers in the five-channel 8° inclined fiber array are coupled with the four light-emitting waveguide edges of the silicon photonic chip and connected to an external optical power meter, while the remaining optical fiber is coupled with the test waveguide edge of the silicon photonic chip and connected to an external light source. Then, the end-to-end insertion loss test can be started. When testing the silicon photonic chip with this structure, since only one fiber array is coupled, compared with the existing technology, one fiber array can be used less, which effectively improves the test efficiency and facilitates mass production testing.

[0008] When the wafer is cleaved into bars, only one five-channel 8° inclined optical fiber array can be used to test the complete insertion loss of each chip, which can effectively improve the test efficiency and facilitate mass production testing.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, four light-emitting waveguides and one test waveguide are arranged side by side with equal spacing at an angle of 8°.

[0011] Furthermore, the incident light splitting ratio of the 2×2 coupler is 2:98, the input waveguide of the 2×2 coupler that accounts for 2% of the incident light is connected to the test waveguide, and the input waveguide that accounts for 98% of the incident light is connected to the optical waveguide.

[0012] Furthermore, the light output splitting ratio of the 2×2 coupler is 50:50, and the 1×2 coupler is a 1×2 equal-ratio light output coupler.

[0013] Furthermore, the silicon photonic chip also includes: five grating couplers integrated on the top surface of the chip and distributed side by side, the input waveguides of four of the five grating couplers are respectively connected one by one with the four output waveguides common to the two 1×2 couplers, and the output waveguide of the remaining grating coupler intersects with the test waveguide and an input waveguide of the 2×2 coupler at one point.

[0014] The further beneficial effects of adopting the above are:

[0015] When testing the internal insertion loss of silicon photonics chips at the wafer level, a five-channel 8° slanted fiber array is equipped. The four grating couplers corresponding to the light output of the five grating couplers are coupled with the four optical fibers in the five-channel 8° slanted fiber array, and an optical power meter is externally connected. The remaining one of the five grating couplers is coupled with the remaining one optical fiber in the five-channel 8° slanted fiber array, and an external light source is connected. Then, the internal insertion loss can be tested, which is convenient for mass production testing. However, existing silicon photonics chips cannot be tested at the wafer level due to structural limitations.

[0016] Furthermore, the splitting ratio of the light output by the output waveguide of each 1×2 coupler into the grating coupler and the light output waveguide is 2:98.

[0017] Furthermore, the five grating couplers are distributed at equal intervals.

[0018] Based on the above technical solution, the utility model also provides a 400G DR4 silicon photonic module, including the above silicon photonic chip.

[0019] Furthermore, the 400G DR4 silicon photonic module also includes: a four-channel 8° inclined optical fiber array and an optical transmission component. The four output waveguides of the silicon photonic chip are edge-coupled with the four-channel 8° inclined optical fiber array, and the input waveguide of the silicon photonic chip is edge-coupled with the optical transmission component.

[0020] Furthermore, the optical emission component includes: a laser chip, a collimating lens, an optical isolator and a converging lens coupled in sequence along the light propagation direction, and the laser chip is fixed on a ceramic heat sink. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural diagram of a silicon photonic chip in the prior art;

[0022] Figure 2 This is a test diagram of edge coupling of a single silicon photonic chip in the prior art;

[0023] Figure 3 This is a structural diagram of the silicon photonic chip in the utility model;

[0024] Figure 4 This is a side coupling test diagram of a single silicon photonic chip in the present utility model;

[0025] Figure 5 This is the edge coupling test diagram of silicon photonic chip in the wafer cleavage bar stage;

[0026] Figure 6 This is the structure diagram of the wafer stage;

[0027] Figure 7 This is the coupling test diagram of silicon photonic chip at the wafer stage;

[0028] Figure 8 This is a structural diagram of the 400G DR4 silicon photonic module in the present invention.

[0029] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0030] 1. Silicon photonic chip, 110. 2×2 coupler, 120. 1×2 coupler, 130. Input light waveguide, 140. Output light waveguide, 150. Test waveguide, 160. Grating coupler, 2. Four-channel 8° inclined optical fiber array, 3. Optical emission component, 310. Laser chip, 320. Collimating lens, 330. Optical isolator, 340. Converging lens, 350. Ceramic heat sink. DETAILED DESCRIPTION

[0031] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0032] Example 1

[0033] like Figure 3 As shown, a silicon photonic chip includes: a 2×2 coupler 110, two 1×2 couplers 120, an input light waveguide 130, four output light waveguides 140, and a test waveguide 150 integrated inside the chip, wherein the input light waveguide 130, the four output light waveguides 140, and the test waveguide 150 are located on the same side of the silicon photonic chip 1, and the four output light waveguides 140 and the test waveguide 150 are arranged side by side in an inclined manner of 8°;

[0034] The two input waveguides of the 2×2 coupler 110 are connected to the optical waveguide 130 and the test waveguide 150 respectively, and the two output waveguides of the 2×2 coupler 110 are connected to the input waveguides of the two 1×2 couplers 120 respectively, and the four output waveguides shared by the two 1×2 couplers 120 are connected to the four optical output waveguides 140 one by one.

[0035] like Figure 4 As shown, if the insertion loss of a single silicon photonic chip 1 is tested to be qualified, a five-channel 8° inclined optical fiber array is equipped, four optical fibers in the five-channel 8° inclined optical fiber array are coupled with the four light output waveguides 140 of the silicon photonic chip 1, and an optical power meter is externally connected, and the remaining optical fiber is coupled with the test waveguide 150 of the silicon photonic chip 1, and an external light source is connected, and then the end-to-end insertion loss can be tested. When testing the silicon photonic chip 1 with this structure, since only one optical fiber array is coupled, compared with the prior art, one optical fiber array can be used to reduce the use of one, effectively improving the test efficiency and facilitating mass production testing;

[0036] like Figure 5As shown, when the wafer is cleaved into bars (that is, a single chip, similar to a single bar of chocolate, with multiple chips on each bar), only one five-channel 8° inclined optical fiber array can be equipped to test the complete insertion loss of each chip, which can also effectively improve the test efficiency and facilitate mass production testing.

[0037] Example 2

[0038] like Figure 3 As shown, this embodiment is a further improvement on the basis of embodiment 1, and the details are as follows:

[0039] The four light emitting waveguides 140 and one test waveguide 150 are arranged side by side with equal spacing at an angle of 8°. Since the four light emitting waveguides 140 and one test waveguide 150 are arranged with equal spacing, a standard five-channel 8° inclined optical fiber array can be used for testing.

[0040] Furthermore, the incident light splitting ratio of the 2×2 coupler 110 is 2:98, the input waveguide of the 2×2 coupler 110 that accounts for 2% of the incident light is connected to the test waveguide 150 , and the input waveguide of the 2×2 coupler 110 that accounts for 98% of the incident light is connected to the optical waveguide 130 .

[0041] In addition, the light output splitting ratio of the 2×2 coupler 110 is 50:50, and the 1×2 coupler 120 is a 1×2 equal-ratio light output coupler.

[0042] Example 3

[0043] like Figure 3 As shown, this embodiment is a further improvement on the basis of Embodiment 1 or 2, and the details are as follows:

[0044] The silicon photonic chip 1 further includes: five grating couplers 160 integrated on the top surface of the chip and arranged side by side, the input waveguides of four grating couplers 160 of the five grating couplers 160 are respectively connected to the four output waveguides shared by the two 1×2 couplers 120 one by one, and the output waveguide of the remaining one grating coupler 160 of the five grating couplers 160 intersects the test waveguide 150 and one input waveguide of the 2×2 coupler 110 at one point;

[0045] like Figure 6 , Figure 7As shown, when testing the internal insertion loss of the silicon photonic chip 1 at the wafer level, only one five-channel 8° inclined optical fiber array is required. Four of the five grating couplers 160 that correspond to the light output are coupled with four optical fibers in the five-channel 8° inclined optical fiber array, and an optical power meter is externally connected. The remaining one of the five grating couplers 160 is coupled with the remaining one optical fiber in the five-channel 8° inclined optical fiber array, and an external light source is connected. Then, the internal insertion loss can be tested, which is convenient for mass production testing. However, the existing silicon photonic chip 1 cannot be tested at the wafer level due to structural influences.

[0046] Furthermore, the splitting ratio of the light output by the output waveguide of each 1×2 coupler 120 into the grating coupler 160 and the light output waveguide 140 is 2:98.

[0047] Example 4

[0048] like Figure 8 As shown, a 400G DR4 silicon photonic module includes a silicon photonic chip 1 as described in any one of embodiments 1 to 3.

[0049] Furthermore: the 400G DR4 silicon photonic module also includes: a four-channel 8° inclined optical fiber array 2 and an optical transmission component 3. The four output light waveguides 140 of the silicon photonic chip 1 are coupled with the four-channel 8° inclined optical fiber array 2, and the input light waveguide 130 of the silicon photonic chip 1 is coupled with the optical transmission component 3.

[0050] The optical emitting component 3 includes: a laser chip 310, a collimating lens 320, an optical isolator 330 and a converging lens 340 coupled in sequence along the light propagation direction. The laser chip 310 is fixed on a ceramic heat sink 350. The incoming light emitted by the laser chip 310 is coupled into the input light waveguide 130 of the silicon photonic chip 1 through the collimating lens 320, the optical isolator 330 and the converging lens 340 in sequence, and then is evenly divided into 4 paths through the silicon photonic chip 1, and then coupled into the four-channel 8° inclined optical fiber array 2 from the four output light waveguides 140.

[0051] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A silicon photonic chip, characterized in that: include: A 2×2 coupler (110) and two 1×2 couplers (120) are integrated inside a chip, and an input light waveguide (130), four output light waveguides (140) and a test waveguide (150) are integrated inside the chip and located on the same side, wherein the four output light waveguides (140) and the test waveguide (150) are arranged side by side in an inclined manner of 8°; the two input waveguides of the 2×2 coupler (110) are respectively connected to the input light waveguide (130) and the test waveguide (150), the two output waveguides of the 2×2 coupler (110) are respectively connected to the input waveguides of the two 1×2 couplers (120), and the four output waveguides commonly possessed by the two 1×2 couplers (120) are respectively connected to the four output light waveguides (140) one by one.

2. The silicon photonic chip according to claim 1, characterized in that: Four light-emitting waveguides (140) and one test waveguide (150) are arranged side by side with equal spacing at an angle of 8°.

3. The silicon photonic chip according to claim 1, characterized in that: The incident light splitting ratio of the 2×2 coupler (110) is 2:

98. The input waveguide of the 2×2 coupler (110) that accounts for 2% of the incident light is connected to the test waveguide (150), and the input waveguide that accounts for 98% of the incident light is connected to the optical waveguide (130).

4. The silicon photonic chip according to claim 3, characterized in that: The light output splitting ratio of the 2×2 coupler (110) is 50:50, and the 1×2 coupler (120) is a 1×2 equal-ratio light splitting coupler.

5. A silicon photonic chip according to any one of claims 1 to 4, characterized in that: Also includes: Five grating couplers (160) are integrated on the top surface of a chip and arranged side by side, and input waveguides of four grating couplers (160) of the five grating couplers (160) are respectively connected one by one with four output waveguides commonly possessed by two 1×2 couplers (120), and the output waveguide of the remaining grating coupler (160) intersects at one point with a test waveguide (150) and an input waveguide of a 2×2 coupler (110).

6. The silicon photonic chip according to claim 5, characterized in that: The splitting ratio of the light output by the output waveguide of each 1×2 coupler (120) into the grating coupler (160) and the light output waveguide (140) is 2:

98.

7. The silicon photonic chip according to claim 5, characterized in that: The five grating couplers (160) are distributed at equal intervals.

8. A 400G DR4 silicon photonic module, characterized in that: It comprises the silicon photonic chip (1) as claimed in any one of claims 1 to 7.

9. A 400G DR4 silicon photonic module according to claim 8, characterized in that: Also includes: A four-channel 8° inclined optical fiber array (2) and a light emitting component (3), wherein the four light output waveguides (140) of the silicon photonic chip (1) are edge-coupled with the four-channel 8° inclined optical fiber array (2), and the light input waveguide (130) of the silicon photonic chip (1) is edge-coupled with the light emitting component (3).

10. A 400G DR4 silicon photonic module according to claim 9, characterized in that: The light emitting component (3) comprises: a laser chip (310), a collimating lens (320), an optical isolator (330) and a converging lens (340) which are sequentially coupled along a light propagation direction; the laser chip (310) is fixed on a ceramic heat sink (350).

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