Boundary scanning controller

Abstract

The utility model discloses a boundary scan controller which comprises an XAVIER master control module, a boundary scan module, two JTAG interface connectors JTAG1 and JTAG2, an IO interface connector and a PSU power supply configuration module. The XAVIER main control module is connected with the boundary scanning module through an FPGA, I2C communication and a common IO, the boundary scanning module is connected with a JTAG1 and a JTAG2 through four lines, the boundary scanning module is connected with the IO interface connector through the common IO, and the PSU power supply configuration module is connected with the boundary scanning module and used for supplying power to the boundary scanning module. According to the utility model, the Ethernet port is adopted for communication, so that boundary scanning has wide applicability, high-speed transmission and flexibility, meanwhile, the SD card is adopted for storage, wide compatibility, relatively low power consumption and higher transmission rate are achieved, and the two groups of JTAG interfaces are connected to provide access to IO of a scan chain, so that the boundary scanning speed is improved. And the requirement on physical test points on the circuit board can be eliminated or greatly reduced, so that the cost is remarkably saved.

Description

Technical Field

[0001] The utility model relates to the technical field related to electronic testing, in particular to a boundary scanning controller. Background Art

[0002] In circuit design and testing, boundary scan is a test method used to detect and configure integrated circuit (IC) pins. It is a test architecture defined by IEEE standard 1149.1, also known as the JTAG (Joint Test Action Group) standard. Therefore, boundary scan technology relies on the JTAG link for signal transmission and control operations. If the link is open or shorted, it may cause the test operation to fail or the results to be unreliable, which in turn leads to communication interruption and communication errors. Utility Model Content

[0003] In order to solve the defects in the prior art, the utility model provides a boundary scan controller.

[0004] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0005] The utility model discloses a boundary scan controller, comprising a XAVIER main control module, a boundary scan module, two-way JTAG interface connectors JTAG1 and JTAG2, an IO interface connector and a PSU power supply configuration module;

[0006] The XAVIER main control module is connected to the boundary scan module through FPGA, I2C communication, and ordinary IO respectively. The boundary scan module is connected to JTAG1 and JTAG2 through 4 lines. The boundary scan module is connected to the IO interface connector through ordinary IO. The PSU power configuration module is connected to the boundary scan module for powering it.

[0007] As a preferred technical solution of the utility model, the XAVIER main control module transmits signals with the DAC digital-to-analog conversion module on the XAVIER main control module through the I2C communication protocol, and the XAVIER main control module transmits signals with the ADC analog-to-digital conversion module on the XAVIER main control module through the SPI communication protocol.

[0008] As a preferred technical solution of the utility model, the PSU power configuration module includes a DC power input terminal, a first buck chip and a second buck chip, and the input terminals of the first buck chip and the second buck chip are both connected to the DC power input terminal, and the output terminal of the first buck chip is connected to the XAVIER main control module, and the input terminal of the second buck chip is divided into 1.8V and 3.3V through the LDO chip, and supplies power to other modules.

[0009] As a preferred technical solution of the present invention, the DAC digital-to-analog conversion module is of model AD5667.

[0010] As a preferred technical solution of the utility model, the boundary scan module also has a level conversion circuit, a photoelectric coupling circuit, and a drive IO group.

[0011] The beneficial effects of the utility model are:

[0012] This type of boundary scan controller uses Ethernet port communication, which makes the boundary scan have wide applicability, high-speed transmission and flexibility, wide compatibility, relatively low power consumption and higher transmission rate. The two sets of JTAG interface connections can eliminate or greatly reduce the need for physical test points on the circuit board by providing access to the IO of the scan chain, which will significantly save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0014] Figure 1 This is a principle block diagram of a boundary scan controller of the utility model;

[0015] Figure 2 This is a schematic diagram of the structure of a PSU power supply configuration module of a boundary scan controller of the utility model;

[0016] Figure 3 The utility model is an I2C communication protocol architecture diagram of a boundary scan controller.

[0017] In the figure: 1. XAVIER main control module; 2. Boundary scan module; 3. IO interface connector; 4. PSU power configuration module; 5. DC power input terminal; 6. First step-down chip; 7. Second step-down chip. DETAILED DESCRIPTION

[0018] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0019] Example: Figure 1-3 As shown, the utility model is a boundary scan controller, comprising a XAVIER main control module 1, a boundary scan module 2, two JTAG interface connectors JTAG1 and JTAG2, an IO interface connector 3 and a PSU power supply configuration module 4;

[0020] The XAVIER main control module 1 is connected to the boundary scan module 2 through FPGA, I2C communication, and ordinary IO respectively. The boundary scan module 2 is connected to JTAG1 and JTAG2 through 4 lines. The boundary scan module 2 is connected to the IO interface connector 3 through ordinary IO. The PSU power configuration module 4 is connected to the boundary scan module 2 for powering it.

[0021] The XAVIER main control module transmits signals with the DAC digital-to-analog conversion module on the XAVIER main control module 1 through the I2C communication protocol, and the XAVIER main control module transmits signals with the ADC analog-to-digital conversion module on the XAVIER main control module 1 through the SPI communication protocol. The Ethernet network port communication is adopted to make the boundary scan have wide applicability, high-speed transmission and flexibility. At the same time, the SD card is used for storage, which has wide compatibility, relatively low power consumption and higher transmission rate. The two sets of JTAG interface connections can eliminate or greatly reduce the need for physical test points on the circuit board by providing access to the IO of the scan chain, which will significantly save costs.

[0022] Among them, the PSU power configuration module 4 includes a DC power input terminal 5, a first buck chip 6 and a second buck chip 7, and the input terminals of the first buck chip 6 and the second buck chip 7 are both connected to the DC power input terminal 5, and the output terminal of the first buck chip 6 is connected to the XAVIER main control module 1, and the input terminal of the second buck chip 7 is divided into 1.8V and 3.3V through the LDO chip, and supplies power to other modules.

[0023] Wherein, the DAC digital-to-analog conversion module is AD5667 model.

[0024] The boundary scanning module also has a level conversion circuit, a photoelectric coupling circuit, and a driving IO group.

[0025] The I2C protocol in the boundary scan controller communicates with the EPPROM and DAC respectively by the XAVIER main control chip through different address configurations. Using this protocol in the EPPROM allows the microcontroller to read or write data in the memory for configuration parameters, storage of calibration data, etc. At the same time, I2C supports multiple devices on the same bus, and each device is identified by a unique address, which makes it more convenient to use multiple DAC modules in the same system because each DAC can have a unique I2C address. The DAC analog-to-digital conversion module is the ADS1263 model, the optocoupler module is the TLP293-4 model, the driver IO module is the SN65LBC176A model, and the level conversion module is the LSF0102DCUR model.

[0026] The ADC analog-to-digital conversion circuit adopts differential input, and the ADC can measure the voltage difference between the two input terminals at the same time. This method has a certain effect on measuring the difference between signals, especially in a noisy environment, and can offset the common mode noise, that is, the noise that affects the two input terminals at the same time. The output of the ADC chip is connected to the XAVIER main control chip through the SPI communication protocol. SPI is a synchronous serial communication protocol that allows multiple devices to communicate in full duplex through four wires and also supports higher rates. When it is necessary to quickly read analog signals from the ADC and digitize them, the high-speed performance of SPI is more suitable.

[0027] The driving IO group drives the voltage to enhance the stability of the signal. At the same time, each driver chip has a matching resistor. If there is an error in the circuit communication, the resistor can be modified for adjustment. In addition, two groups of connectors are included, each of which is equipped with a JTAG interface and an IO expansion interface. The standard JTAG interface is 4-wire, which are mode selection, clock, data input and data output lines. The JTAG pin used also has TRST, which is an optional pin and serves as the input pin for test reset. One end of the IO expansion port is connected to the input pin of the ADC, and the other end is connected to the output pin of the DAC.

[0028] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A boundary scan controller, characterized in that: It includes a XAVIER main control module (1), a boundary scan module (2), two JTAG interface connectors JTAG1 and JTAG2, an IO interface connector (3) and a PSU power configuration module (4); The XAVIER main control module (1) is connected to the boundary scan module (2) via FPGA, I2C communication, and ordinary IO respectively; the boundary scan module (2) is connected to JTAG1 and JTAG2 via 4 lines; the boundary scan module (2) is connected to the IO interface connector (3) via ordinary IO; and the PSU power configuration module (4) is connected to the boundary scan module (2) for supplying power thereto.

2. A boundary scan controller according to claim 1, characterized in that: The XAVIER main control module performs signal transmission with the DAC digital-to-analog conversion module on the XAVIER main control module (1) via the I2C communication protocol, and the XAVIER main control module performs signal transmission with the ADC analog-to-digital conversion module on the XAVIER main control module (1) via the SPI communication protocol.

3. A boundary scan controller according to claim 1, characterized in that: The PSU power configuration module (4) comprises a DC power input terminal (5), a first buck chip (6) and a second buck chip (7), wherein the input terminals of the first buck chip (6) and the second buck chip (7) are both connected to the DC power input terminal (5), and the output terminal of the first buck chip (6) is connected to the XAVIER main control module (1), and the input terminal of the second buck chip (7) is divided into 1.8V and 3.3V via an LDO chip, and supplies power to other modules.

4. A boundary scan controller according to claim 2, characterized in that: The DAC digital-to-analog conversion module is model AD5667.

5. A boundary scan controller according to claim 1, characterized in that: The boundary scanning module also has a level conversion circuit, a photoelectric coupling circuit, and a driving IO group.

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