Wafer level packaging power device chip and battery management system

Abstract

The utility model provides a wafer level packaging power device chip and a battery management system. The wafer level packaging power device chip comprises a plurality of charge and discharge MOSFETs and a plurality of pad windows prepared on the same wafer, the plurality of pad windows are arranged on one surface of the chip, and a drain pad, a first gate pad and a second gate pad respectively occupy at least one pad window. And the first source electrode bonding pad and the second source electrode bonding pad respectively occupy at least one bonding pad window, so that the first source electrode bonding pad and the second source electrode bonding pad are directly contacted with the circuit board through the bonding pad windows, and source region current of the charging and discharging MOSFET is uniformly guided to the electrodes of the circuit board.

Description

Technical Field

[0001] The present disclosure relates to a wafer-level packaged power device chip and a battery management system. Background Art

[0002] In the prior art, it is necessary to control the charge and discharge of the battery pack. Since the charge and discharge current is large, it is necessary to improve the heat dissipation efficiency. In addition, when multiple transistors are used as charge and discharge control transistors, it is difficult for multiple transistors to achieve current balance from the current inflow end to the current outflow end. Utility Model Content

[0003] In order to solve one of the above technical problems, the present disclosure provides a wafer-level packaged power device chip and a battery management system.

[0004] According to one aspect of the present disclosure, a wafer-level packaged power device chip is provided, comprising: a plurality of charge and discharge MOSFETs prepared on the same wafer, wherein the plurality of charge and discharge MOSFETs include N charge and discharge MOSFET pairs connected in parallel, wherein N≥1, each charge and discharge MOSFET pair includes a first charge and discharge MOSFET and a second charge and discharge MOSFET connected in series, the source of the first charge and discharge MOSFET is connected to a first source pad, the source of the second charge and discharge MOSFET is connected to a second source pad, the drains of the first charge and discharge MOSFET and the second charge and discharge MOSFET are connected to a drain pad, the gates of the first charge and discharge MOSFET are connected to a first gate pad, and the gates of the second charge and discharge MOSFET are connected to a second gate pad; a plurality of pad openings, the plurality of pad openings are arranged on a surface of the chip, wherein the drain pad, the first gate pad, and the second gate pad each occupy at least one pad opening, and the first source pad and the second source pad each occupy at least one pad opening, so that the first source pad and the second source pad are in direct contact with a circuit board through the pad openings, and the source current of the charge and discharge MOSFET is evenly directed to the circuit board electrode.

[0005] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the first source pad and the second source pad each occupy more than two pad windows.

[0006] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the current, voltage and heat of the wafer-level packaged power device chip can be transmitted to the circuit board through the solder joints between the chip and the circuit board.

[0007] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the withstand voltage values ​​of the drain pad and the first source pad, and the withstand voltage values ​​of the drain pad and the second source pad are respectively set to be the same, 60-200V.

[0008] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the same wafer is also prepared with M pairs of pre-charge and discharge MOSFETs, each pre-charge and discharge MOSFET pair includes a first pre-charge and discharge MOSFET and a second pre-charge and discharge MOSFET connected in series, the drains of the first pre-charge and discharge MOSFET and the second pre-charge and discharge MOSFET of each pre-charge and discharge MOSFET pair are connected to each other and connected to the drain pad, the source and gate of the first pre-charge and discharge MOSFET are respectively connected to their own pre-charge source pad and pre-charge gate pad, and each pre-charge source pad and pre-charge gate pad respectively occupies at least one pad opening.

[0009] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the same wafer is also prepared with a temperature detection element, the two ends of the temperature detection element are respectively connected to two temperature detection pads, and the temperature detection pad occupies at least one pad opening.

[0010] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the pad openings occupied by the pre-charge source pad and the pre-charge gate pad are peripheral pad openings among a plurality of pad openings.

[0011] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the pad windows other than the pad windows occupied by the drain pad, the first gate pad, the second gate pad, the pre-charge source pad, the pre-charge gate pad and the temperature detection pad are all occupied by the first source pad and the second source pad.

[0012] A wafer-level packaged power device chip according to at least one embodiment of the present disclosure includes a bulk silicon layer, in which a charge-discharge MOSFET and a pre-charge-discharge MOSFET are prepared.

[0013] According to at least one embodiment of the wafer-level packaged power device chip of the present disclosure, a front metal layer is arranged on the bulk silicon layer, at least a metal plating layer serving as a pad is arranged on the front metal layer, and an insulating layer is arranged on the periphery of the metal plating layer and on the front metal layer, or the insulating layer covers the edge of the metal plating layer and is arranged on the front metal layer.

[0014] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the temperature detection element is prepared in the bulk silicon layer or in the front metal layer.

[0015] According to at least one embodiment of the wafer-level packaged power device chip of the present disclosure, a polyimide layer is disposed on the insulating layer.

[0016] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, an under ball metal layer is disposed on the metal plating layer, and a ball metal layer is disposed on the under ball metal layer.

[0017] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the under-ball metal layer is a copper layer, and the ball metal layer is a tin layer and can be soldered to a circuit board electrode.

[0018] According to at least one embodiment of the wafer-level packaged power device chip of the present disclosure, a back-sealing layer or a back-adhesive layer is disposed below the bulk silicon layer, or the back-sealing layer and the back-adhesive layer are disposed in sequence.

[0019] According to at least one embodiment of the present disclosure, the wafer-level packaged power device chip is soldered to the circuit board electrode in an inverted manner.

[0020] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, a terminal isolation ring is provided near the drain pad to enable the drain to be led out from the one surface.

[0021] According to the wafer-level packaged power device chip of at least one embodiment of the present disclosure, the pad openings are arranged in an array on one surface of the chip.

[0022] According to another aspect of the present disclosure, a battery management system is provided, comprising: a wafer-level packaged power device chip as described in any one of the above items; a circuit board, wherein a first source pad and a second source pad of the wafer-level packaged power device chip are connected to a negative side line or a positive side line of a battery pack via the circuit board; and a driving unit, wherein the driving unit provides a driving signal to a first gate terminal pad and a second gate short pad connected to the circuit board via the circuit board, so as to control the conduction and disconnection of a charge and discharge MOSFET, thereby controlling the charge and discharge of the battery pack. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0024] Figure 1 It is a circuit diagram of a wafer-level packaged power device chip according to an embodiment of the present disclosure.

[0025] Figure 2 is a schematic diagram of a battery management system according to one embodiment of the present disclosure.

[0026] Figure 3It is a schematic diagram of the appearance of a wafer-level packaged power device chip according to an embodiment of the present disclosure.

[0027] Figure 4 It is a schematic cross-sectional view of a PAD window of a wafer-level packaged power device chip according to an embodiment of the present disclosure.

[0028] Figure 5 It is a schematic diagram of a PAD window cross-sectional view of a DM pad of a wafer-level packaged power device chip according to an embodiment of the present disclosure.

[0029] Figure 6 It is a schematic diagram of a PAD window cross-section of a temperature detection pad of a wafer-level packaged power device chip according to an embodiment of the present disclosure.

[0030] Figure 7 It is a schematic diagram of wafer-level packaged power device chip and circuit board installation according to an embodiment of the present disclosure.

[0031] Figure 8 is a schematic diagram of current flow according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] The present disclosure is further described in detail below in conjunction with the accompanying drawings and implementations. It is understood that the specific implementations described herein are only used to explain the relevant content, rather than to limit the present disclosure. It should also be noted that, for ease of description, only the parts related to the present disclosure are shown in the accompanying drawings.

[0033] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] Unless otherwise specified, the exemplary embodiments / embodiments shown will be understood as providing exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features of the various embodiments / embodiments can be combined, separated, interchanged and / or rearranged without departing from the technical concept of the present disclosure.

[0035] The use of cross-hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same figure numbers represent the same components.

[0036] When a component is referred to as being "on" or "over," "connected to," or "coupled to" another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there are no intervening components. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0037] For descriptive purposes, the present disclosure may use spatially relative terms such as "under," "beneath," "under," "down," "over," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, components described as "under" or "beneath" other components or features would subsequently be positioned "over" the other components or features. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0038] The terms used here are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used here, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, it is explained that there are stated features, integral bodies, steps, operations, parts, assemblies and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups. It should also be noted that, as used here, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values ​​and / or the values ​​provided that will be recognized by those of ordinary skill in the art.

[0039] According to one embodiment of the present application, a wafer-level packaged power device chip is provided. Figure 1 A circuit diagram of a power device chip according to an embodiment of the present application is shown.

[0040] like Figure 1 As described above, the power device chip 100 may include a plurality of metal-oxide semiconductor field effect transistors (MOSFETs) as charge and discharge MOSFETs in a battery management system. Figure 1 Eight charge and discharge MOSFETs M1-M8 are shown in the figure. The number of charge and discharge MOSFETs can be 2N, where N≥1 and is a positive integer. The 2N charge and discharge MOSFETs can be divided into N pairs, and the two charge and discharge transistors in each pair can be connected in series, and multiple charge and discharge MOSFET pairs are connected in parallel. For example, M1 and M2 are connected in series to form the first charge and discharge MOSFET pair, M3 and M4 are connected in series to form the second charge and discharge MOSFET pair, M5 and M6 are connected in series to form the third charge and discharge MOSFET pair, and M7 and M8 are connected in series to form the fourth charge and discharge MOSFET pair. The first to fourth pairs of charge and discharge MOSFETs are connected in series to form a charge and discharge MOSFET module in the battery management system.

[0041] Each of the N charge-discharge MOSFET pairs includes a first charge-discharge MOSFET and a second charge-discharge MOSFET. In each charge-discharge MOSFET pair, the drain of the first charge-discharge MOSFET is connected to the drain of the second charge-discharge MOSFET. The sources of the first charge-discharge MOSFETs of each charge-discharge MOSFET pair are connected, and the sources of the second charge-discharge MOSFETs of each charge-discharge MOSFET pair are connected. The gates of the first charge-discharge MOSFETs of each charge-discharge MOSFET pair are connected, and the gates of the second charge-discharge MOSFETs of each charge-discharge MOSFET pair are connected. Figure 1, the first charge and discharge MOSFETs are M1, M3, M5, and M7, and the second charge and discharge MOSFETs are M2, M4, M6, and M8. The drain of the first charge and discharge MOSFET in each charge and discharge MOSFET pair is connected to the drain of the second charge and discharge MOSFET and then connected to the drain pad (PAD) DM. The gates of the first charge and discharge MOSFETs are connected and then connected to the first gate pad G1M. The gates of the second charge and discharge MOSFETs are connected and then connected to the second gate pad G2M. The sources of the first charge and discharge MOSFETs are connected and then connected to the first source pad S1M. The sources of the second charge and discharge MOSFETs are connected and then connected to the second source pad S2M.

[0042] Figure 2 The application schematic diagram of the wafer-level packaged power device chip according to the present disclosure is shown. The power device chip can be used to control the charging and discharging of the battery. The power device chip can be set on the negative voltage side circuit of the battery or on the positive voltage side circuit of the battery. The figure shows the situation on the negative voltage side. The front-end acquisition unit can be used to collect the voltage of the battery pack, etc., and provide it to the control unit, and the control unit can provide a signal to the drive unit. The drive unit provides a drive signal to the power device chip through the first gate pad and the second gate pad to control the conduction or disconnection of the charge and discharge transistor. The first source pad and the second source pad of the power device chip can be connected in the charge and discharge circuit.

[0043] The charge and discharge MOSFET can be a three-port MOSFET, including a gate, a drain and a source, or a four-port MOSFET, including a gate, a separate gate, a source and a drain. Figure 1 A four-port MOSFET is shown in the figure, wherein the separated gates of the first charge and discharge MOSFETs of each charge and discharge MOSFET pair are connected together and connected to the first separated gate pad SG1M, and the separated gates of the second charge and discharge MOSFETs of each charge and discharge MOSFET pair are connected together and connected to the second separated gate pad SG2M.

[0044] The wafer-level packaged power device chip may further include pre-charge and discharge MOSFETs, the number of which is M pairs, where M≥2, and each pair of pre-charge and discharge MOSFETs includes two pre-charge and discharge MOSFETs connected in parallel. Figure 1As shown, the wafer-level packaged power device chip includes two pre-charge and discharge MOSFET pairs, wherein the first pre-charge and discharge MOSFET pair may include a first pre-charge and discharge MOSFET M1A and a second pre-charge and discharge MOSFET M2A, and the second pre-charge and discharge MOSFET pair may include a first pre-charge and discharge MOSFET M1B and a second pre-charge and discharge MOSFET M2B. The drains of the first pre-charge and discharge MOSFET M1A and the second pre-charge and discharge MOSFET M2A may be connected together, and may be connected to the drain of the charge and discharge MOSFET, and then connected to the drain pad DM. The drains of the first pre-charge and discharge MOSFET M1B and the second pre-charge and discharge MOSFET M2B may be connected together, and may be connected to the drain of the charge and discharge MOSFET, and then connected to the drain pad DM. The source of the first pre-charge and discharge MOSFET M1A may be connected to the third source pad S1ALC, and the gate may be connected to the third gate pad G1ALC. The source of the second pre-charge and discharge MOSFET M2A may be connected to the fourth source pad S2ALC, and the gate may be connected to the fourth gate pad G2ALC. The source of the first pre-charge and discharge MOSFET M1B may be connected to the fifth source pad S1BLC, and the gate may be connected to the fifth gate pad G1BLC. The source of the second pre-charge and discharge MOSFET M2B may be connected to the sixth source pad S2BLC, and the gate may be connected to the sixth gate pad G2BLC. It should be understood that although Figure 1 Two pre-charge and discharge MOSFET pairs are shown in FIG, but other numbers of pre-charge and discharge MOSFET pairs may also be selected.

[0045] In addition, the wafer-level packaged power device chip may also include a thermistor, such as Figure 1 Thermistors R1 and R2 are shown, where thermistors can be used to detect the temperature of the module. In addition, a diode can also be used for temperature detection. In addition, other temperature detection elements can also be used. The two ends of the thermistor R1 are respectively connected to the first temperature detection pad NTC1P and the second temperature detection pad NTC1N, and the two ends of the thermistor R2 are respectively connected to the third temperature detection pad NTC2P and the fourth temperature detection pad NTC2N.

[0046] Figure 3 The schematic diagram of the surface of a wafer-level packaged power device chip is shown. In this surface, a plurality of pad openings (PAD openings) 310 are provided on an insulating layer 320. The insulating layer 320 may be one or more layers of an oxide layer, a nitride layer, a nitride oxide layer, a polyimide layer, etc. The pad openings 310 may be arranged in an array on the surface of the chip and the sizes of the pad openings 310 may be the same or different.

[0047] In the present application, the drain pad DM, the first gate pad G1M, the second gate pad G2M, the first separated gate pad SG1M, the second separated gate pad SG2M, the third source pad S1ALC, the third gate pad G1ALC, the fourth source pad S2ALC, the fourth gate pad G2ALC, the fifth source pad S1BLC, the fifth gate pad G1BLC, the sixth source pad S2BLC, the sixth gate pad G2BLC, the first temperature detection pad NTC1P, the second temperature detection pad NTC1N, the third temperature detection pad NTC2P and the fourth temperature detection pad NTC2N can respectively occupy one pad window of multiple pad openings. Among them, preferably, the third source pad S1ALC, the third gate pad G1ALC, the fourth source pad S2ALC, the fourth gate pad G2ALC, the fifth source pad S1BLC, the fifth gate pad G1BLC, the sixth source pad S2BLC, and the sixth gate pad G2BLC occupy the peripheral pad openings, that is, the occupied pad openings are peripheral pad openings. The first source pad S1M and the second source pad S2M occupy the remaining pad openings. In addition, the first temperature detection pad NTC1P, the second temperature detection pad NTC1N, the third temperature detection pad NTC2P, and the fourth temperature detection pad NTC2N can respectively occupy n pad openings and be evenly distributed, where n≥1.

[0048] The specific structure of the pad window will be described in detail below, wherein the upper cross-section and lower cross-section methods are described separately. Figure 4 A schematic diagram of a cross-sectional structure of a pad opening is shown. Figure 4 The top of the figure shows three embodiments of the upper cross section, and the bottom shows three embodiments of the lower cross section. They can be combined arbitrarily, so Figure 4 A total of nine specific structures of the embodiments are shown.

[0049] In the first embodiment of the upper cross section, the insulating layer 410 can be arranged to surround the pad opening and the pad opening is provided with a metal plating layer 450, and the front metal layer 420 is arranged under the metal plating layer 450. In addition, the insulating layer can also cover the edge of the metal plating layer. In this way, the insulating layer can be arranged on the periphery of the metal plating layer, and can also cover the edge of the metal plating layer. In the second embodiment of the upper cross section, the difference from the first embodiment is that a polyimide layer 480 is also provided, wherein the polyimide layer 480 is arranged on the insulating layer and can cover the peripheral part of the metal plating layer 450 or not cover the metal plating layer 450. In the third embodiment of the upper cross section, the difference from the second embodiment is that a ball-under metal layer 460 is arranged on the front metal layer 420, and a ball metal layer 490 can also be arranged on the ball-under metal layer 460. Among them, the insulating layer 410 and the front metal layer 420 are arranged on the bulk silicon layer 440.

[0050] In the first embodiment of the lower cross section, a backing layer 470 is disposed under the bulk silicon layer 440. In the second embodiment of the lower cross section, the difference from the first embodiment is that a backing layer 430 is further disposed under the backing layer 470. In the third embodiment of the lower cross section, a backing layer 430 is disposed under the bulk silicon layer 440.

[0051] In addition, the specific structure and doping method are not shown in the cross-sectional bulk silicon layer, and the specifics can be referred to the prior art of manufacturing the device. The back seal layer can be an oxide layer, a multi-gold layer, and a multi-layer superposition structure thereof. The front metal layer can be an aluminum layer, or an aluminum-copper layer, or an aluminum-silicon-copper layer. The metal plating layer can be a nickel-palladium-gold layer, or a nickel-gold layer, or a titanium-copper layer. The metal layer under the ball can be a copper layer. The ball metal layer can be a tin layer.

[0052] Figure 5 The lead-out method of the drain pad DM is shown, and a terminal isolation ring can be used to realize the positive lead-out of the drain. The terminal isolation ring not only protects the edge of the high-voltage MOSFET from the influence of the electric field concentration effect, but also ensures that the drain can be safely and effectively led out without destroying the overall electrical isolation performance.

[0053] Figure 6 The first temperature detection pad NTC1P, the second temperature detection pad NTC1N, the third temperature detection pad NTC2P and the fourth temperature detection pad NTC2N can be connected by Figure 6 way. Figure 6 Thermistors and diodes are shown in the figure. Thermistors can be formed by metal and polysilicon. In the present application, the temperature detection element can be prepared in the bulk silicon layer or in the metal plating layer.

[0054] According to the wafer-level packaged power device chip of the present application, the withstand voltage values ​​between the pads can be as follows: DM and S1M withstand voltage 60-200V; DM and S2M withstand voltage 60-200V; DM and S1ALC withstand voltage 60-200V; DM and S2ALC withstand voltage 60-200V; DM and S1BLC withstand voltage 60-200V; DM and S2BLC withstand voltage 60-200V. In this way, the withstand voltage values ​​between the above pads can be consistent on one chip.

[0055] In this application, the wafer-level packaged power device chip can be attached to the circuit board by flip-chip bonding. Figure 7 A schematic diagram of flip chip mounting is shown. Figure 4 Each of the embodiments can be attached to the circuit board in a flip-chip manner through the soldering layer.

[0056] In this application, the ratio of the package area to the wafer-level package power device chip area is 1:1. The small package size allows it to take up less space in the application and also helps to improve heat dissipation efficiency. Among them, the parasitic resistance is relatively low, which reduces heat generation. The parasitic resistance of this package is much lower than other package forms. The total resistance of the product is lower and heat is less.

[0057] The heat generated by the packaged chip during operation can be easily transferred to the PCB through the contact area between the solder joints and the PCB and dissipated. This heat dissipation method shortens the effective heat dissipation path and has higher heat dissipation efficiency. In addition, through the solder joints, the current and voltage of the packaged chip can also be transmitted to the circuit board through the solder joints.

[0058] The N pairs of charge and discharge MOSFETs in this packaged chip come from adjacent areas of the same wafer. Compared with discrete N pairs of MOS tubes, their parameters have no batch-to-batch differences and even smaller intra-chip differences. The S1M and S2M packages are in direct contact with the circuit board through multiple PAD openings. The contact resistance between each PAD opening and the circuit board is close, which can evenly guide the MOS source current to the circuit board electrode. Figure 8 The comparison between the packaged chip of the present application and the discrete structure is shown in FIG. The comparison between the packaged chip M and the discrete N pairs of MOSFETs at the application end (simplified diagram of 4 pairs of discrete MOS). In the case of discrete N pairs of MOSFETs, from the current path, the path length between the endpoint where the current enters and the discrete MOSFETs M1, M2, M3, and M4 is inconsistent, and the path length between the discrete MOSFETs M5, M6, M7, and M8 and the endpoint where the current goes out is inconsistent. However, the packaged current of the present application passes through M from the endpoint where the current enters to the endpoint where the current goes out, and the packaged chip has better current balancing in application than the discrete N pairs of MOS tubes.

[0059] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments / methods or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments / methods or examples described in this specification and the features of the different embodiments / methods or examples, unless they are contradictory.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0061] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications may be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A wafer-level packaged power device chip, characterized in that: include: A plurality of charge and discharge MOSFETs prepared on the same wafer, wherein the plurality of charge and discharge MOSFETs include N charge and discharge MOSFET pairs connected in parallel, wherein N ≥ 1, and each charge and discharge MOSFET pair includes a first charge and discharge MOSFET and a second charge and discharge MOSFET connected in series, the source of the first charge and discharge MOSFET is connected to the first source pad, the source of the second charge and discharge MOSFET is connected to the second source pad, the drains of the first charge and discharge MOSFET and the second charge and discharge MOSFET are connected to the drain pad, the gates of the first charge and discharge MOSFET are connected to the first gate pad, and the gates of the second charge and discharge MOSFET are connected to the second gate pad; A plurality of pad windows are provided on a surface of the chip, wherein the drain pad, the first gate pad and the second gate pad each occupy at least one pad window, and the first source pad and the second source pad each occupy at least one pad window, so that the first source pad and the second source pad are in direct contact with the circuit board through the pad windows, and the source current of the charge and discharge MOSFET is evenly guided to the circuit board electrode.

2. The wafer-level packaged power device chip according to claim 1, characterized in that: The first source pad and the second source pad each have more than two pad windows.

3. The wafer-level packaged power device chip according to claim 1, characterized in that: The current, voltage and heat of the wafer-level packaged power device chip can be transmitted to the circuit board through the solder joints between the chip and the circuit board.

4. The wafer-level packaged power device chip according to claim 1, characterized in that: The withstand voltage values ​​of the drain pad and the first source pad, and the drain pad and the second source pad are the same, which is set to 60-200V.

5. The wafer-level packaged power device chip according to claim 1, characterized in that: The same wafer is also prepared with M pairs of pre-charge and discharge MOSFETs, each pre-charge and discharge MOSFET pair includes a first pre-charge and discharge MOSFET and a second pre-charge and discharge MOSFET connected in series, the drains of the first pre-charge and discharge MOSFET and the second pre-charge and discharge MOSFET of each pre-charge and discharge MOSFET pair are connected to each other and to the drain pad, the source and gate of the first pre-charge and discharge MOSFET are respectively connected to their own pre-charge source pad and pre-charge gate pad, and each pre-charge source pad and pre-charge gate pad occupies at least one pad opening respectively.

6. The wafer-level packaged power device chip according to claim 5, characterized in that: The same wafer is also prepared with a temperature detection element, two ends of the temperature detection element are respectively connected to two temperature detection pads, and the temperature detection pad occupies at least one pad opening.

7. The wafer-level packaged power device chip according to claim 6, characterized in that: The pad openings occupied by the pre-charge source pad and the pre-charge gate pad are peripheral pad openings among the plurality of pad openings.

8. The wafer-level packaged power device chip according to claim 7, characterized in that: The pad windows other than the pad windows occupied by the drain pad, the first gate pad, the second gate pad, the pre-charge source pad, the pre-charge gate pad and the temperature detection pad are all occupied by the first source pad and the second source pad.

9. The wafer-level packaged power device chip according to any one of claims 6 to 8, characterized in that: It comprises a bulk silicon layer, in which a charge-discharge MOSFET and a pre-charge-discharge MOSFET are prepared.

10. The wafer-level packaged power device chip according to claim 9, characterized in that: A front metal layer is arranged on the bulk silicon layer, and at least a metal plating layer serving as a pad is arranged on the front metal layer, and an insulating layer is arranged on the periphery of the metal plating layer and on the front metal layer, or the insulating layer covers the edge of the metal plating layer and is arranged on the front metal layer.

11. The wafer-level packaged power device chip according to claim 10, characterized in that: The temperature detection element is prepared in the bulk silicon layer or in the front metal layer.

12. The wafer-level packaged power device chip according to claim 10, characterized in that: A polyimide layer is disposed on the insulating layer.

13. The wafer-level packaged power device chip according to claim 10, characterized in that: An under-ball metal layer is disposed on the metal plating layer, and a ball metal layer is disposed on the under-ball metal layer.

14. The wafer-level packaged power device chip according to claim 13, characterized in that: The under-ball metal layer is a copper layer, and the ball metal layer is a tin layer and can be soldered to a circuit board electrode.

15. The wafer-level packaged power device chip according to claim 9, characterized in that: A back-sealing layer or a back-adhesive layer is arranged below the bulk silicon layer, or the back-sealing layer and the back-adhesive layer are arranged in sequence.

16. The wafer-level packaged power device chip according to claim 15, characterized in that: The wafer-level packaged power device chip is soldered to the circuit board electrode in an inverted manner.

17. The wafer-level packaged power device chip according to claim 1, characterized in that: A terminal isolation ring is arranged near the drain pad to enable the drain to be led out from the one surface.

18. The wafer-level packaged power device chip according to claim 1, characterized in that: The pad openings are arranged in an array form on a surface of the chip.

19. A battery management system, characterized in that: include: The wafer-level packaged power device chip according to any one of claims 1 to 18; A circuit board, wherein the first source pad and the second source pad of the wafer-level packaged power device chip are connected to the negative electrode side circuit or the positive electrode side circuit of the battery pack via the circuit board; A driving unit provides a driving signal to a first gate terminal pad and a second gate short pad connected to the circuit board via the circuit board to control the on and off of the charge and discharge MOSFET, thereby controlling the charge and discharge of the battery pack.

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