Display device

Abstract

A display device includes: a plurality of light emitting devices each including a first electrode, a second electrode, and an intermediate layer disposed between the first electrode and the second electrode and including a light emitting layer; a pixel defining layer provided with a plurality of light emitting openings, each of the plurality of light emitting openings overlapping the light emitting layer of a corresponding one of the plurality of light emitting devices; a separator disposed on the pixel defining layer and provided with a plurality of separated openings respectively overlapping the plurality of light emitting openings; and at least one spacer disposed on the pixel defining layer. The second electrode of each of the plurality of light emitting devices may overlap with a corresponding one of the plurality of separation openings, and the plurality of light emitting devices are electrically separated from each other by the separator.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0060100 filed in the Korean Intellectual Property Office on May 9, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device with improved process reliability. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, computers (eg, tablet computers), navigation devices, and game devices include display devices that display images.

[0005] The display device includes a light emitting device and a circuit for driving the light emitting device. The light emitting device included in the display device emits light in response to a voltage applied thereto from the circuit, and generates an image. Research on the connection between the light emitting device and the circuit for improving the reliability of the display device is underway. In addition, research is underway to reduce defects occurring in the process and to improve the reliability of the display device. Utility Model Content

[0006] The present disclosure provides a display device with improved process reliability and reduced light emission defects.

[0007] Embodiments of the present invention provide a display device, which may include: a plurality of light-emitting devices, each including a first electrode, a second electrode, and an intermediate layer disposed between the first electrode and the second electrode and including a light-emitting layer; a pixel defining layer including a plurality of light-emitting openings, each of the plurality of light-emitting openings overlapping with a light-emitting layer of a corresponding one of the plurality of light-emitting devices; a partition disposed on the pixel defining layer and including a plurality of partition openings, each of the plurality of partition openings overlapping with a corresponding one of the plurality of light-emitting openings; and at least one spacer disposed on the pixel defining layer. The second electrode of each of the plurality of light-emitting devices may overlap with a corresponding one of the plurality of partition openings, and the plurality of light-emitting devices may be electrically separated from each other by the partition.

[0008] In a plan view, the at least one spacer may overlap a portion of the partition, or the at least one spacer may be disposed between the pixel defining layer and the partition.

[0009] In a plan view, an entire area of ​​the at least one spacer may overlap with the partition.

[0010] In a plan view, the at least one spacer may be partially exposed without being covered by the partition.

[0011] The spacer may include a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface and having a width greater than that of the lower surface in a cross-sectional view, and in a cross-sectional view, the at least one spacer may have a width equal to or greater than that of the lower surface of the spacer.

[0012] The spacer may include a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface, and the distance between the pixel defining layer and the upper surface of the spacer overlapping with the at least one spacer may be greater than the distance between the pixel defining layer and the upper surface of the spacer not overlapping with the at least one spacer.

[0013] The at least one spacer may be disposed on the partition, and an entire area of ​​the at least one spacer may overlap with the partition in a plan view.

[0014] The spacer may include a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface and having a width greater than a width of the lower surface in a cross-sectional view, and in a cross-sectional view, the at least one spacer may have a width equal to or less than a width of the upper surface of the spacer.

[0015] The divider may include divider grid lines defining a plurality of divider openings, the divider grid lines may include a plurality of first lines extending in a first direction and a plurality of second lines extending in a second direction, and the divider may include a plurality of intersections at which the plurality of first lines intersect with the plurality of second lines.

[0016] The at least one spacer may overlap one of the plurality of intersection portions.

[0017] The plurality of intersection portions may include: at least one first intersection portion having a cross shape in a plan view; and at least one second intersection portion having a T shape in a plan view.

[0018] The at least one spacer may overlap the at least one first intersection portion, and the at least one spacer may have a quadrilateral shape or a cross shape in a plan view.

[0019] The at least one first intersection portion may include: a first intersection area; a first-first line area and a first-second line area of ​​each of the plurality of first lines, extending from the first intersection area in opposite directions in the first direction; a second-first line area and a second-second line area of ​​each of the plurality of second lines, extending from the first intersection area in opposite directions in the second direction; and a first protruding area, protruding from corresponding line areas adjacent to each other among the first-first line area, the first-second line area, the second-first line area and the second-second line area, and the at least one spacer may overlap with at least a portion of each of the first intersection area, the first-first line area and the first-second line area, the second-first line area and the second-second line area and the first protruding area.

[0020] The at least one spacer may overlap the at least one second intersection portion, and the at least one spacer may have a quadrilateral shape, a T shape, or a triangular shape in a plan view.

[0021] The at least one second intersection portion may include: a second intersection area; a first-third line area of ​​each of the plurality of first lines, extending from the second intersection area in the first direction; a second-third line area and a second-fourth line area of ​​each of the plurality of second lines, extending from the second intersection area in opposite directions in the second direction; and a second protruding area, protruding from corresponding line areas adjacent to each other among the first-third line area, the second-third line area and the second-fourth line area, and the at least one spacer may overlap with at least a portion of each of the second intersection area, the first-third line area, the second-third line area, the second-fourth line area and the second protruding area.

[0022] The at least one first intersection portion may include a plurality of first intersection portions, the at least one second intersection portion may include a plurality of second intersection portions, the at least one spacer may include a plurality of spacers, and each of the plurality of first intersection portions and the plurality of second intersection portions may overlap with a corresponding one of the plurality of spacers.

[0023] The at least one first intersection portion may include a plurality of first intersection portions, the at least one second intersection portion may include a plurality of second intersection portions, the at least one spacer may include a plurality of spacers, some of the plurality of first intersection portions and some of the plurality of second intersection portions may respectively overlap with corresponding spacers in the plurality of spacers, and other first intersection portions in the plurality of first intersection portions and other second intersection portions in the plurality of second intersection portions may not overlap with any spacers in the plurality of spacers.

[0024] The at least one spacer may include a plurality of spacers, the plurality of spacers may include a first spacer and a second spacer, the first spacer may overlap with one of the plurality of intersections, and the second spacer may be spaced apart from each of the plurality of intersections and may overlap with one of the plurality of first lines and the plurality of second lines.

[0025] The separator may further include a bending portion, and the bending portion may include: a bending zone; a first to fourth line zone of each of the plurality of first lines, extending from the bending zone in the first direction; and a second to fifth line zone of each of the plurality of second lines, extending from the bending zone in the second direction.

[0026] In a plan view, the at least one spacer may overlap the bent portion.

[0027] The at least one spacer overlapping the bent portion may have an L-shape.

[0028] The at least one spacer may include a plurality of spacers, the plurality of spacers may include a first spacer and a second spacer, the first spacer may overlap with one of the plurality of intersecting portions, and the second spacer may be spaced apart from each of the plurality of intersecting portions and may overlap with the bending portion.

[0029] The at least one spacer may include a plurality of spacers, the plurality of spacers may include a first spacer and a second spacer, the first spacer may be spaced apart from the plurality of intersections and may overlap with one of the plurality of first lines and the plurality of second lines, and the second spacer may be spaced apart from the plurality of intersections and may overlap with the bending portion.

[0030] The at least one spacer may include a plurality of spacers, and each of the plurality of spacers may be spaced apart from each of the plurality of intersection portions and may overlap with one of the plurality of first lines and the plurality of second lines.

[0031] The at least one spacer may include an organic material.

[0032] The organic material may include polyimide.

[0033] The display device may further include: a first dummy layer, disposed on the partition and spaced apart from the intermediate layer of each of the plurality of light emitting devices, the first dummy layer and the intermediate layer of each of the plurality of light emitting devices may include the same material; and a second dummy layer, disposed on the first dummy layer and spaced apart from the second electrode of each of the plurality of light emitting devices, the second dummy layer and the second electrode of each of the plurality of light emitting devices may include the same material.

[0034] The display device may further include: a plurality of transistors, each of the plurality of transistors being electrically connected to a second electrode of a corresponding one of the plurality of light emitting devices; and a plurality of connection wirings, each of the plurality of connection wirings electrically connecting a corresponding one of the plurality of transistors to a second electrode of a corresponding one of the plurality of light emitting devices. Each of the plurality of connection wirings may include: a light emitting connection portion electrically connected to a second electrode of a corresponding one of the plurality of light emitting devices and spaced apart from a corresponding one of the plurality of light emitting openings; and a driver connection portion electrically connected to a corresponding transistor among the plurality of transistors.

[0035] According to the above, the at least one spacer can be arranged to overlap with the spacer that electrically disconnects the cathodes of the light-emitting devices from each other. Therefore, the defects of the spacer that occur in the process of forming the light-emitting layers of the plurality of light-emitting devices can be reduced. Accordingly, the process reliability can be improved, and a display device with reduced light emission defects can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other advantages of the present disclosure will become readily apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0037] Figure 1 is a schematic block diagram of a display device according to an embodiment of the present disclosure;

[0038] Figure 2A and Figure 2B is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure;

[0039] Figure 3A and Figure 3B is a plan view of a display panel according to an embodiment of the present disclosure;

[0040] FIG. 4A to FIG. 4C is an enlarged plan view of some areas of a display panel according to an embodiment of the present disclosure;

[0041] Figure 5 According to an embodiment of the present disclosure, Figure 4B A schematic enlarged cross-sectional view of a region of the display panel taken along line II';

[0042] Fig. 6A According to the embodiment of the present disclosure Figure 5 A schematic enlarged cross-sectional view of area AA of a display panel;

[0043] Figure 6B According to the embodiment of the present disclosure Figure 5 A schematic enlarged cross-sectional view of area BB of a display panel;

[0044] Figure 7According to an embodiment of the present disclosure, Figure 4B A schematic enlarged cross-sectional view of a region of the display panel taken along line II';

[0045] Figure 8 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0046] Fig. 9A According to an embodiment of the present disclosure, Figure 8 A schematic enlarged cross-sectional view of a region of the display panel taken along line II-II';

[0047] Fig. 9B According to an embodiment of the present disclosure, Figure 8 A schematic enlarged cross-sectional view of a region of the display panel taken along line III-III';

[0048] Fig. 10A According to an embodiment of the present disclosure, Figure 8 A schematic enlarged cross-sectional view of a region of the display panel taken along line II-II';

[0049] Fig. 10B According to an embodiment of the present disclosure, Figure 8 A schematic enlarged cross-sectional view of a region of the display panel taken along line III-III';

[0050] FIG. 11A to FIG. 11C is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0051] FIG. 12A to FIG. 12C is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0052] Fig.13 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0053] Fig.14 According to an embodiment of the present disclosure, Fig.13 A schematic enlarged cross-sectional view of a region of the display panel taken along line IV-IV';

[0054] Fig.15 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0055] Fig.16 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0056] Fig.17 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0057] Fig.18is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure;

[0058] Fig.19 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure; and

[0059] Fig. 20 is an enlarged plan view of a region of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the utility model. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be implemented without these specific details or with one or more equivalent arrangements. In this article, various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration and features of an embodiment can be used or implemented in another embodiment.

[0061] Unless otherwise specified, the embodiments shown should be understood to provide exemplary features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0062] The use of cross hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements, unless otherwise specified. Further, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same figure numerals and / or reference characters represent the same elements.

[0063] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or coupled to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without an intervening element. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to three axes of a rectangular coordinate system such as an x-axis, a y-axis, and a z-axis, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0064] Although the terms "first", "second", etc. can be used to describe various types of elements in this article, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0065] Spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes and thereby to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Further, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0066] The terms used in this article are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used in this article, the singular forms "one" and "the (said)" are also intended to include plural forms, unless the context clearly indicates otherwise. In addition, in the case of using in this specification, the terms "include", "comprise", "contain", and / or "have" indicate the existence of the described features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used in this article, the terms "substantially", "approximately" and other similar terms are used as approximate terms rather than degree terms, and therefore, are used to illustrate the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0067] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to specific illustrated shapes of regions, but will include shape deviations, for example, caused by manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and are therefore not necessarily intended to be limiting.

[0068] As is customary in the art, some embodiments are described and shown in the accompanying drawings with functional blocks, parts and / or modules. It will be appreciated by those skilled in the art that these blocks, parts and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, parts and / or modules are implemented by microprocessors or other similar hardware, these blocks, parts and / or modules can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, part and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, each block, part and / or module of some exemplary embodiments can be physically divided into two or more interacting and discrete blocks, parts and / or modules without departing from the scope of the present invention. Furthermore, the blocks, parts and / or modules of some exemplary embodiments may be physically combined into more complex blocks, parts and / or modules without departing from the scope of the inventive concept.

[0069] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0070] Figure 1 is a schematic block diagram of a display device DD according to an embodiment of the present disclosure. Figure 1 , the display device DD may include a display panel DP, panel drivers SDC, EDC and DDC, a power supply unit PWS and a timing controller TC. In an embodiment, the display panel DP may be a light-emitting display panel. The light-emitting display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel or a quantum dot light-emitting display panel. In the following description, the organic light-emitting display panel will be described in detail as a display panel DP. The panel drivers SDC, EDC and DDC may include a scan driver SDC, an emission driver EDC and a data driver DDC.

[0071] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP may include a plurality of pixels electrically connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. Each of "m" and "n" may be an integer greater than 1.

[0072] For example, a pixel PXij ("i" may be an integer greater than 1 and less than or equal to n, and "j" may be an integer greater than 1 and less than or equal to m) positioned to correspond to the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) may be electrically connected to the i-th first scan line (or write scan line) GWLi, the i-th second scan line (or compensation scan line) GCLi, the i-th third scan line (or first initialization scan line) GILi, the i-th fourth scan line (or second initialization scan line) GBLi, the i-th fifth scan line (or reset scan line) GRLi, the j-th data line DLj and the i-th emission line ESLi.

[0073] The pixel PXij may include a plurality of light emitting devices, a plurality of transistors, and a plurality of capacitors. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or reference voltage) VREF, a fourth power supply voltage (or first initialization voltage) VINT1, a fifth power supply voltage (or second initialization voltage) VINT2, and a sixth power supply voltage (or compensation voltage) VCOMP from a power supply unit PWS.

[0074] The first power supply voltage VDD and the second power supply voltage VSS may have voltage values ​​set to allow current to flow through the light emitting device and emit light. As an example, the first power supply voltage VDD may be set to have a voltage level higher than that of the second power supply voltage VSS.

[0075] The third power supply voltage VREF may be a voltage for initializing a gate electrode of a driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement grayscale using a voltage difference between the third power supply voltage VREF and a data signal. To this end, the third power supply voltage VREF may be set to a voltage within a voltage range of the data signal.

[0076] The fourth power supply voltage VINT1 may be used to initialize a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to have a voltage level lower than the voltage level of the third power supply voltage VREF. As an example, the fourth power supply voltage VINT1 may be set to have a voltage level lower than the difference between the voltage level of the third power supply voltage VREF and the voltage level of the threshold voltage of the driving transistor, however, the present disclosure should not be limited thereto or thereby.

[0077] The fifth power supply voltage VINT2 may be used to initialize the cathode of the light emitting device included in the pixel PXij. The fifth power supply voltage VINT2 may be set to have a voltage level lower than the voltage level of the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to have a voltage level similar to or equal to the voltage level of the third power supply voltage VREF, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the fifth power supply voltage VINT2 may be set to have a voltage level similar to or equal to the voltage level of the first power supply voltage VDD.

[0078] The sixth power supply voltage VCOMP may provide current to the driving transistor while the threshold voltage of the driving transistor is compensated.

[0079] Figure 1 A structure in which the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP can all be provided from the power supply unit PWS is shown, however, the present disclosure should not be limited thereto or thereby. As an example, both the first power supply voltage VDD and the second power supply voltage VSS can be provided regardless of the circuit structure of the pixel PXij, however, depending on the circuit structure of the pixel PXij, at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be provided.

[0080] According to the present disclosure, by considering the circuit structure of the pixel PXij, the signal line electrically connected to the pixel PXij may be designed in various ways.

[0081] The scan driver SDC may receive a first control signal SCS from the timing controller TC and may provide a scan signal to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn in response to the first control signal SCS.

[0082] The scan signal may be set to a voltage that allows the transistor to be turned on in response to the scan signal. As an example, the scan signal provided to the P-type transistor may be set to have a logic low level, and the scan signal provided to the N-type transistor may be set to have a logic high level. Hereinafter, the expression "the scan signal is provided" may mean that the scan signal may be provided to the transistor, whereby the transistor may be controlled at a logic level that turns on the transistor.

[0083] For ease of explanation, Figure 1 One scan driver SDC is shown, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the display device DD may include a plurality of scan drivers for providing scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0084] The emission driver EDC may receive the second control signal ECS from the timing controller TC and may provide the emission signal to the emission lines ESL1 to ESLn in response to the second control signal ECS. As an example, the emission signal may be sequentially provided to the emission lines ESL1 to ESLn.

[0085] Each transistor electrically connected to the emission lines ESL1 to ESLn may be an N-type transistor. The emission signal provided to the emission lines ESL1 to ESLn may have a gate-off voltage. The transistor may be turned off when receiving the emission signal, and may be turned on in other cases.

[0086] The second control signal ECS may include an emission start signal and a clock signal, and the emission driver EDC may be implemented by a shift register that sequentially shifts the emission start signal having a pulse shape using the clock signal to sequentially generate and output emission signals having a pulse shape.

[0087] The data driver DDC may receive the third control signal DCS and the image data RGB from the timing controller TC. The data driver DDC may convert the image data RGB in digital form into data signals in analog form. The data driver DDC may provide data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0088] The third control signal DCS may include a data enable signal, a horizontal start signal, and a data clock signal to indicate the output of a valid data signal. As an example, the data driver DDC may include a shift register that shifts the horizontal start signal synchronously with the data clock signal to generate a sampling signal, a latch that latches the image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data RGB (e.g., image data RGB in digital form) into a data signal in analog form, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0089] The power supply unit PWS may provide the first power supply voltage VDD, the second power supply voltage VSS and the third power supply voltage VREF to the display panel DP to drive the pixel PXij. In addition, the power supply unit PWS may provide at least one voltage of the fourth power supply voltage VINT1, the fifth power supply voltage VINT2 and the sixth power supply voltage VCOMP to the display panel DP.

[0090] As an example, the power supply unit PWS can be respectively Figure 2A The first power supply line VDL (reference Figure 2A )、Second power line VSL (reference Figure 2A )、The third power line (or reference voltage line) VRL (reference Figure 2A ), the fourth power line (or the first initialization voltage line) VIL1 (reference Figure 2A ), the fifth power line (or the second initialization voltage line) VIL2 (reference Figure 2A ) and the sixth power line (or compensation voltage line) VCL (reference Figure 2A ) provides a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF, a fourth power supply voltage VINT1, a fifth power supply voltage VINT2 and a sixth power supply voltage VCOMP to the display panel DP.

[0091] The power supply unit PWS may be implemented by a power management integrated circuit, however, the present disclosure should not be limited thereto or thereby.

[0092] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal. The first control signal SCS may be applied to the scan driver SDC, the second control signal ECS may be applied to the emission driver EDC, the third control signal DCS may be applied to the data driver DDC, and the fourth control signal PCS may be applied to the power supply unit PWS. The timing controller TC may rearrange the input image data IRGB to correspond to the arrangement of pixels in the display panel DP, and may generate image data RGB (or frame data).

[0093] The scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and / or the timing controller TC may be formed (e.g., directly formed) in the display panel DP, or may be electrically connected to the display panel DP after being implemented in a separate driver chip. In addition, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and the timing controller TC may be implemented in a single driver chip. As an example, the data driver DDC and the timing controller TC may be provided in a single driver chip.

[0094] Details of the display device DD can be found in Figure 1 However, the display device DD should not be limited to or constrained by this. Depending on the circuit structure of the pixel, the signal line can be added or omitted. In addition, the connection relationship between a pixel and the signal line can be changed. In the case where one of the signal lines can be omitted, the omitted signal line can be replaced by another signal line.

[0095] Figure 2A and Figure 2B is a schematic diagram of an equivalent circuit of pixels PXij and PXij-1 according to an embodiment of the present disclosure. Figure 2A and Figure 2B An equivalent circuit diagram of pixels PXij and PXij-1 that may be electrically connected to an i-th first scan line GWLi and a j-th data line (hereinafter, referred to as a data line) DLj is shown.

[0096] refer to Figure 2A The pixel PXij may include a light emitting device LD and a pixel driver PDC. The light emitting device LD may be electrically connected to the first power line VDL and the pixel driver PDC.

[0097] The pixel driver PDC may be electrically connected to the scan lines GWLi, GCLi, GILi, GBLi, and GRLi, the data lines DLj, the emission lines ESLi, and the power lines VDL, VSL, VIL1, VIL2, VRL, and VCL (hereinafter, some of the power lines VDL, VSL, VIL1, VIL2, VRL, and VCL will be referred to as power lines, and other of the power lines VDL, VSL, VIL1, VIL2, VRL, and VCL will be referred to as voltage lines). The pixel driver PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, a first capacitor C1, and a second capacitor C2. Hereinafter, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 will be described as an N-type transistor, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, some of the first to eighth transistors T1 to T8 may be N-type transistors and other transistors of the first to eighth transistors T1 to T8 may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be a P-type transistor, and the present disclosure should not be particularly limited.

[0098] The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first electrode of the first transistor T1 may be electrically connected to the second node N2, and the second electrode of the first transistor T1 may be electrically connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the light emitting device LD in response to a voltage of the first node N1. The first power supply voltage VDD may be set to a voltage having a voltage level higher than a voltage level of the second power supply voltage VSS.

[0099] In the present disclosure, the expression "a transistor is electrically connected to a signal line or another transistor" may mean that the source electrode, drain electrode or gate electrode of the transistor and the signal line are integrated with each other, or that the source electrode, drain electrode or gate electrode of the transistor is electrically connected to a signal line or another transistor via a connecting electrode.

[0100] The second transistor T2 may include a gate electrode electrically connected to the write scan line GWLi, a first electrode electrically connected to the data line DLj, and a second electrode electrically connected to the first node N1. The second transistor T2 may provide the data signal DATA to the first node N1 in response to a write scan signal GW applied thereto via the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is applied to the write scan line GWLi, and thus, the data line DLj may be electrically connected to the first node N1.

[0101] The third transistor T3 may be electrically connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF via the reference voltage line VRL, and the second electrode of the third transistor T3 may be electrically connected to the first node N1. In an embodiment, the gate electrode of the third transistor T3 may receive the reset scan signal GR via the i-th fifth scan line (hereinafter, referred to as the reset scan line) GRLi. The third transistor T3 may be turned on when the reset scan signal GR is applied to the reset scan line GRLi, and the reference voltage VREF may be provided to the first node N1.

[0102] The fourth transistor T4 may be electrically connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 may be electrically connected to the third node N3, and the second electrode of the fourth transistor T4 may be electrically connected to the first initialization voltage line VIL1 through which the first initialization voltage VINT1 may be provided. The fourth transistor T4 may be referred to as a first initialization transistor. The gate electrode of the fourth transistor T4 may receive the first initialization scan signal GI via the i-th third scan line (hereinafter, referred to as the first initialization scan line) GILi. The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0103] The fifth transistor T5 may be electrically connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP via the compensation voltage line VCL, and the second electrode of the fifth transistor T5 may be electrically connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may receive the compensation scan signal GC via the i-th second scan line (hereinafter, referred to as the compensation scan line) GCLi. The fifth transistor T5 may be turned on and may provide the compensation voltage VCOMP to the second node N2 when the compensation scan signal GC is provided to the compensation scan line GCLi, and therefore, the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0104] The sixth transistor T6 may be electrically connected between the first transistor T1 and the light emitting device LD. In detail, the gate electrode of the sixth transistor T6 may receive the emission signal EM via the i-th emission line (hereinafter, referred to as the emission line) ESLi. The first electrode of the sixth transistor T6 may be electrically connected to the cathode of the light emitting device LD via the fourth node N4, and the second electrode of the sixth transistor T6 may be electrically connected to the first electrode of the first transistor T1 via the second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. The sixth transistor T6 may be turned on when the emission signal EM is provided to the emission line ESLi, and therefore, the light emitting device LD may be electrically connected to the first transistor T1.

[0105] The seventh transistor T7 may be electrically connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 may be electrically connected to the second electrode of the first transistor T1 via the third node N3, and the second electrode of the seventh transistor T7 may receive the second power supply voltage VSS via the second power line VSL. The gate electrode of the seventh transistor T7 may be electrically connected to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. The seventh transistor T7 may be turned on when the emission signal EM is provided to the emission line ESLi, and therefore, the second electrode of the first transistor T1 may be electrically connected to the second power line VSL.

[0106] According to an embodiment, the sixth transistor T6 and the seventh transistor T7 may be electrically connected to the same emission line ESLi and may be turned on in response to the same emission signal EM, however, this may be only an example. According to an embodiment, the sixth transistor T6 and the seventh transistor T7 may be turned on independently in response to different signals distinguished from each other. In addition, according to an embodiment, one of the sixth transistor T6 and the seventh transistor T7 may be omitted from the pixel driver PDC.

[0107] The eighth transistor T8 may be electrically connected between the second initialization voltage line VIL2 and the fourth node N4. For example, the eighth transistor T8 may include a gate electrode electrically connected to the i-th fourth scan line (hereinafter, referred to as the second initialization scan line) GBLi, a first electrode electrically connected to the second initialization voltage line VIL2, and a second electrode electrically connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may provide the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting device LD in response to the second initialization scan signal GB applied thereto via the second initialization scan line GBLi. The cathode of the light emitting device LD may be initialized by the second initialization voltage VINT2.

[0108] According to an embodiment, some of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be substantially turned on at the same time in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 may be substantially turned on at the same time in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 may be operated in response to the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be substantially turned on or off at the same time in response to the same compensation scan signal GC. The compensation scan line GCLi and the second initialization scan line GBLi may be substantially provided as a single scan line. Accordingly, the initialization of the cathode of the light emitting device LD and the compensation of the threshold voltage of the first transistor T1 may be performed at the same timing, however, the present disclosure should not be limited thereto or be limited thereto.

[0109] According to the present disclosure, the initialization of the cathode of the light emitting device LD and the compensation of the threshold voltage of the first transistor T1 can be performed in response to the same power supply voltage. As an example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided substantially as a single power supply line. The initialization operation of the cathode of the light emitting device LD and the compensation operation of the first transistor (or driving transistor) T1 can be performed using one power supply voltage, and therefore, the design of the pixel driver PDC can be simplified. However, this may be only an example, and the present disclosure should not be particularly limited.

[0110] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may be charged with electric charges corresponding to a difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0111] The second capacitor C2 may be provided between the third node N3 and the second power line VSL. For example, one electrode of the second capacitor C2 may be electrically connected to the second power line VSL receiving the second power voltage VSS, and the other electrode of the second capacitor C2 may be electrically connected to the third node N3. The second capacitor C2 may be charged with a charge corresponding to the difference between the second power voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor. Compared to the first capacitor C1, the second capacitor C2 may have a higher storage capacity. Accordingly, the second capacitor C2 may reduce the change in the voltage of the third node N3 according to the change in the voltage of the first node N1.

[0112] In an embodiment, the light emitting device LD may be electrically connected to the pixel driver PDC via a fourth node N4. The light emitting device LD may include an anode electrically connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the light emitting device LD may be electrically connected to the pixel driver PDC via its cathode. For example, according to the pixel PXij, the connection node at which the light emitting device LD may be electrically connected to the pixel driver PDC may be a fourth node N4, and the fourth node N4 may correspond to a connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting device LD. Accordingly, the potential of the fourth node N4 may correspond to the potential of the cathode of the light emitting device LD.

[0113] In detail, the anode of the light emitting device LD may be electrically connected to the first power line VDL, the first power voltage VDD which may be a constant voltage may be applied to the anode of the light emitting device LD, and the cathode of the light emitting device LD may be electrically connected to the first transistor T1 via the sixth transistor T6. For example, in an embodiment where each of the first transistor T1 to the eighth transistor T8 is an N-type transistor, the potential of the third node N3 corresponding to the source electrode of the first transistor T1 which may be a driving transistor may not be affected by (e.g., directly affected by) the characteristics of the light emitting device LD. Accordingly, even if the light emitting device LD may be degraded, the effect of the degradation of the characteristics of the light emitting device LD on the gate-source voltage (Vgs) of the transistor (especially the driving transistor) constituting the pixel driver PDC may be reduced. For example, since the variation range of the amount of the driving current ILD due to the degradation of the light emitting device LD may be reduced, the image residual defect of the display panel according to the increase in the use time may be reduced, and the life of the display panel may be improved.

[0114] like Figure 2B As shown in FIG. 1 , the pixel PXij- 1 may include a pixel driver PDC- 1 including two transistors T1 and T2 and a capacitor C1. The pixel driver PDC- 1 may be electrically connected to the light emitting device LD, the write scan line GWLi, the data line DLj, and the second power line VSL. Figure 2B The pixel driver PDC-1 shown in FIG. 1 may have a Figure 2A The pixel driver PDC shown in FIG. 1 is a circuit configuration obtained by removing the third transistor T3 to the eighth transistor T8 and the second capacitor C2 .

[0115] Each of the first transistor T1 and the second transistor T2 may be an N-type transistor or a P-type transistor. In an embodiment, each of the first transistor T1 and the second transistor T2 will be described as an N-type transistor.

[0116] The first transistor T1 may include a gate electrode electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. The second node N2 may be electrically connected to a first power line VDL via a light emitting device LD, and the third node N3 may be electrically connected to a second power line VSL. The first transistor T1 may be electrically connected to the light emitting device LD via a second node N2, and may be electrically connected to a second power line VSL via a third node N3. The first transistor T1 may be a driving transistor.

[0117] The second transistor T2 may include a gate electrode receiving a write scan signal GW via the write scan line GWLi, a first electrode electrically connected to the data line DLj, and a second electrode electrically connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW applied thereto via the write scan line GWLi.

[0118] The capacitor C1 may include one electrode electrically connected to the first node N1 and another electrode electrically connected to the third node N3. The capacitor C1 may be charged with charges corresponding to a difference between a voltage of the data signal DATA applied to the first node N1 and a voltage of the third node N3.

[0119] The light emitting device LD may include an anode and a cathode. In an embodiment, the anode of the light emitting device LD may be electrically connected to the first power line VDL, and the cathode of the light emitting device LD may be electrically connected to the pixel driver PDC-1 via the second node N2. In an embodiment, the cathode of the light emitting device LD may be electrically connected to the first transistor T1. The light emitting device LD may emit light in response to the amount of the driving current ILD flowing through the first transistor T1 of the pixel driver PDC-1.

[0120] In an embodiment where each of the first transistor T1 and the second transistor T2 is an N-type transistor, the cathode of the light emitting device LD may be electrically connected to the second node N2 of the pixel driver PDC-1 at which the cathode of the light emitting device LD may correspond to the drain electrode of the first transistor T1. For example, the display panel may prevent a change in the gate-source voltage (Vgs) of the first transistor T1 that may be caused by degradation of the characteristics of the light emitting device LD. Accordingly, the range of variation in the amount of the driving current ILD due to degradation of the light emitting device LD may be reduced, the image residual defect of the display panel according to the increase in the use time may be reduced, and the life of the display panel may be improved.

[0121] Figure 2A and Figure 2BThe circuit configuration of the pixel driver PDC and PDC-1 according to the embodiment of the present disclosure is shown. In the display panel according to the embodiment of the present disclosure, the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways and should not be particularly limited as long as the pixel driver PDC or PDC-1 is electrically connected to the cathode of the light emitting device LD.

[0122] Figure 3A and Figure 3B is a plan view of a display panel DP according to an embodiment of the present disclosure. Figure 3A and Figure 3B In the following, reference will be made to Figure 3A and Figure 3B Describe the present disclosure. Figure 3A , the display panel DP may include a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a plurality of light emitting parts EP.

[0123] The light emitting portion EP may be a region where a pixel emits light. In detail, each of the light emitting portions EP may be connected to a light emitting opening OP-PDL (refer to Figure 5 ) corresponding to.

[0124] The peripheral area NDA may be defined as being adjacent to the display area DA. In an embodiment, the peripheral area NDA may have a shape surrounding an edge of the display area DA, however, this may be only an example. According to an embodiment, the peripheral area NDA may be defined as being adjacent to one side of the display area DA or may be omitted, and it should not be particularly limited.

[0125] In an embodiment, a scan driver SDC and a data driver DDC may be installed in the display panel DP. The scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the light emitting portions EP disposed in the display area DA in a plan view. Since the scan driver SDC may be disposed in the display area DA, the size of the peripheral area NDA may be reduced compared to the size of the peripheral area of ​​a conventional display panel in which the scan driver is disposed in the peripheral area, and thus, the display device DD may be easily implemented (refer to FIG. 1 ). Figure 1 ) with a narrow border.

[0126] and Figure 3AUnlike the scan driver SDC shown in the figure, the scan driver SDC may be provided as two scan drivers SDC distinguished from each other. The two scan drivers SDC may be respectively disposed on the left and right sides of the display area DA and may be spaced apart from each other, wherein the center of the display area DA is disposed between the two scan drivers SDC. According to an embodiment, three or more scan drivers SDC may be adopted, and the number of the scan drivers SDC should not be particularly limited.

[0127] Figure 3A A representative example of the display panel DP is shown, however, according to an example, the data driver DDC may be disposed in the display area DA. In the case where the data driver DDC may be disposed in the display area DA, some of the light emitting parts EP arranged in the display area DA may overlap with the data driver DDC in a plan view.

[0128] The data driver DDC may be provided in a separate driving chip formed independently of the display panel DP and may be electrically connected to the display panel DP, however, this may be only an example. According to an embodiment, the data driver DDC may be formed by the same process as the scan driver SDC in the case where the display panel DP may be manufactured, and it should not be limited thereto or thereby.

[0129] refer to Figure 3B , the display panel DP may have a shape in which the length in the first direction DR1 may be longer than the length in the second direction DR2. The pixels PX11 to PXnm may be arranged in n rows by m columns in the display area DA. In an embodiment, the display panel DP may include a plurality of scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 may include a first scan driver SDC1 and a second scan driver SDC2 that may be spaced apart from each other in the first direction DR1.

[0130] exist Figure 3B , the first scan driver SDC1 may be electrically connected to the scan lines GL1 to GLn, and the second scan driver SDC2 may be electrically connected to the scan lines GL1 to GLn. Alternatively, the first scan driver SDC1 may be electrically connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be electrically connected to the other scan lines GL1 to GLn. As an example, the first scan driver SDC1 may be electrically connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be electrically connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0131] For ease of explanation, Figure 3BThe pads PD of the data lines DL1 to DLm are shown. The pads PD may be located at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be electrically connected to the data driver DDC (reference Figure 3A ).

[0132] According to the present disclosure, the pads PD may be arranged in areas of the peripheral area NDA that may be spaced apart from each other (where the display area DA is disposed between these areas). As an example, some of the pads PD may be arranged in an upper portion of the display panel DP that may be adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other pads of the pads PD may be arranged in a lower portion of the display panel DP that may be adjacent to the last scan line GLn among the scan lines GL1 to GLn. In an embodiment, pads electrically connected to odd-numbered data lines may be arranged in the above-mentioned upper portion, and pads electrically connected to even-numbered data lines may be arranged in the above-mentioned lower portion.

[0133] Although not shown in the figure, the display panel DP may include an upper data driver electrically connected to the pad PD arranged in the above-mentioned upper portion and a lower data driver electrically connected to the pad PD arranged in the above-mentioned lower portion, however, these may be only examples. According to an embodiment, the display panel DP may include an upper data driver electrically connected to the pad PD arranged in the above-mentioned upper portion and / or a lower data driver electrically connected to the pad PD arranged in the above-mentioned lower portion. According to an embodiment, the pad PD may be arranged in one side portion of the display panel DP and may be electrically connected to a single data driver, however, the present disclosure should not be particularly limited.

[0134] As reference Figure 3A As described, Figure 3B The display panel DP shown in FIG. 5 may include a scan driver and / or a data driver arranged in the display area DA, and thus, some of the light emitting parts arranged in the display area DA may overlap with the scan driver and / or the data driver in a plan view.

[0135] FIG. 4A to FIG. 4C is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) are enlarged plan views of some areas. Figure 4A shows a region in which four light emitting units may be arranged in two rows by two columns, and Figure 4B Can be Figure 4A An enlarged view of the portion of the area shown in . Figure 4C Shows Figure 4A However, for convenience of explanation, some components may be emphasized or may not be shown. FIG. 4A to FIG. 4C The present disclosure is described.

[0136] Figure 4A The light emitting units UT11, UT12, UT21, and UT22 arranged in two rows by two columns are shown. The light emitting portion arranged in the first row Rk may include the light emitting portion constituting the light emitting unit UT11 arranged in the first row and the first column and the light emitting unit UT12 arranged in the first row and the second column, and the light emitting portion arranged in the second row Rk+1 may include the light emitting portion constituting the light emitting unit UT21 arranged in the second row and the first column and the light emitting unit UT22 arranged in the second row and the second column. Figure 4B The light emitting parts arranged in the first row Rk are shown. FIG. 4A to FIG. 4C A spacer SPR, a plurality of light emitting parts EP1, EP2, and EP3 disposed in regions divided by the spacer SPR, connection wirings CN1, CN2, and CN3, a first electrode EL1, second electrodes EL2_1, EL2_2, and EL2_3, and a spacer SPC are illustrated.

[0137] As described above, each of the light emitting parts EP1, EP2, and EP3 may be aligned with the light emitting opening OP-PDL (refer to Figure 5 ) corresponds to. For example, each of the light emitting parts EP1, EP2 and EP3 can be a light emitting device LD (refer to Figure 2A and Figure 2B ) from which light is emitted, and can be connected to the display panel DP (reference Figure 1 ) corresponds to a portion of an image displayed. In more detail, each of the light emitting portions EP1, EP2, and EP3 may correspond to a portion of an image displayed by a light emitting opening OP-PDL (reference Figure 5 ) corresponds to the area defined by the .

[0138] The light emitting parts EP1, EP2 and EP3 may include a first light emitting part EP1, a second light emitting part EP2 and a third light emitting part EP3. The first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may emit light having different colors from each other. As an example, the first light emitting part EP1 may emit red light, the second light emitting part EP2 may emit green light and the third light emitting part EP3 may emit blue light, however, the color of the light emitted by the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 should not be limited thereto or limited thereto. In addition, at least two of the light emitting parts EP1, EP2 and EP3 may emit light having the same color. For example, all of the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may emit blue light or white light.

[0139] Among the light emitting parts EP1, EP2, and EP3, the third light emitting part EP3 emitting light emitted by the third light emitting device may include two sub-light emitting parts EP31 and EP32 spaced apart from each other in the second direction DR2, however, this may be only an example. According to an embodiment, like the other light emitting parts EP1 and EP2, the third light emitting part EP3 may be provided in a single pattern having an integral shape, or at least one of the other light emitting parts EP1 and EP2 may include sub-light emitting parts spaced apart from each other, and the present disclosure should not be particularly limited.

[0140] The light emitting parts arranged in the first row Rk may include the light emitting parts EP1, EP2 and EP3 constituting the light emitting cells UT11 arranged in the first row and the first column and the light emitting cells UT12 arranged in the first row and the second column, and the light emitting parts arranged in the second row Rk+1 may include the light emitting parts EP1, EP2 and EP3 constituting the light emitting cells UT21 arranged in the second row and the first column and the light emitting cells UT22 arranged in the second row and the second column. A part of the light emitting parts arranged in the first row Rk and a part of the light emitting parts arranged in the second row Rk+1 may be symmetrical to each other. As an example, the first light emitting part EP1 and the second light emitting part EP2 of the light emitting cell UT12 arranged in the first row and the second column and the first light emitting part EP1 and the second light emitting part EP2 of the light emitting cell UT11 arranged in the first row and the first column may have a shape and arrangement that may be line-symmetrical about an axis parallel to the second direction DR2. The third light emitting part EP3 of the light emitting cell UT21 arranged in the second row and the first column and the third light emitting part EP3 of the light emitting cell UT11 arranged in the first row and the first column may have a shape and arrangement that may be line-symmetrical about an axis parallel to the first direction DR1.

[0141] Hereinafter, the light emitting unit UT11 arranged in the first row and the first column will be described in detail. For convenience of explanation, Figure 4B The second electrodes EL2_1, EL2_2, and EL2_3, the pixel drivers PDC1, PDC2, and PDC3, and the connection wirings CN1a, CN1b, CN2a, CN2b, CN3a, and CN3b are shown. The second electrodes EL2_1, EL2_2, and EL2_3 may be separated from each other by a separator SPR and electrically disconnected from each other.

[0142] The separator SPR may be provided with a plurality of separation openings OP-S defined therethrough. The second electrodes EL2_1, EL2_2, and EL2_3 may be respectively disposed in the separation openings OP-S to be separated from each other. Accordingly, the arrangement and shape of the second electrodes EL2_1, EL2_2, and EL2_3 may correspond to the arrangement and shape of the separation openings OP-S of the separator SPR.

[0143] In an embodiment, the spacer SPR may include separation grid lines MSL, and the separation grid lines MSL may include first lines L1-S extending in the first direction DR1 and second lines L2-S extending in the second direction DR2. The separation openings OP-S of the spacer SPR may be defined by the separation grid lines MSL.

[0144] In an embodiment, one light emitting unit may include three light emitting parts EP1, EP2 and EP3. Accordingly, one light emitting unit may include three second electrodes EL2_1, EL2_2 and EL2_3 (hereinafter, referred to as first cathode, second cathode and third cathode), three pixel drivers PDC1, PDC2 and PDC3 and three connection wirings CN1a, CN2a and CN3a or CN1b, CN2b and CN3b, however, this may be only an example. According to an embodiment, the number and arrangement of the light emitting units may be designed in various ways and should not be particularly limited.

[0145] The first partition opening OP1-S, the second partition opening OP2-S and the third partition opening OP3-S may be defined by a partition member SPR. The first partition opening OP1-S, the second partition opening OP2-S and the third partition opening OP3-S may overlap with the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3, respectively. In a plan view (or when viewed from the top side of the display device), the first partition opening OP1-S, the second partition opening OP2-S and the third partition opening OP3-S may surround the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3, respectively. In a plan view, the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may be respectively disposed in the first partition opening OP1-S, the second partition opening OP2-S and the third partition opening OP3-S. The first cathode EL2_1, the second cathode EL2_2 and the third cathode EL2_3 may be separated from each other by a partition member SPR and may be respectively disposed in the first partition opening OP1-S, the second partition opening OP2-S and the third partition opening OP3-S.

[0146] The first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be electrically connected to the light emitting devices forming the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3, respectively. In the present disclosure, the expression that component A may be electrically connected to component B may mean not only a case where component A may be connected (e.g., directly and physically connected) to component B, but also a case where component A may be electrically connected to component B.

[0147] like Figure 4BAs shown in FIG. 1 , each region where pixel drivers PDC1, PDC2, and PDC3 can be defined on a plane can be repeatedly arranged with light emitting devices LD constituting driving pixels (refer to FIG. 1 ). Figure 2A ) of the pixel driver PDC (reference Figure 2A ) (or circuit) corresponds to the transistor and capacitor parts.

[0148] The first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 may be sequentially arranged in the first direction DR1. The arrangement positions of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 may be independently designed regardless of the positions or shapes of the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3.

[0149] As an example, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be positioned at a position different from the area divided by the partition SPR (i.e., the position at which the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be positioned), or may be designed to have a shape and size different from the shape and size of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. According to an embodiment, the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be positioned to overlap with the positions at which the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may be positioned, respectively, and may be designed to have a shape and size similar to the shape and size of the area divided by the partition SPR (i.e., the shape and size of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3).

[0150] In an embodiment, each of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 may have a rectangular shape, each of the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 may have a size smaller than that of a corresponding one of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3 and a shape different from the shape of a corresponding one of the first pixel driver PDC1, the second pixel driver PDC2 and the third pixel driver PDC3, and the first cathode EL2_1, the second cathode EL2_2 and the third cathode EL2_3 may be positioned at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 and may have an irregular shape.

[0151] Accordingly, if Figure 4BAs shown in , the first pixel driver PDC1 may be positioned at a position overlapping the first light emitting portion EP1, the second light emitting portion EP2, and a portion of another light emitting portion adjacent to them. The second pixel driver PDC2 may be positioned at a position overlapping the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. The third pixel driver PDC3 may be positioned at a position overlapping the third light emitting portion EP3, however, these may be merely examples. According to an embodiment, the positions of the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3 may be designed to have various shapes and arrangements independently of the light emitting portions EP1, EP2, and EP3, and should not be particularly limited.

[0152] The connection wiring CN may be provided in plurality, and the plurality of connection wirings CN may be arranged spaced apart from each other. One connection wiring CN may electrically connect one pixel driver among the pixel drivers PDC1, PDC2, and PDC3 and the light emitting device corresponding thereto. In detail, the connection wiring CN may be connected to the light emitting device LD (refer to Figure 2A and Figure 2B ) can be electrically connected thereto Figure 2A The pixel driver PDC or Figure 2B The pixel driver PDC-1 node (reference Figure 2A The fourth node N4 or Figure 2B Corresponding to the second node N2).

[0153] The connection wiring CN may include a first connection portion (or light emitting connection portion) CE and a second connection portion (or driver connection portion) CD. The light emitting connection portion CE may be provided at one end of the connection wiring CN, and the driver connection portion CD may be provided at the other end of the connection wiring CN.

[0154] The driver connection portion CD may be a portion of the connection wiring CN that may be electrically connected to the pixel driver PDC or PDC-1. In an embodiment, the driver connection portion CD may be electrically connected to one electrode of a transistor forming the pixel driver PDC or PDC-1. In detail, the driver connection portion CD may be electrically connected to Figure 2A The drain electrode of the sixth transistor T6 shown in FIG. Figure 2B . Accordingly, the position of the driver connection portion CD can be aligned with the transistor of the pixel driver PDC or PDC-1 that can be physically connected to the connection wiring CN (refer to Figure 5The light emitting connection portion CE may be a portion of the connection wiring CN that may be electrically connected to the light emitting device LD. In an embodiment, the light emitting connection portion CE may be electrically connected to the second electrode EL2 (hereinafter, referred to as the cathode, refer to Figure 5 ).

[0155] The light emitting unit may include a first connection wiring CN1, a second connection wiring CN2, and a third connection wiring CN3. The first connection wiring CN1 may connect the light emitting device LD forming the first light emitting portion EP1 to the first pixel driver PDC1, the second connection wiring CN2 may connect the light emitting device LD forming the second light emitting portion EP2 to the second pixel driver PDC2, and the third connection wiring CN3 may connect the light emitting device LD forming the third light emitting portion EP3 to the third pixel driver PDC3.

[0156] In detail, the first connection wiring CN1, the second connection wiring CN2, and the third connection wiring CN3 may connect the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 to the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3, respectively. The first connection wiring CN1 may include a first driver connection portion CD1 electrically connected to the first pixel driver PDC1 and a first light emitting connection portion CE1 electrically connected to the first cathode EL2_1. The second connection wiring CN2 may include a second driver connection portion CD2 electrically connected to the second pixel driver PDC2 and a second light emitting connection portion CE2 electrically connected to the second cathode EL2_2. The third connection wiring CN3 may include a third driver connection portion CD3 electrically connected to the third pixel driver PDC3 and a third light emitting connection portion CE3 electrically connected to the third cathode EL2_3.

[0157] The first driver connection part CD1, the second driver connection part CD2, and the third driver connection part CD3 may be arranged in the first direction DR1. As described above, the positions of the first driver connection part CD1, the second driver connection part CD2, and the third driver connection part CD3 may correspond to the positions of the connection transistors forming the first pixel driver PDC1, the second pixel driver PDC2, and the third pixel driver PDC3, respectively. In one pixel, the connection transistor may include a connection node at which the pixel driver PDC or PDC-1 may be electrically connected to the light emitting device LD as its electrode. As an example, the connection transistor may be connected to Figure 2A The sixth transistor T6 or Figure 2BThe connection transistor may be provided in each pixel, and each of the connection transistors may be electrically connected to a corresponding second electrode among the second electrodes EL2_1, EL2_2, and EL2_3 of the light emitting device LD via a corresponding driver connection portion among the driver connection portions CD1, CD2, and CD3. According to the present disclosure, the shape, position, and arrangement of the pixel driver PDC or PDC-1 of all pixels may be simplified regardless of the shape, size, or emission color of the light emitting portions EP1, EP2, and EP3.

[0158] In the embodiment, the first light emitting connection portion CE1, the second light emitting connection portion CE2, and the third light emitting connection portion CE3 may be defined at positions that do not overlap with the light emitting portions EP1, EP2, and EP3 in a plan view. Since each of the light emitting connection portions CE1, CE2, and CE3 of the connection wiring CN may be electrically connected to the light emitting device LD (refer to Figure 5 ) and can define the tip portion TP (reference Figure 5 ) part, so each of the light emitting connection parts CE1, CE2 and CE3 can be provided without contacting the light emitting opening OP-PDL (reference Figure 5 ) at a position where the light emitting connection parts CE1, CE2 and CE3 overlap. For example, the light emitting connection parts CE1, CE2 and CE3 may be positioned at positions in the cathodes EL2_1, EL2_2 and EL2_3 that are spaced apart from the light emitting parts EP1, EP2 and EP3, and the cathodes EL2_1, EL2_2 and EL2_3 may include some areas protruding from the light emitting parts EP1, EP2 and EP3 in a plan view to be electrically connected to the connection wirings CN1, CN2 and CN3 at positions where the light emitting connection parts CE1, CE2 and CE3 may be positioned.

[0159] As an example, the first cathode EL2_1 may include a protruding portion protruding from the first light emitting portion EP1 at a position not overlapping the first light emitting portion EP1 to be electrically connected to the first connection wiring CN1 at a position where the first light emitting connection portion CE1 can be located, and the first light emitting connection portion CE1 may be provided in the protruding portion.

[0160] In the first pixel driver PDC1, the first connection wiring CN1 may be electrically connected thereto to the transistor TR (refer to Figure 5 ) may be defined at a position not overlapping the first light emitting portion EP1 in a plan view. According to an embodiment, since the first connection wiring CN1 may be provided in the first light emitting portion EP1, the first cathode EL2_1 may be easily electrically connected to the first pixel driver PDC1.

[0161] In the third pixel driver PDC3, the third driver connection portion CD3, which may be a position at which the third connection wiring CN3 may be electrically connected to the transistor TR, may be limited to a position that does not overlap with the third light emitting connection portion CE3 in a plan view, and may be positioned at a position that overlaps with the third light emitting portion EP3. According to an embodiment, since the third cathode EL2_3 may be electrically connected to the third pixel driver PDC3 via the third connection wiring CN3, restrictions on the design of the third pixel driver PDC3 due to the position or shape of the third light emitting portion EP3 may be reduced, and the degree of freedom of circuit design may be improved.

[0162] In an embodiment, the first light emitting connection portion CE1, the second light emitting connection portion CE2, and the third light emitting connection portion CE3 may overlap with the first partition opening OP1-S, the second partition opening OP2-S, and the third partition opening OP3-S of the partition member SPR, respectively. Accordingly, in one light emitting unit, the first partition opening OP1-S may surround the first light emitting portion EP1 and the first light emitting connection portion CE1 in a plan view, the second partition opening OP2-S may surround the second light emitting portion EP2 and the second light emitting connection portion CE2 in a plan view, and the third partition opening OP3-S may surround the third light emitting portion EP3 and the third light emitting connection portion CE3 in a plan view.

[0163] Reference again Figure 4A , the shape and arrangement of the light emitting parts of the light emitting units UT21 and UT22 arranged in the second row Rk+1 may be line-symmetrical with the shape and arrangement of the light emitting parts of the light emitting units UT11 and UT12 arranged in the first row Rk about an axis parallel to the first direction DR1 or the second direction DR2. Due to the shape and arrangement of the light emitting parts UT11 and UT12 arranged in the first row Rk, the light emitting units UT21 and UT22 arranged in the second row Rk+1 may include light emitting parts obtained by shifting the light emitting units UT11 and UT12 arranged in the first row Rk in the first direction DR1 and the second direction DR2. For example, the light emitting unit UT21 arranged in the second row and the first column may include a light emitting part having the same shape as that of the light emitting part included in the light emitting unit UT12 arranged in the first row and the second column, and the light emitting unit UT22 arranged in the second row and the second column may include a light emitting part having the same shape as that of the light emitting part included in the light emitting unit UT11 arranged in the first row and the first column.

[0164] Accordingly, the connection wiring CN-c provided in the light emitting unit UT21 arranged in the second row and the first column may have the same shape and arrangement as the shape and arrangement of the connection wiring CN1b, CN2b, and CN3b provided in the light emitting unit UT12 arranged in the first row and the second column. Similarly, the connection wiring CN-d provided in the light emitting unit UT22 arranged in the second row and the second column may have the same shape and arrangement as the shape and arrangement of the connection wiring CN1a, CN2a, and CN3a provided in the light emitting unit UT11 arranged in the first row and the first column.

[0165] refer to Figure 4C , the first electrode EL1 (hereinafter, referred to as an anode) of the light emitting device LD may be commonly provided in the light emitting parts EP1, EP2, and EP3. For example, the anode EL1 may be formed as a single layer formed integrally, and thus, the anode EL1 formed as a single layer may be provided to overlap with the partition SPR. According to an embodiment, each anode EL1 may be respectively formed as an independent conductive pattern spaced apart from each other in each light emitting device LD, each anode EL1 may be electrically connected to each other through a conductive layer, and thus, the anode EL1 formed as a pattern may be positioned at a position not overlapping with the partition SPR.

[0166] As described above, the first power supply voltage VDD (reference Figure 2A ) may be applied to the anode EL1, and a common voltage may be applied to all the light emitting parts EP1, EP2, and EP3. The anode EL1 may be electrically connected to the peripheral area NDA (reference Figure 3A ) in which a first power supply line VDL (reference Figure 2A ) or may be electrically connected to the first power line VDL in the display area DA, and it should not be limited thereto or thereby.

[0167] The opening OP-EL1 may be defined by the anode EL1, and the opening OP-EL1 may pass through the anode EL1 formed as a layer. The opening OP-EL1 formed through the anode EL1 as a layer may be positioned not to overlap with the light emitting portion EP, and may be defined at a position overlapping with the partition SPR. The opening OP-EL1 may facilitate the light emission from an organic layer (e.g., the sixth insulating layer 60 (refer to FIG. 1 ) disposed under the anode EL1. Figure 5 Accordingly, the gas from the organic layer provided under the light emitting device LD can be sufficiently discharged in the manufacturing process of the display panel DP, and thus, the degradation of the light emitting device LD which may be caused by the gas generated from the organic layer after the display panel DP is completed can be prevented.

[0168] According to the present disclosure, since the connection wiring can be provided between the light emitting part and the pixel driver, the light emitting device can be stably electrically connected to the pixel driver by only changing the shape of the cathode without changing the arrangement and shape of the light emitting part. Accordingly, the degree of freedom in designing the arrangement of the pixel driver can be improved, and the size of the light emitting part or the resolution of the display panel can be easily increased.

[0169] According to an embodiment, the spacer SPC may be disposed to overlap with the separator SPR. The spacer SPC may be provided in plurality, and at least a portion of each of the spacers SPC may overlap with the separator SPR. The spacer SPC will be described in detail later.

[0170] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Fig. 6A According to the embodiment of the present disclosure Figure 5 Schematic enlarged cross-sectional view of a portion of the display panel DP. Figure 6B According to the embodiment of the present disclosure Figure 5 Schematic enlarged cross-sectional view of a portion of the display panel DP. Figure 5 It is along Figure 4B Schematic cross-sectional view taken along line II'. Fig. 6A yes Figure 5 A schematic enlarged cross-sectional view of region AA, and Figure 6B yes Figure 5 Schematic enlarged cross-sectional view of area BB. Figures 5 to 6B The present disclosure is described.

[0171] refer to Figure 5 , the display panel DP may include a base layer BS, a driving device layer DDL, a light emitting device layer LDL, an encapsulation layer ECL, and a sensing layer ISL. The driving device layer DDL may include a plurality of insulating layers 10, 20, 30, 40, and 50 disposed on the base layer BS and a plurality of conductive patterns and a plurality of semiconductor patterns that may be disposed between the insulating layers 10, 20, 30, 40, and 50. The conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, and 50 may form a pixel driver PDC. For ease of explanation, Figure 5 A schematic cross-sectional view shows a portion of a region in which one light emitting portion may be provided.

[0172] The base layer BS may provide a base surface on which the pixel driver PDC may be disposed. The base layer BS may be a rigid substrate or may be a flexible substrate that is bendable, foldable or rollable. The base layer BS may be a glass substrate, a metal substrate or a polymer substrate, however, it should not be limited thereto or thereby. According to an embodiment, the base layer BS may be an inorganic layer, an organic layer or a composite material layer.

[0173] The base layer BS may have a multi-layer structure. For example, the base layer BS may include a first polymer resin layer, a silicon oxide (SiO x ) layer, set on silicon oxide (SiO x ) layer and a second polymer resin layer disposed on the amorphous silicon (a-Si) layer. Silicon oxide (SiO x ) layer and the amorphous silicon (a-Si) layer may be referred to as a base barrier layer.

[0174] Each of the first polymer resin layer and the second polymer resin layer may include a polyimide resin. In addition, each of the first polymer resin layer and the second polymer resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the present disclosure, as used herein, the term "X-type resin" refers to a resin including a functional group of X.

[0175] The insulating layer, the conductive layer and the semiconductor layer may be formed on the base layer BS by a coating process and a deposition process. The insulating layer, the conductive layer and the semiconductor layer may be selectively patterned by multiple photolithography processes, and thus, a hole may be defined by the insulating layer, or a semiconductor pattern, a conductive pattern and a signal line may be formed.

[0176] The driving device layer DDL may include first, second, third, fourth, and fifth insulating layers 10 , 20 , 30 , 40 , and 50 , which may be sequentially stacked on one another on the base layer BS, and a pixel driver PDC. Figure 5 One transistor TR of the pixel driver PDC and two capacitors C1 and C2 are shown. The transistor TR may be electrically connected to the light emitting device LD via the connection wiring CN (ie, electrically connected to a node ( Figure 2A The fourth node N4 or Figure 2B The transistor TR may be connected to the second node N2 of the transistor. Figure 2A The sixth transistor T6 or Figure 2BAlthough not shown in the drawings, other transistors forming the pixel driver PDC may have the same Figure 5 The structure of the transistor TR (hereinafter, referred to as the connecting transistor) shown in FIG. 1 is substantially the same as that of the transistor TR shown in FIG. 2 , however, this may be only an example. According to an embodiment, other transistors forming the pixel driver PDC may have a structure different from that of the connecting transistor TR and should not be particularly limited.

[0177] The first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may have a single-layer structure of a silicon oxide layer. Other insulating layers described later may be inorganic layers and / or organic layers, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, however, it should not be limited thereto or thereby.

[0178] The first insulating layer 10 may cover the bottom conductive layer BCL. For example, the display panel DP may further include a bottom conductive layer BCL disposed under the connection transistor TR and overlapping the connection transistor TR. The bottom conductive layer BCL may prevent the potential caused by the polarization phenomenon of the base layer BS from affecting the connection transistor TR. In addition, the bottom conductive layer BCL may block light from being incident from the lower side of the bottom conductive layer BCL into the connection transistor TR. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the bottom conductive layer BCL and the base layer BS.

[0179] The bottom conductive layer BCL may include a reflective metal material. As an example, the bottom conductive layer BCL may include titanium (Ti), molybdenum (Mo), an alloy including molybdenum (Mo), aluminum (Al), an alloy including aluminum (Al), aluminum nitride (AlN), or a plurality of other materials. x N y ), tungsten (W), tungsten nitride (W x N y ) and / or copper (Cu).

[0180] In an embodiment, the bottom conductive layer BCL may be electrically connected to the source electrode of the connection transistor TR (or transistor) via the source electrode pattern W1. The bottom conductive layer BCL may be synchronized with the source electrode of the connection transistor TR, however, this may be only an example. According to an embodiment, the bottom conductive layer BCL may be electrically connected to and synchronized with the gate electrode of the connection transistor TR. According to an embodiment, the bottom conductive layer BCL may be electrically connected to another electrode to independently receive a constant voltage or a pulse signal. According to an embodiment, the bottom conductive layer BCL may be provided in an isolated form isolated from other conductive patterns. The bottom conductive layer BCL may be provided in various shapes and should not be particularly limited.

[0181] The connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. As an example, the oxide semiconductor may include an indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) or the like, however, the material used for the semiconductor pattern SP should not be limited thereto or thereby. As an example, the semiconductor pattern SP may include amorphous silicon, low temperature polysilicon, or polycrystalline silicon.

[0182] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR that are distinguished from each other depending on the degree of conductivity. In a plan view, the channel region CR may overlap the gate electrode GE. The source region SR and the drain region DR may be spaced apart from each other, wherein the channel region CR is disposed between the source region SR and the drain region DR. In the case where the semiconductor pattern SP may be an oxide semiconductor, each of the source region SR and the drain region DR may be a reduction region. Accordingly, the source region SR and the drain region DR may have a relatively high content of reduction metal compared to the channel region CR. According to an embodiment, in the case where the semiconductor pattern SP may be polycrystalline silicon, each of the source region SR and the drain region DR may be a highly doped region.

[0183] The source region SR and the drain region DR may have relatively high conductivity compared to the channel region CR. The source region SR may correspond to a source electrode connected to the transistor TR, and the drain region DR may correspond to a drain electrode connected to the transistor TR. Figure 5 As shown in FIG, the connection transistor TR may further include a source electrode pattern W1 and a drain electrode pattern W2 separated from each other and electrically connected to the source region SR and the drain region DR, respectively. In detail, each of the source electrode pattern W1 and the drain electrode pattern W2 is connected to the source region SR and the drain region DR. Figure 2A The pixel driver PDC or Figure 2BOne of the lines of the pixel driver PDC-1 may be integral with each other, however, it should not be limited thereto or thereby.

[0184] The second insulating layer 20 may overlap with a plurality of pixels in common and may cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may have a single-layer structure of a silicon oxide layer.

[0185] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate electrode of the connection transistor TR. The gate electrode GE may be disposed above the semiconductor pattern SP, however, this may be only an example. According to an embodiment, the gate electrode GE may be disposed under the semiconductor pattern SP, and it should not be particularly limited.

[0186] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (Al x N y ), tungsten (W), tungsten nitride (W x N y ), copper (Cu), or an alloy thereof, however, it should not be particularly limited.

[0187] The third insulating layer 30 may be disposed on the second insulating layer 20 and the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0188] Among the conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may form a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart from each other with the first insulating layer 10 and the second insulating layer 20 disposed therebetween.

[0189] According to an embodiment, the first capacitor electrode CPE1 and the bottom conductive layer BCL may be provided integrally with each other. In addition, the second capacitor electrode CPE2 and the gate electrode GE may be integral with each other.

[0190] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2, wherein the third insulating layer 30 is disposed between the second capacitor electrode CPE2 and the third capacitor electrode CPE3, and the third capacitor electrode CPE3 may overlap with the second capacitor electrode CPE2. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may form a second capacitor C2.

[0191] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0192] The source electrode pattern W1 and the drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be electrically connected to the source region SR of the connection transistor TR via the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may serve as the source electrode of the connection transistor TR. The drain electrode pattern W2 may be electrically connected to the drain region DR of the connection transistor TR via the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may serve as the drain electrode of the connection transistor TR. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, the source electrode pattern W1, and the drain electrode pattern W2.

[0193] The connection wiring CN may be disposed on the fifth insulating layer 50. The connection wiring CN may electrically connect the pixel driver PDC to the light emitting device LD. For example, the connection wiring CN may electrically connect the connection transistor TR to the light emitting device LD. The connection wiring CN may be a connection node connecting the pixel driver PDC to the light emitting device LD. For example, the connection wiring CN may be connected to the Figure 2A The fourth node N4 shown in FIG. 1 corresponds to or may be Figure 2B , however, this may be only an example. According to an embodiment, according to the design of the pixel driver PDC, the connection wiring CN may be defined as a connection node electrically connected to various components of the pixel driver PDC, and the connection wiring CN should not be particularly limited as long as the connection wiring CN can be electrically connected to the light emitting device LD.

[0194] The sixth insulating layer 60 may be disposed on the connection wiring CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the connection wiring CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. As an example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0195] The sixth insulating layer 60 may be provided with an opening defined therethrough to expose at least a portion of the connection wiring CN. The connection wiring CN may be electrically connected to the light emitting device LD via the portion exposed and not covered by the sixth insulating layer 60. For example, the connection wiring CN may electrically connect the connection transistor TR to the light emitting device LD. This will be described in detail later. The sixth insulating layer 60 may be omitted from the display panel DP or may be provided in plurality in the display panel DP, and the present disclosure should not be limited thereto or thereby.

[0196] The light emitting device layer LDL may be disposed on the sixth insulating layer 60. The light emitting device layer LDL may include a pixel defining layer PDL, a light emitting device LD, and a spacer SPR. The pixel defining layer PDL may be an organic layer. As an example, the pixel defining layer PDL may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a mixture thereof.

[0197] The pixel defining layer PDL may have light absorbing properties. For example, the pixel defining layer PDL may have a black color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, or a metal material such as chromium or an oxide thereof. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking property.

[0198] The pixel defining layer PDL may be provided with an opening (hereinafter, referred to as a light emitting opening) OP-PDL defined therethrough. The light emitting opening OP-PDL may be provided in plural, and the plural light emitting openings OP-PDL may correspond to the plural light emitting devices LD, respectively. All components of the light emitting device LD may be arranged in the light emitting opening OP-PDL while overlapping each other, and the light emitting opening OP-PDL may correspond to a region in which light emitted from the light emitting device LD may be substantially emitted. Accordingly, in a plan view, the light emitting portion EP (refer to Figure 3A ) may basically correspond to the shape of the light emitting opening OP-PDL.

[0199] The light emitting device LD may include a first electrode EL1, an intermediate layer IML including a light emitting layer EML, and a second electrode EL2. Figure 5 One light emitting device LD is shown, however, the light emitting device LD may be provided in plurality, and each of the plurality of light emitting devices LD may include a first electrode EL1, an intermediate layer IML including a light emitting layer EML, and a second electrode EL2. According to an embodiment, the first electrodes EL1 of the light emitting device LD may be provided integrally with each other. The intermediate layers IML of the light emitting device LD may be separated from each other by a partition SPR, and the second electrodes EL2 of the light emitting device LD may be separated from each other by a partition SPR.

[0200] The first electrode EL1 may be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may have a stack structure of ITO / Ag / ITO.

[0201] In an embodiment, the first electrode EL1 may be an anode of the light emitting device LD. For example, the first electrode EL1 may be electrically connected to a first power line VDL (reference Figure 2A or Figure 2B ), and can receive a first power supply voltage VDD (reference Figure 2A or Figure 2B The first electrode EL1 may be formed in the display area DA (refer to Figure 3A or Figure 3B) is electrically connected to the first power line VDL, or may be in the peripheral area NDA (reference Figure 3A or Figure 3B ) is electrically connected to the first power line VDL. In the case where the first electrode EL1 may be electrically connected to the first power line VDL in the peripheral area NDA, the first power line VDL may be disposed in the peripheral area NDA, and the first electrode EL1 may extend to the peripheral area NDA.

[0202] Figure 5 1 and 2 show a structure in which the first electrode EL1 overlaps with the light emitting opening OP-PDL but does not overlap with the partition SPR, however, it should not be limited thereto or thereby. As described above, the first electrode EL1 of the light emitting device LD may have an integral shape and may have a shape such as Figure 4C For example, the first electrode EL1 may have various shapes as long as the light emitting devices LD receive the same first power supply voltage VDD through their first electrodes EL1, however, it should not be limited thereto or thereby.

[0203] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light emitting layer EML and a functional layer FNL, however, this may be only an example. According to the embodiment, the light emitting device LD may include an intermediate layer IML having various structures, and should not be particularly limited. As an example, the functional layer FNL may include a plurality of layers, or may include two or more layers spaced apart from each other, wherein the light emitting layer EML is disposed between the layers. According to the embodiment, the functional layer FNL may be omitted.

[0204] The light-emitting layer EML may include an organic light-emitting material. In addition, the light-emitting layer EML may include an inorganic light-emitting material, or may include a layer obtained by mixing an organic light-emitting material with an inorganic light-emitting material. In an embodiment, the light-emitting layers EML respectively included in the light-emitting parts EP adjacent to each other may include light-emitting materials showing different colors from each other. As an example, the light-emitting layer EML included in each of the light-emitting parts EP may emit light having at least one color of blue, red, and green, however, it should not be limited to or thereby. According to an embodiment, the light-emitting layers EML included in all the light-emitting parts EP may include a light-emitting material showing the same color. The light-emitting layer EML may provide blue light or white light. In addition, in Figure 5 In the embodiment, the light emitting layer EML and the functional layer FNL have different shapes from each other, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, in a plan view, the light emitting layer EML may have substantially the same shape as that of the functional layer FNL.

[0205] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. In detail, the functional layer FNL may be disposed between the first electrode EL1 and the light-emitting layer EML, or may be disposed between the second electrode EL2 and the light-emitting layer EML. According to an embodiment, the functional layer FNL may be disposed between the first electrode EL1 and the light-emitting layer EML and between the second electrode EL2 and the light-emitting layer EML. In an embodiment, the light-emitting layer EML may be inserted into the functional layer FNL, however, this may be only an example. According to an embodiment, the functional layer FNL may include a layer disposed between the light-emitting layer EML and the first electrode EL1 and / or a layer disposed between the light-emitting layer EML and the second electrode EL2, and each of these layers may be provided in plurality. However, they should not be limited thereto or thereby.

[0206] The functional layer FNL may control the movement of charges. The functional layer FNL may include a hole injection / transport material and / or an electron injection / transport material. The functional layer FNL may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0207] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be electrically connected to the connection wiring CN, and may be electrically connected to the pixel driver PDC. In an embodiment, the second electrode EL2 may be electrically connected to the connection transistor TR via the connection wiring CN.

[0208] As described above, the connection wiring CN may include a driver connection portion CD and a light emitting connection portion CE. The driver connection portion CD of the connection wiring CN may be electrically connected to the pixel driver PDC, and may be substantially electrically connected to the connection transistor TR. In an embodiment, the driver connection portion CD may be electrically connected to the drain region DR of the semiconductor pattern SP via the drain electrode pattern W2 after passing through the fifth insulating layer 50. The light emitting connection portion CE of the connection wiring CN may be electrically connected to the light emitting device LD. The light emitting connection portion CE may be defined in an area exposed and not covered by the sixth insulating layer 60, and the second electrode EL2 may be in contact with (e.g., directly in contact with) the light emitting connection portion CE. The tip portion TP may be defined in the light emitting connection portion CE.

[0209] Will refer to Figure 5 and Fig. 6A The light emitting connection portion CE of the connection wiring CN is described in more detail. Figure 5 and Fig. 6AAs shown in , the connection wiring CN may have a three-layer structure. In detail, the connection wiring CN may include a first layer L1, a second layer L2, and a third layer L3 that may be sequentially stacked on each other in the third direction DR3. The second layer L2 may include a material different from that of the first layer L1. In addition, the second layer L2 may include a material different from that of the third layer L3. The second layer L2 may have a thickness that is relatively thicker than that of the first layer L1. In addition, the second layer L2 may have a thickness that is relatively thicker than that of the third layer L3. The second layer L2 may include a material having high electrical conductivity. As an example, the second layer L2 may include aluminum (Al).

[0210] The first layer L1 may include a material having an etching rate lower than that of the second layer L2. For example, the second layer L2 may include a material having a higher etching selectivity relative to the first layer L1. As an example, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). The side surface L1_W of the first layer L1 may be defined outside the side surface L2_W of the second layer L2. For example, the light emitting connection portion CE of the connection wiring CN may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. For example, the light emitting connection portion CE of the connection wiring CN may have a shape in which the side surface L2_W of the second layer L2 may be recessed inward from the side surface L1_W of the first layer L1.

[0211] The third layer L3 may include a material having an etching rate lower than that of the second layer L2. For example, the third layer L3 and the second layer L2 may include materials having different etching selectivities relative to each other. As an example, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). The side surface L3_W of the third layer L3 may be defined outside the side surface L2_W of the second layer L2. For example, the light emitting connection portion CE of the connection wiring CN may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. In other words, the light emitting connection portion CE of the connection wiring CN may have an undercut shape or an overhang structure, and the tip portion TP of the light emitting connection portion CE may be defined by a portion of the third layer L3 that may protrude more than the second layer L2.

[0212] At least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2 may be exposed without being covered by the sixth insulating layer 60 and the pixel defining layer PDL. In detail, the first opening OP1 may be defined by the sixth insulating layer 60 to expose one end of the connection wiring CN, and the second opening OP2 may be defined by the pixel defining layer PDL to overlap with the first opening OP1. In a plan view, the second opening OP2 may have a size equal to or larger than that of the first opening OP1, however, the present disclosure should not be limited to or thereby. According to an embodiment, in a plan view, the size of the second opening OP2 may be less than or equal to that of the first opening OP1, as long as at least a portion of the tip portion TP and at least a portion of the side surface L2_W of the second layer L2 may be exposed.

[0213] The intermediate layer IML may be disposed on the pixel defining layer PDL. The intermediate layer IML may be disposed on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel defining layer PDL. In addition, the intermediate layer IML may also be disposed on a portion of the connection wiring CN exposed by the first opening OP1 of the sixth insulating layer 60. Fig. 6A As shown in , the intermediate layer IML may include one end IN1 provided along the side surface L2_W of the second layer L2 and another end IN2 provided along the upper surface of the tip portion TP. For example, when viewed in a cross-sectional view, the intermediate layer IML may be partially disconnected based on the tip portion TP in the region defined with the light emitting connection portion CE. However, in a plan view, the intermediate layer IML may have a region defined as a closed line by the partition SPR (refer to Figure 4B ) as a one-piece shape extending as a whole.

[0214] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may be disposed on a portion of the sixth insulating layer 60 exposed by the second opening OP2 of the pixel defining layer PDL. In addition, the second electrode EL2 may also be disposed on a portion of the connection wiring CN exposed by the first opening OP1 of the sixth insulating layer 60. Fig. 6A As shown in , the second electrode EL2 may include one end EN1 provided along the upper surface of the fifth insulating layer 50 and the other end EN2 provided along the upper surface of the tip portion TP. For example, when viewed in a cross-sectional view, the second electrode EL2 may be partially disconnected based on the tip portion TP in the region defined with the light emitting connection portion CE. However, in a plan view, the second electrode EL2 may have a region defined as a closed line by the partition SPR (refer to Figure 4B ) as a one-piece shape extending as a whole.

[0215] The end EN1 of the second electrode EL2 may be disposed along the side surface L2_W of the second layer L2 and may be in contact with the side surface L2_W of the second layer L2. In detail, due to the difference in deposition angles between the second electrode EL2 and the intermediate layer IML, the second electrode EL2 may be in contact with the side surface L2_W of the second layer L2 that is exposed through the tip portion TP and not covered by the intermediate layer IML. For example, the second electrode EL2 may be electrically connected to the connection wiring CN without a separate patterning process for the intermediate layer IML, and therefore, the light emitting device LD may be electrically connected to the pixel driver PDC via the connection wiring CN.

[0216] According to an embodiment, the other end IN2 of the intermediate layer IML and the other end EN2 of the second electrode EL2 may cover the side surface L3_W of the third layer L3, however, this may be only an example. According to an embodiment, at least a portion of the side surface L3_W of the third layer L3 may be exposed without being covered by the other end IN2 of the intermediate layer IML and / or the other end EN2 of the second electrode EL2.

[0217] As described above, the display panel DP may include a spacer SPR. The spacer SPR may be disposed on the pixel defining layer PDL. The second electrode EL2 and the intermediate layer IML may be commonly formed in a plurality of pixels using an open mask. The second electrode EL2 and the intermediate layer IML may be divided into a plurality of parts by the spacer SPR. As described above, for each light emitting portion EP, the spacer SPR may have a closed line shape, and therefore, the second electrode EL2 and the intermediate layer IML may be divided into a plurality of parts to be respectively disposed in each of the light emitting portions EP. For example, the second electrode EL2 and the intermediate layer IML may be disposed in each pixel, and may be electrically isolated or separated from other second electrodes EL2 and other intermediate layers IML that may be disposed in other pixels adjacent thereto.

[0218] Will refer to Figure 5 and Figure 6B The separator SPR is described in detail. Figure 6B As shown in , the spacer SPR may have an inverted tapered shape. For example, the angle θ (hereinafter, referred to as the cone angle) between the upper surface of the pixel defining layer PDL and the side surface SPR_W of the spacer SPR may be an obtuse angle, however, this may be only an example. The cone angle θ of the spacer SPR may be set in various ways, as long as the second electrode EL2 located in each pixel can be electrically disconnected from other second electrodes EL2 located in other pixels by the spacer SPR. In addition, the spacer SPR may have the same structure as that of the tip portion TP, and the present disclosure should not be particularly limited.

[0219] The spacer SPR may include a material having an insulating property, and specifically, may include an organic insulating material. The spacer SPR may include an inorganic insulating material, or may have a multilayer structure of an organic insulating material and an inorganic insulating material. According to an embodiment, the spacer SPR may include a conductive material. For example, the material of the spacer SPR should not be particularly limited as long as the second electrode EL2 located in each pixel can be electrically disconnected from other second electrodes EL2 located in other pixels.

[0220] The dummy layer UP may be disposed on the spacer SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the spacer SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 and the intermediate layer IML may be formed by the same process and may include the same material. The second dummy layer UP2 and the second electrode EL2 may be formed by the same process and may include the same material. For example, the first dummy layer UP1 and the second dummy layer UP2 may be formed during the manufacturing process of the intermediate layer IML and the second electrode EL2. According to an embodiment, the display panel DP may not include the dummy layer UP.

[0221] like Figure 6B As shown in , the second electrode EL2 may include a first end EN1a, and the second dummy layer UP2 may include a second end EN2a. The first end EN1a may be spaced apart from the spacer SPR and may be disposed on the pixel defining layer PDL. The second end EN2a may be separated from the first end EN1a and may be disposed on a side surface SPR_W of the spacer SPR. Figure 6B A structure in which the first end EN1a may be spaced a distance from the side surface SPR_W of the separator SPR is shown, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the first end EN1a may be in contact with the side surface SPR_W of the separator SPR as long as the first end EN1a is electrically disconnected from the second end EN2a. In addition, although the first end EN1a and the second end EN2a may be connected to each other without being distinguished from each other, in the case where the portion of the second electrode EL2 formed along the side surface SPR_W of the separator SPR and the portion of the second dummy layer UP2 formed along the side surface SPR_W of the separator SPR have a thin thickness and a high resistance and the second electrode EL2 may not be electrically connected to other second electrodes EL2 of other pixels adjacent thereto, the second electrode EL2 may be determined to be divided by the separator SPR.

[0222] According to the present disclosure, since the second electrode EL2 or the intermediate layer IML may not be formed on the side surface SPR_W of the separator SPR or may be thinly formed on the side surface SPR_W of the separator SPR, even if a separate patterning process using a mask may not be performed, the second electrode EL2 or the intermediate layer IML may be divided for each pixel. According to an embodiment, as long as the second electrode EL2 or the intermediate layer IML can be electrically disconnected between pixels adjacent to each other, the shape of the separator SPR may be changed in various ways and should not be particularly limited.

[0223] Reference again Figure 5 , the encapsulation layer ECL may be disposed on the light emitting device layer LDL. The encapsulation layer ECL may cover the light emitting device LD and may cover the partition SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 which may be sequentially stacked on each other, however, it should not be limited thereto or thereby. According to an embodiment, the encapsulation layer ECL may further include a plurality of inorganic layers and a plurality of organic layers. In addition, the encapsulation layer ECL may be a glass substrate.

[0224] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the light emitting device LD from moisture and oxygen from the outside of the display panel DP, and the organic layer OL may protect the light emitting device LD from foreign matter such as particles remaining in the formation process of the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer OL may include an acrylic organic layer, however, it should not be particularly limited.

[0225] The sensing layer ISL may sense external input. The sensing layer ISL may be formed on the encapsulation layer ECL through a continuous process. The sensing layer ISL may be disposed on (e.g., directly disposed on) the encapsulation layer ECL. In the present disclosure, the expression "the sensing layer ISL may be disposed on (e.g., directly disposed on) the encapsulation layer ECL" means that no intervening element may be between the sensing layer ISL and the encapsulation layer ECL. For example, a separate bonding member may not be disposed between the sensing layer ISL and the encapsulation layer ECL, however, this may be merely an example. According to an embodiment, the sensing layer ISL may be provided to be connected to the display panel DP through a bonding member after being separately formed, but it should not be limited to or thereby.

[0226] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this may be only an example, and the number of conductive layers and the number of insulating layers should not be particularly limited.

[0227] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single layer structure or a multilayer structure of a plurality of layers stacked on each other in the third direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0228] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be electrically connected to the first sensing conductive layer MTL1 via a contact hole CNT formed through the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure of a plurality of layers stacked on each other in the third direction DR3.

[0229] The sensing conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, an alloy thereof, or a combination thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (IZTO), or a combination thereof. In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, or a combination thereof.

[0230] The sensing conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The sensing conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0231] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may form a sensor to sense an external input in the sensing layer ISL. The sensor may be driven by a capacitance method (e.g., a mutual capacitance method or a self-capacitance method), however, this may be only an example. According to an embodiment, the sensor may be driven by a resistive film method, an ultrasonic method, or an infrared method instead of a capacitance method, and it should not be particularly limited.

[0232] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide, or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include various materials and may have various shapes as long as visibility of an image displayed by the display panel DP is not deteriorated.

[0233] Figure 7 is a schematic cross-sectional view of a display panel DP' according to an embodiment of the present disclosure. For ease of explanation, Figure 7 Shown with Figure 5 In the following, Figure 7 In the same reference numerals, Figures 1 to 6B , and therefore, detailed description of the same elements will be omitted.

[0234] and Figure 5 Compared with the display panel DP shown in Figure 7 The display panel DP' shown in FIG. 1 may further include a cover pattern CPP. The cover pattern CPP may be disposed on the sixth insulating layer 60. In addition, the cover pattern CPP may also be disposed on a portion of the connection wiring CN that may be exposed via the first opening OP1 defined by the sixth insulating layer 60. The cover pattern CPP may be disposed to overlap with the connection wiring CN. In detail, the cover pattern CPP may be disposed to overlap with the light emitting connection portion CE and / or the tip portion TP.

[0235] like Figure 7 As shown in FIG. 1 , in a cross-sectional view, the cap pattern CPP may be partially disconnected based on the tip portion TP in a region where the light emitting connection portion CE may be defined. However, in a plan view, the cap pattern CPP may have a region (refer to FIG. 1 ) in which a closed line may be defined by the partition SPR. Figure 4B ) as an integrated shape electrically connected as a whole. One end of the cover pattern CPP that may be partially disconnected may contact the side surface of the second layer L2 of the connection wiring CN, and the other end of the cover pattern CPP may be disposed on the third layer L3 of the connection wiring CN to cover the tip portion TP.

[0236] The cover pattern CPP may include a conductive material. Accordingly, the second electrode EL2 may be electrically connected to the connection wiring CN through the cover pattern CPP. For example, the cover pattern CPP may be in contact with the side surface of the second layer L2 of the connection wiring CN, the second electrode EL2 may be in contact with the cover pattern CPP, and thus, the cover pattern CPP, the second layer L2 of the connection wiring CN, and the second electrode EL2 may be electrically connected to each other. Since the cover pattern CPP may be positioned relatively adjacent to the light-emitting device LD compared to the second layer L2 of the connection wiring CN, the second electrode EL2 may be electrically connected to the second layer L2 by contacting only with the cover pattern CPP instead of contacting with the side surface of the second layer L2, and thus, the connection wiring CN and the second electrode EL2 may be more easily electrically connected to each other.

[0237] The cap pattern CPP may include a material having relatively low reactivity compared to the second layer L2 of the connection wiring CN. As an example, the cap pattern CPP may include copper (Cu), silver (Ag), a transparent conductive oxide, etc., or a combination thereof. Since the side surface of the second layer L2 of the connection wiring CN can be protected by the cap pattern CPP having relatively low reactivity, oxidation of the material included in the second layer L2 can be prevented. In addition, during the etching process of patterning the first electrode EL1, components such as silver (Ag) contained in the first electrode EL1 can be prevented from being reduced and remaining as particles causing defects.

[0238] The cap pattern CPP and the first electrode EL1 may be formed by the same process and may include the same material, however, this may be only an example. According to an embodiment, the cap pattern CPP and the first electrode EL1 may be formed by different processes and may include different materials.

[0239] Figure 8 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Figure 8 is shown with Figure 4A The parts correspond to the plan views of the parts. Figure 8 shows the display area DA and Figure 4A For ease of explanation, Figure 8 Only the display panel DP (refer to Figure 1 ) among the components of the separator SPR, the spacer SPC, the light emitting parts EP1, EP2 and EP3 and the light emitting connection parts CE1, CE2 and CE3. Figure 8 The arrangement of the spacer SPC in the plan view is described in detail. Figure 8 In the same / similar reference numerals, FIG. 4A to FIG. 7 , and therefore, detailed description of the same / similar elements will be omitted.

[0240] According to the present disclosure, each of the spacers SPC may overlap a portion of the spacer SPR in a plan view. In an embodiment, each of the spacers SPC may overlap the spacer SPR in a plan view.

[0241] The intersection portion IP defined by the first line L1-S and the second line L2-S intersecting the first line L1-S may be defined in the separator SPR. In an embodiment, the intersection portion IP may include a first intersection portion IP1 and a second intersection portion IP2. The first intersection portion IP1 may have a cross shape in a plan view, and the second intersection portion IP2 may have a T shape in a plan view.

[0242] In an embodiment, each of the spacers SPC may overlap with one of the intersection portions IP of the partition SPR. In more detail, some of the spacers SPCa of the spacers SPC may overlap with the first intersection portion IP1, and other spacers SPCb of the spacers SPC may overlap with the second intersection portion IP2.

[0243] In an embodiment, the spacer SPC may be arranged to overlap only some of the intersections IP of the separator SPR. The spacer SPC may overlap with the some of the intersections, respectively. For example, some of the first intersections IP1 and some of the second intersections IP2 may overlap with the spacer SPC, respectively, and other first intersections IP1 and other second intersections IP2 may not overlap with the spacer SPC. However, the number and position of the spacer SPC should not be limited to Figure 8 The quantities and locations shown in .

[0244] Fig. 9A According to an embodiment of the present disclosure, Figure 8 FIG. 1 is a schematic enlarged cross-sectional view of a region of the display panel DP taken along line II-II′. Fig. 9B According to an embodiment of the present disclosure, Figure 8 A schematic enlarged cross-sectional view of a region of the display panel DP taken along line III-III'. Fig. 9A and Fig. 9B In the same / similar reference numerals, Figures 5 to 8 , and therefore, detailed description of the same / similar elements will be omitted.

[0245] refer to Fig. 9A, the spacer SPC may be disposed between the pixel defining layer PDL and the spacer SPR. For example, the spacer SPC may be disposed on (eg, directly disposed on) the upper surface UP of the pixel defining layer PDL and may be disposed under the spacer SPR.

[0246] The spacer SPR may include a lower surface LS adjacent to the pixel defining layer PDL and an upper surface US opposite to the lower surface LS. Since the spacer SPR has an inverted tapered shape, a width W-US of the upper surface US of the spacer SPR may be greater than a width W-LS of the lower surface LS of the spacer SPR in a cross-sectional view.

[0247] In the cross-sectional view, the width WC of the spacer SPC in one direction may be equal to or less than the width W-US of the upper surface US of the spacer SPR in the one direction. In the plan view, the entire area of ​​the spacer SPC may overlap with the spacer SPR. In other words, the spacer SPC may not be exposed but covered by the spacer SPR.

[0248] According to an embodiment, as the spacer SPC may be disposed under the spacer SPR, the width WC of the spacer SPC in the one direction may be equal to or greater than the width W-LS of the lower surface LS of the spacer SPR in the one direction. Fig. 9A A structure is shown in which the width WC of the spacer SPC in the one direction may be substantially equal to the width W-LS of the lower surface LS of the spacer SPR in the one direction.

[0249] Fig. 9B Schematic cross-sectional view of the display panel DP taken along the extending direction of the spacer SPR is shown. Fig. 9B , in a cross-sectional view taken along the extension direction of the spacer SPR, the spacer SPR may cover the spacer SPC while extending. The upper surface US of the spacer SPR may include a portion protruding to the encapsulation layer ECL through the spacer SPC in the thickness direction. Fig. 9B A structure in which the upper surface US of the separator SPR protruding through the spacer SPC includes an approximately flat portion is shown as a representative example, however, the upper surface US of the separator SPR may have a dome shape as a whole, and depending on the width of the spacer SPC, the upper surface US of the separator SPR may protrude without an approximately flat portion.

[0250] In an embodiment, a portion of the upper surface US of the spacer SPR overlapping the spacer SPC may be spaced further from the pixel defining layer PDL than a portion of the upper surface US of the spacer SPR not overlapping the spacer SPC. For example, a height h1 from the upper surface UP of the pixel defining layer PDL to a portion of the upper surface US of the spacer SPR overlapping the spacer SPC may be greater than a height h0 from the upper surface UP of the pixel defining layer PDL to a portion of the upper surface US of the spacer SPR not overlapping the spacer SPC.

[0251] In the manufacturing process of the display panel DP, the light-emitting layer EML can be formed by a process of depositing a light-emitting material using a fine metal mask (FMM). Accordingly, the light-emitting material can be deposited for each pixel, and therefore, a light-emitting layer EML patterned for each pixel can be formed. According to an embodiment, in the case of forming the light-emitting layer EML, a fine metal mask can be disposed on the spacer SPR and can be supported by the spacer SPR. Since the upper surface US of the spacer SPR includes a portion protruding in the thickness direction in the area overlapping with the spacer SPC in a plan view, the fine metal mask can contact the portion of the upper surface US of the spacer SPR that protrudes upward due to the presence of the spacer SPC below.

[0252] On the other hand, unlike the embodiment, in the case where the spacer SPC may not be disposed under the spacer SPR, the upper surface US of the spacer SPR may be completely flat. Accordingly, in the formation of the light emitting layer EML, the fine metal mask may completely contact the upper surface US of the spacer SPR.

[0253] According to the present disclosure, since the spacer SPC overlapping the spacer SPR can be disposed under the spacer SPR, the contact area between the fine metal mask and the upper surface US of the spacer SPR can be reduced compared to the case where the spacer SPC is not disposed. Accordingly, the degree of damage to the spacer SPR caused by the dent defect of the fine metal mask can be reduced. Accordingly, after the formation of the light-emitting layer EML, the reliability of the spacer SPR can be improved.

[0254] In the case where damage occurs in the separator after the light-emitting layer is formed, during a subsequent process of forming the first inorganic layer of the encapsulation layer, the first inorganic layer may fail to seal the damaged portion of the separator. As an example, cracks may be formed in the first inorganic layer due to the damaged portion of the separator, and the first inorganic layer may be broken. Moisture or oxygen may enter the light-emitting layer, foreign matter may enter the light-emitting layer, and as a result, light emission defects may occur in the final product.

[0255] According to the embodiment, since the spacer SPR with improved reliability can be provided after the process of forming the light emitting layer EML, defects of the first inorganic layer IL1 can be reduced or prevented. Accordingly, moisture, oxygen, or foreign matter can be prevented from entering the light emitting layer EML. Therefore, process reliability can be improved, and the display device DD (refer to Figure 1 ) light emission defects.

[0256] According to an embodiment, since the number and / or area of ​​the spacers SPC can be adjusted, the area of ​​the upper surface US of the spacer SPR that can contact the fine metal mask can be controlled. For example, in the case where the area of ​​the upper surface US of the spacer SPR that can contact the fine metal mask is controlled to fully support the fine metal mask and minimize damage to the spacer SPR, the limitation of controlling the area can be minimized.

[0257] The display panel DP according to the embodiment may include a partition opening OP-S (refer to Figure 4A ) to provide cathode electrodes EL2_1, EL2_2 and EL2_3 separated from each other for each pixel (refer to Figure 4B ). Accordingly, the partition member SPR may have a shape surrounding the light emitting parts EP1, EP2 and EP3 (refer to Figure 4B According to an embodiment, since the spacer SPC can be set to overlap with the partition SPR, no additional space is required to position the spacer SPC, and even if the spacer SPC can be provided, the size of the light emitting area may not be reduced.

[0258] The spacer SPC may include an organic material. As an example, the spacer SPC may include polyimide (PI).

[0259] The spacer SPC may be formed by coating, patterning and curing an organic material. After the spacer SPC may be formed, the spacer SPR may be formed. According to an embodiment, the spacer SPR may also be formed by coating, patterning and curing an organic material. However, the method of forming the spacer SPC and the spacer SPR should not be limited thereto or thereby.

[0260] Fig. 10A and Fig. 10B is a schematic enlarged cross-sectional view of a region of a display panel DP-1 according to an embodiment of the present disclosure. Fig. 10A According to an embodiment of the present disclosure, Figure 8 Schematic enlarged cross-sectional view of a region of the display panel DP-1 taken along line II-II'. Fig. 10B According to an embodiment of the present disclosure, Figure 8A schematic enlarged cross-sectional view of a region of the display panel DP-1 taken along line III-III'. Fig. 10A and Fig. 10B In the same / similar reference numerals, Figures 5 to 9B , and therefore, detailed description of the same / similar elements will be omitted.

[0261] refer to Fig. 10A and Fig. 10B , the spacer SPC-1 may be disposed on the separator SPR. The spacer SPC-1 may be disposed (eg, directly disposed) on an upper surface U-S1 of the separator SPR.

[0262] When viewed in a cross-sectional view, a width W-C1 of the spacer SPC-1 in one direction may be equal to or smaller than a width W-US of an upper surface U-S1 of the spacer SPR in the one direction. In a plan view, the entire area of ​​the spacer SPC-1 may overlap with the spacer SPR.

[0263] As the spacer SPC-1 may be disposed on the separator SPR, a width W-C1 of the spacer SPC-1 in the one direction may be equal to or smaller than a width W-LS of a lower surface L-S1 of the separator SPR in the one direction. Fig. 10A A structure in which the width W-C1 of the spacer SPC-1 in the one direction may be substantially equal to the width W-LS of the lower surface L-S1 of the spacer SPR in the one direction is illustrated as a representative example.

[0264] In an embodiment, since the spacer SPR may be disposed to be in full contact with the upper surface UP of the pixel defining layer PDL, the upper surface U-S1 of the spacer SPR may be completely flat. The spacer SPC-1 may be covered by the first dummy layer UP1 above the upper surface U-S1 of the spacer SPR.

[0265] According to an embodiment, in the process of forming the light-emitting layer EML, the fine metal mask may be disposed on the spacer SPC-1. For example, the fine metal mask may be in contact with the upper surface U-C1 of the spacer SPC-1. Since the spacer SPC-1 may be disposed on the spacer SPR, the fine metal mask may not be in contact with the upper surface U-S1 of the spacer SPR. Accordingly, the area in which the fine metal mask may be in contact with the component supporting the fine metal mask may be reduced. As a result, the degree of damage to the spacer SPC-1 and the spacer SPR caused by the dent defects of the fine metal mask may be reduced. For example, after the light-emitting layer EML is formed, the reliability of the spacer SPC-1 and the spacer SPR may be improved, and defects in the first inorganic layer IL1 may be prevented. Therefore, the process reliability may be improved, and defects in the display device DD (reference Figure 1 ) light emission defects.

[0266] According to an embodiment, the area in which the fine metal mask can contact the upper surface U-C1 of the spacer SPC-1 can be controlled by adjusting the number and / or area of ​​the spacer SPC-1. For example, the limitation of controlling the area can be minimized while controlling the area of ​​the upper surface U-C1 of the spacer SPC-1 that can contact the fine metal mask to fully support the fine metal mask and minimize damage to the spacer SPC-1 and the separator SPR.

[0267] The display panel DP-1 according to the embodiment may include a partition opening OP-S (refer to Figure 4A ) to provide cathode electrodes EL2_1, EL2_2 and EL2_3 separated from each other for each pixel (refer to Figure 4B ). Accordingly, the partition member SPR may have a shape surrounding the light emitting parts EP1, EP2 and EP3 (refer to Figure 4B )(i.e., the light emitting area). According to an embodiment, since the spacer SPC-1 can be set on the upper surface U-S1 of the partition SPR, no additional space is required to position the spacer SPC-1, and even if the spacer SPC-1 can be provided, the size of the light emitting area may not be reduced.

[0268] FIG. 11A to FIG. 11C is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. FIG. 11A to FIG. 11C It is a separator SPR (reference Figure 8 ) is an enlarged plan view of a first intersection portion IP1, and shows the shapes of spacers SPCa, SPCa1 and SPCa2 respectively overlapping the first intersection portion IP1 in the plan view. FIG. 11A to FIG. 11CAs a representative example, the spacers SPCa, SPCa1, and SPCa2 may be provided in the spacer SPR (refer to Figure 8 ) on the structure.

[0269] refer to FIG. 11A to FIG. 11C , the first intersection portion IP1 may be defined as a separator SPR (refer to Figure 8 ) of a cross-shaped portion where the first line L1-S and the second line L2-S intersect each other in a plan view.

[0270] The first intersection portion IP1 may include a first intersection region CC1 , first-first line regions L11 and L12 , second-first line regions L21 and L22 , and a first protruding region P1 .

[0271] The first intersection region CC1 may be a region where the first line L1-S intersects the second line L2-S. The first-first line region L11 and the first-second line region L12 may extend from the first intersection region CC1 of the first line L1-S in opposite directions to each other in the first direction DR1. The second-first line region L21 and the second-second line region L22 may extend from the first intersection region CC1 of the second line L2-S in opposite directions to each other in the second direction DR2.

[0272] The first protrusion area P1 may protrude from corresponding line areas adjacent to each other among the first-first line area L11, the first-second line area L12, the second-first line area L21, and the second-second line area L22. The first protrusion area P1 may include the first-first protrusion area P11, the first-second protrusion area P12, the first-third protrusion area P13, and the first-fourth protrusion area P14.

[0273] The first-first protruding area P11 may protrude from the first-first line area L11 and the second-first line area L21. The first-first protruding area P11 may protrude from an area of ​​the first-first line area L11 and the second-first line area L21 adjacent to the first intersection area CC1 toward a separation opening OP-S (refer to Figure 8 ). The first-second protruding area P12 may protrude from the first-first line area L11 and the second-second line area L22. The first-second protruding area P12 may protrude from an area of ​​the first-first line area L11 and the second-second line area L22 adjacent to the first intersection area CC1 toward the separation opening OP-S defined by the first-first line area L11 and the second-second line area L22 (refer to Figure 8 ) protrudes from the inside.

[0274] The first-third protruding area P13 may protrude from the first-second line area L12 and the second-first line area L21. The first-third protruding area P13 may protrude from an area of ​​the first-second line area L12 and the second-first line area L21 adjacent to the first intersection area CC1 toward the separation opening OP-S defined by the first-second line area L12 and the second-first line area L21 (refer to Figure 8 ). The first-fourth protruding area P14 may protrude from the first-second line area L12 and the second-second line area L22. The first-fourth protruding area P14 may protrude from an area of ​​the first-second line area L12 and the second-second line area L22 adjacent to the first intersection area CC1 toward the separation opening OP-S defined by the first-second line area L12 and the second-second line area L22 (refer to Figure 8 ) protrudes from the inside.

[0275] like Fig.11A and Fig. 11B As shown in FIG, the spacers SPCa and SPCa1 overlapping the first intersection portion IP1 may have a quadrilateral shape.

[0276] As an example, Fig.11A As shown in FIG. 1 , the spacer SPCa overlapped with the first intersection portion IP1 may have a rectangular shape (eg, a square shape) having sides extending in the first direction DR1 and sides extending in the second direction DR2 .

[0277] As an example, Fig. 11B As shown in , the spacer SPCa1 may have a quadrilateral shape (e.g., a rhombus shape or a rhombus shape) having sides extending in the fourth direction DR4 and sides extending in the fifth direction DR5. The fourth direction DR4 may be defined as a direction intersecting the first direction DR1 and the second direction DR2, and the fifth direction DR5 may be defined as a direction intersecting the fourth direction DR4. Fig. 11B As a representative example, the fifth direction DR5 may be defined to be perpendicular to the fourth direction DR4.

[0278] like Fig.11A and Fig. 11BAs shown in , the spacers SPCa and SPCa1 overlapping the first intersection portion IP1 may overlap at least a portion of each of the first intersection area CC1, the first-first line area L11, the first-second line area L12, the second-first line area L21, the second-second line area L22, and the first protruding area P1, however, the present disclosure should not be limited to or thereby. According to an embodiment, the spacers SPCa and SPCa1 overlapping the first intersection portion IP1 may be arranged not to overlap with the first protruding area P1, or may be arranged not to overlap with the first-first line area L11, the first-second line area L12, the second-first line area L21, and the second-second line area L22.

[0279] According to the embodiment, Fig. 11C As shown in , the spacer SPCa2 overlapping the first intersection portion IP1 may have a cross shape defined by a portion extending in the first direction DR1 and a portion extending in the second direction DR2 and intersecting the portion extending in the first direction DR1. The portion extending in the first direction DR1 may overlap the first line L1-S, and the portion extending in the second direction DR2 may overlap the second line L2-S.

[0280] Fig. 11C A structure is shown as a representative example in which the spacer SPCa2 overlapping the first intersection portion IP1 overlaps at least a portion of each of the first intersection area CC1, the first-first line area L11, the first-second line area L12, the second-first line area L21, and the second-second line area L22 and does not overlap the first protruding area P1. However, the present disclosure should not be limited to or thereby, and the spacer SPCa2 may be provided to overlap the first protruding area P1.

[0281] However, the shapes of the spacers SPCa, SPCa1 and SPCa2 each overlapping the first intersection portion IP1 should not be particularly limited, and as long as the spacers SPCa, SPCa1 and SPCa2 can be set to overlap the first intersection portion IP1, the spacers SPCa, SPCa1 and SPCa2 each overlapping the first intersection portion IP1 can have a variety of shapes.

[0282] FIG. 12A to FIG. 12C is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. FIG. 12A to FIG. 12C It is a separator SPR (reference Figure 8 ) is an enlarged plan view of the second intersection portion IP2, and shows the shapes of the spacers SPCb, SPCb1 and SPCb2 respectively overlapping the second intersection portion IP2 in the plan view. FIG. 12A to FIG. 12CAs a representative example, the spacers SPCb, SPCb1, and SPCb2 may be provided in the separator SPR (refer to Figure 8 ) on the structure.

[0283] refer to Fig. 12B , the second intersection portion IP2 may include a separator SPR (reference Figure 8 ), and therefore, the second intersection portion IP2 may have a T-shape.

[0284] The second intersection portion IP2 may include a second intersection region CC2 , a first-third line region L13 , a second-third line region L23 , a second-fourth line region L24 , and a second protruding region P2 .

[0285] The second intersection region CC2 may be a region where the first line L1-S intersects the second line L2-S. The first to third line regions L13 of the first line L1-S may extend in the first direction DR1 from the second intersection region CC2. FIG. 12A to FIG. 12C A structure in which the first-third line region L13 extends from the second intersection region CC2 in the first direction DR1 is shown as a representative example, however, according to the position of the second intersection portion IP2 in the separator SPR, the first-third line region L13 may extend from the second intersection region CC2 in a direction opposite to the first direction DR1. The second-third line region L23 and the second-fourth line region L24 of the second line L2-S may extend from the second intersection region CC2 in directions opposite to each other in the second direction DR2.

[0286] The second protrusion region P2 may protrude from corresponding line regions adjacent to each other among the first-third line region L13, the second-third line region L23, and the second-fourth line region L24. The second protrusion region P2 may include a second-first protrusion region P21 and a second-second protrusion region P22.

[0287] The second-first protruding area P21 may protrude from the first-third line area L13 and the second-third line area L23. The second-first protruding area P21 may protrude from an area of ​​the first-third line area L13 and the second-third line area L23 adjacent to the second intersection area CC2 toward the separation opening OP-S defined by the first-third line area L13 and the second-third line area L23 (refer to Figure 8 ). The second-second protruding area P22 may protrude from the first-third line area L13 and the second-fourth line area L24. The second-second protruding area P22 may protrude from an area of ​​the first-third line area L13 and the second-fourth line area L24 adjacent to the second intersection area CC2 toward the separation opening OP-S defined by the first-third line area L13 and the second-fourth line area L24 (refer to Figure 8 ) protrudes from the inside.

[0288] According to the embodiment, Fig. 12A As shown in FIG. 1 , the spacer SPCb overlapped with the second intersection portion IP2 may have a quadrilateral shape (eg, a rectangular shape) defined by sides extending in the first direction DR1 and sides extending in the second direction DR2 .

[0289] like Fig. 12A As shown in , the spacer SPCb overlapping the second intersection portion IP2 may overlap at least a portion of each of the second intersection area CC2, the first-third line area L13, the second-third line area L23, the second-fourth line area L24, and the second protruding area P2. However, the present disclosure should not be limited to or restricted thereto. According to an embodiment, the spacer SPCb overlapping the second intersection portion IP2 may be arranged not to overlap the second protruding area P2, or may be arranged not to overlap the first-third line area L13, the second-third line area L23, and the second-fourth line area L24.

[0290] According to the embodiment, Fig. 12B As shown in , the spacer SPCb1 overlapping the second intersection portion IP2 may have a T shape defined by a portion extending in the second direction DR2 and a portion extending in the first direction DR1 from the portion extending in the second direction DR2. The portion extending in the first direction DR1 may overlap the first line L1-S, and the portion extending in the second direction DR2 may overlap the second line L2-S.

[0291] Fig. 12B A structure is shown in which the spacer SPCb1 overlapping the second intersection portion IP2 overlaps at least a portion of each of the second intersection area CC2, the first-third line area L13, the second-third line area L23, and the second-fourth line area L24 and does not overlap the second protruding area P2, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the spacer SPCb1 may be disposed to overlap the second protruding area P2.

[0292] According to the embodiment, Fig. 12C As shown in, the spacer SPCb2 overlapping with the second intersection portion IP2 may have a triangular shape. The spacer SPCb2 overlapping with the second intersection portion IP2 may include a first side S1, a second side S2 and a third side S3. The first side S1 may extend in the second direction DR2. In an embodiment, the first side S1 may overlap with the second side L2-S. In addition, the vertex P at which the second side S2 of the spacer SPCb2 intersects with the third side S3 may face the first side S1 and may overlap with the first line L1-S. Fig. 12CA structure in which the spacer SPCb2 overlapping the second intersection portion IP2 has an isosceles triangle shape in which the second side S2 and the third side S3 have the same length is illustrated as a representative example, however, the present disclosure should not be limited thereto or thereby.

[0293] like Fig. 12C As shown in , the spacer SPCb2 overlapping the second intersection portion IP2 may overlap at least a portion of each of the second intersection area CC2, the first-third line area L13, the second-third line area L23, the second-fourth line area L24, and the second protruding area P2. However, according to an embodiment, the spacer SPCb2 overlapping the second intersection portion IP2 may be configured not to overlap the second protruding area P2, or may also be configured not to overlap the first-third line area L13, the second-third line area L23, and the second-fourth line area L24.

[0294] However, the shapes of the spacers SPCb, SPCb1 and SPCb2 each overlapping the second intersection portion IP2 should not be particularly limited, and as long as the spacers SPCb, SPCb1 and SPCb2 can be set to overlap the second intersection portion IP2, the spacers SPCb, SPCb1 and SPCb2 each overlapping the second intersection portion IP2 can have a variety of shapes.

[0295] refer to Figure 8 as well as FIG. 11A to FIG. 12C Due to the etching deviation, the first line L1-S and the second line L2-S may intersect in a rounded shape in the intersection portion IP without intersecting vertically. As an example, the first protruding area P1 and the second protruding area P2 may correspond to portions around corners of the spacer SPR that remain and are not etched during a process of etching the spacer SPR to form the separation opening OP-S.

[0296] According to an embodiment, in the case where the spacer SPC may be arranged to overlap with the intersection portion IP, the spacer SPC may be arranged to overlap with the first protruding area P1 or the second protruding area P2. In particular, in the case where the spacer SPC is positioned below the separator SPR, the area where the separator SPR can be supported may be wider than other areas. Therefore, in the case where the spacer SPC overlaps with the intersection portion IP, the spacer SPC may support the separator SPR more stably.

[0297] Fig.13 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig.13 is with Figure 4A The floor plan corresponding to the floor plan. Fig.13 The display area DAa is shown Figure 4AFor ease of explanation, Fig.13 Only the display panel DP (refer to Figure 1 ) includes a separator SPR, a spacer SPC_a, light emitting parts EP1, EP2 and EP3, and light emitting connection parts CE1, CE2 and CE3.

[0298] refer to Fig.13 , a portion of each of the spacers SPC_a may be arranged to overlap with the separator SPR in a plan view. In a plan view, only the portion of each of the spacers SPC_a may overlap with the separator SPR. In other words, the other portion of each of the spacers SPC_a may be exposed without being covered by the separator SPR.

[0299] In an embodiment, each of the spacers SPC_a may overlap one of the intersection portions IP of the spacer SPR. In more detail, some of the spacers SPCa_a of the spacers SPC_a may overlap the first intersection portion IP1, and other spacers SPCb_a of the spacers SPC_a may overlap the second intersection portion IP2.

[0300] In an embodiment, the spacer SPC_a may be arranged to overlap only some of the intersection portions IP of the spacer SPR. The spacer SPC_a may overlap the some of the intersection portions, respectively. However, the number and position of the spacer SPC_a should not be limited to Fig.13 The quantities and locations shown in .

[0301] Each of the spacers SPCa_a overlapping the first intersection portion IP1 may be in a quadrilateral shape or a cross shape. The quadrilateral shape may be similar to the cross shape as shown in FIG. Fig.11A The described quadrilateral shape including the sides extending in the first direction DR1 and the sides extending in the second direction DR2 corresponds to, or may be similar to, as described with reference to Fig. 11B The description includes the fourth direction DR4 (reference Fig. 11B ) and in the fifth direction DR5 (reference Fig. 11B ) corresponds to a quadrilateral shape with sides extending from the top. The cross shape can be similar to Fig. 11C , corresponds to a cross shape defined by a portion extending in the first direction DR1 and a portion extending in the second direction DR2 and intersecting the portion extending in the first direction DR1.

[0302] For example, in Fig.13 The shape of the spacer SPCa_a disposed to overlap with the first intersection portion IP1 may be different from FIG. 11A to FIG. 11C The spacers SPCa, SPCa1 and SPCa2 shown in FIG. 1 are similar in shape, and Fig.13 The spacer SPCa_a and FIG. 11A to FIG. 11C The only difference between the spacers SPCa, SPCa1, and SPCa2 may be that the size of the spacer SPCa_a may be increased to allow the spacer SPCa_a to be exposed without being covered by the partition SPR in a plan view.

[0303] Each of the spacers SPCb_a overlapping the second intersection portion IP2 may have a quadrilateral shape, a T shape, or a triangular shape. The quadrilateral shape may be similar to Fig. 12A The T-shape corresponds to a quadrilateral shape defined by the sides extending in the first direction DR1 and the sides extending in the second direction DR2 as shown in FIG. Fig. 12B The triangular shape may correspond to the T shape defined by the portion extending in the second direction DR2 and the portion extending in the first direction DR1 from the portion extending in the second direction DR2 as shown in FIG. Fig. 12C The first side S1 (reference Fig. 12C ) extends in the second direction DR2 and the second side S2 (reference Fig. 12C ) and the third side S3 (reference Fig. 12C ) intersects the vertex P (reference Fig. 12C ) corresponds to a triangular shape overlapping the first line L1-S.

[0304] For example, Fig.13 The shape of the spacer SPCb_a overlapping the second intersection portion IP2 may be FIG. 12A to FIG. 12C The spacers SPCb, SPCb1 and SPCb2 are similar in shape, and Fig.13 The spacer SPCb_a and FIG. 12A to FIG. 12C The only difference between the spacers SPCb, SPCb1 and SPCb2 may be that the size of the spacer SPCb_a may be increased to allow the spacer SPCb_a to be exposed without being covered by the partition SPR in a plan view. In the case where the spacer SPCb_a has a triangular shape, unlike Fig. 12C , the first side S1 (reference Fig. 12C ) can be set outside the second line L2-S.

[0305] Fig.14 According to an embodiment of the present disclosure, Fig.13 A schematic enlarged cross-sectional view of a region of the display panel DP taken along line IV-IV'. Fig.14 In the same / similar reference numerals, Figures 5 to 9B , and therefore, detailed description of the same / similar elements will be omitted.

[0306] refer to Fig.14, the spacer SPC_a may be disposed between the pixel defining layer PDL and the spacer SPR. For example, the spacer SPC_a may be disposed (eg, directly disposed) on the upper surface UP of the pixel defining layer PDL and may be disposed under the spacer SPR.

[0307] In the cross-sectional view, the width W-Ca of the spacer SPC_a in one direction may be greater than the width W-US of the upper surface US of the separator SPR in the one direction. Accordingly, a portion of the spacer SPC_a may be exposed in the plan view without being covered by the spacer SPR. According to an embodiment in which the width W-Ca of the spacer SPC_a may be greater than the width W-US of the spacer SPR, the spacer SPC_a may not be disposed on the spacer SPR and may be disposed only under the spacer SPR.

[0308] Fig.15 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig.15 is with Figure 4A The parts correspond to the plan views of the parts. Fig.15 shows the display area DAb and Figure 4A For ease of explanation, Fig.15 Only the display panel DP (refer to Figure 1 ) includes a separator SPR, a spacer SPC_b, light emitting parts EP1, EP2 and EP3, and light emitting connection parts CE1, CE2 and CE3.

[0309] refer to Fig.15 , the spacers SPC_b may overlap with the intersection portions IP of the spacers SPR, respectively. The spacers SPC_b may be arranged to overlap with the intersection portions IP of the spacers SPR, and each of the spacers SPC_b may overlap with a corresponding intersection portion among the intersection portions IP. For example, in a plan view, each of the intersection portions IP may overlap with one spacer SPC_b.

[0310] The intersection portion IP of the spacer SPR may include a first intersection portion IP1 having a cross shape and a second intersection portion IP2 having a T shape. Some of the spacers SPCa_b among the spacers SPC_b may overlap with the first intersection portion IP1, respectively, and other spacers SPCb_b among the spacers SPC_b may overlap with the second intersection portion IP2, respectively. For example, each of the first intersection portion IP1 and the second intersection portion IP2 may overlap with a corresponding spacer among the spacers SPC_b.

[0311] Fig.15As a representative example, a structure in which the entire area of ​​each of the spacers SPC_b overlaps with the spacer SPR in a plan view is shown, however, the present disclosure should not be limited thereto or thereby. For example, a portion of the spacer SPC_b may be exposed in a plan view without being covered by the spacer SPR, as shown in FIG. Fig.13 described.

[0312] Fig.16 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig.16 is with Figure 4A The parts correspond to the plan views of the parts. Fig.16 shows the display area DAc and Figure 4A For ease of explanation, Fig.16 Only the display panel DP (refer to Figure 1 ) includes the spacer SPR, the spacer SPC_c, the light emitting parts EP1, EP2 and EP3, and the light emitting connection parts CE1, CE2 and CE3.

[0313] refer to Fig.16 , each of the spacers SPC_c may be disposed to overlap at least one of the first line L1-S and the second line L2-S. The spacers SPC_c may not overlap the intersection portion IP.

[0314] Fig.16 A structure in which the spacer SPC_c overlaps only the first line L1-S is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the spacer SPC_c may overlap only the second line L2-S. According to an embodiment, some of the spacers SPC_c may overlap the first line L1-S, and other of the spacers SPC_c may overlap the second line L2-S. In addition, the number and position of the spacers SPC_c should not be limited to Fig.16 quantity and location.

[0315] Fig.16 A structure in which a portion of each of the spacers SPC_c may be exposed in a plan view without being covered by the spacer SPR is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. Figure 8 As described above, the entire region of each of the spacers SPC_c may be disposed to overlap the spacer SPR in a plan view.

[0316] Fig.17 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig.17 is with Figure 4A The parts correspond to the plan views of the parts. Fig.17 shows the display area DAd and Figure 4A For ease of explanation, Fig.17 Only the display panel DP (refer to Figure 1 ) includes a separator SPR, a spacer SPC_d, light emitting parts EP1, EP2 and EP3, and light emitting connection parts CE1, CE2 and CE3 among the components.

[0317] refer to Fig.17 , the spacer SPC_d may include a first spacer SPC1_d and a second spacer SPC2_d.

[0318] The first spacer SPC1_d may overlap one of the intersection portions IP. Fig.17 A structure in which one first spacer SPC1_d overlaps the first intersection portion IP1 is shown as a representative example, however, the first spacer SPC1_d may overlap the second intersection portion IP2. In addition, the number and position of the first spacer SPC1_d should not be limited to Fig.17 The embodiment shown in .

[0319] The second spacer SPC2_d may be disposed to overlap one of the first line L1 -S and the second line L2 -S. Fig.17 As a representative example, a structure in which a plurality of second spacers SPC2_d may be disposed to overlap only the first line L1-S is shown. However, according to embodiments, the second spacers SPC2_d may overlap only the second line L2-S, or some of the second spacers SPC2_d may overlap the first line L1-S and other of the second spacers SPC2_d may overlap the second line L2-S. In addition, the number and position of the second spacers SPC2_d should not be limited to Fig.17 Embodiment of the invention.

[0320] Fig.17 As a representative example, a structure in which a portion of each of the spacers SPC_d may be exposed in a plan view without being covered by the spacer SPR is shown, however, the present disclosure should not be limited thereto or thereby. Figure 8 As described above, the entire area of ​​each of the spacers SPC_d may overlap with the spacer SPR in a plan view.

[0321] Fig.18 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig.19 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1) area. Fig.18 is with Figure 4A The parts correspond to the plan views of the parts. Fig.18 shows the display area DAe and Figure 4A For ease of explanation, Fig.18 Only the display panel DP (refer to Figure 1 ) includes the spacer SPR, the spacer SPC_e, the light emitting parts EP1, EP2 and EP3, and the light emitting connection parts CE1, CE2 and CE3.

[0322] refer to Fig.18 , the spacer SPC_e may include a first spacer SPC1_e and a third spacer SPC3_e.

[0323] The first spacer SPC1_e may overlap one of the intersection portions IP. Fig.18 A structure in which some of the first spacers SPC1a_e overlap the first intersection portion IP1 and other first spacers SPC1b_e overlap the second intersection portion IP2 is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the first spacer SPC1_e may overlap only the first intersection portion IP1, or may overlap only the second intersection portion IP2. In addition, the number and position of the first spacers SPC1_e should not be limited to Fig.18 Embodiment of the invention.

[0324] The third spacer SPC3_e may overlap with the bent portion BP of the spacer SPR. In an embodiment, the bent portion BP may be defined in the spacer SPR. According to an embodiment, due to etching deviation, the first line L1-S and the second line L2-S may extend to each other in a rounded shape without extending perpendicularly to each other, and therefore, the bent portion BP may be defined in the spacer SPR.

[0325] Fig.19 2 is an enlarged plan view of a bent portion BP of the separator SPR, and illustrates a third separator SPC3_e overlapping the bent portion BP. Fig.19 As a representative example, a structure in which the third spacer SPC3_e may be disposed under the spacer SPR is shown (refer to Fig. 9A ). refer to Fig.18 and Fig.19 The bending portion BP may include a bending area B, first to fourth line areas L14 of a first line L1-S extending from the bending area B in the first direction DR1, and second to fifth line areas L25 of a second line L2-S extending from the bending area B in the second direction DR2.

[0326] According to an embodiment, the third spacer SPC3_e overlapping the bending portion BP may have an L shape. The third spacer SPC3_e may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 may overlap the first to fourth line regions L14 and the bending region B, and the portion extending in the second direction DR2 may overlap the second to fifth line regions L25 and the bending region B. However, the shape of the third spacer SPC3_e should not be particularly limited, and as long as the third spacer SPC3_e overlaps the bending portion BP, the third spacer SPC3_e may have various shapes.

[0327] Fig.18 Only one third spacer SPC3_e is shown, however, the number and position of the third spacer SPC3_e should not be limited to Fig.18 The embodiment shown in .

[0328] Fig.18 1 shows a structure in which a portion of each of the spacers SPC_e may be exposed in a plan view without being covered by the spacer SPR as a representative example, and Figure 8 As shown in , the entire area of ​​each of the spacers SPC_e may overlap with the spacer SPR in a plan view.

[0329] Fig. 20 is a display panel DP according to an embodiment of the present disclosure (refer to Figure 1 ) area. Fig. 20 is with Figure 4A The parts correspond to the plan views of the parts. Fig. 20 shows the display area DAf and Figure 4A For ease of explanation, Fig. 20 Only the display panel DP (refer to Figure 1 ) includes the spacer SPR, the spacer SPC_f, the light emitting parts EP1, EP2 and EP3, and the light emitting connection parts CE1, CE2 and CE3.

[0330] refer to Fig. 20 , the spacer SPC_f may include a second spacer SPC2_f and a third spacer SPC3_f.

[0331] The second spacer SPC2_f may be disposed to overlap one of the first line L1 -S and the second line L2 -S. Fig. 20A structure in which a plurality of second spacers SPC2_f may be disposed to overlap only the first line L1-S is shown as a representative example, however, the second spacer SPC2_f may overlap only the second line L2-S. According to an embodiment, some of the second spacers SPC2_f may overlap the first line L1-S, and other second spacers SPC2_f may overlap the second line L2-S. In addition, the number and position of the second spacers SPC2_f should not be limited to Fig. 20 Embodiment of the invention.

[0332] The third spacer SPC3_f may overlap the bent portion BP of the spacer SPR. Fig. 20 Only one third spacer SPC3_f is shown, however, the number and position of the third spacer SPC3_f should not be limited to Fig. 20 The embodiment shown in .

[0333] Fig. 20 A structure in which a portion of each of the spacers SPC_f may be exposed in a plan view without being covered by the spacer SPR is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. Figure 8 As shown in , the entire area of ​​each of the spacers SPC_f may overlap with the spacer SPR in a plan view.

[0334] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present disclosure as claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present invention should be determined according to the claims.

Claims

1. A display device, comprising: A plurality of light emitting devices, each comprising a first electrode, a second electrode, and an intermediate layer disposed between the first electrode and the second electrode and comprising a light emitting layer; a pixel defining layer comprising a plurality of light emitting openings, each of the plurality of light emitting openings overlapping the light emitting layer of a corresponding one of the plurality of light emitting devices; a partition disposed on the pixel defining layer and comprising a plurality of partition openings, each of the plurality of partition openings overlapping a corresponding one of the plurality of light emitting openings; as well as At least one spacer is disposed on the pixel defining layer, wherein The second electrode of each of the plurality of light emitting devices overlaps with a corresponding one of the plurality of partition openings, and the plurality of light emitting devices are electrically separated from each other by the partition.

2. The display device according to claim 1, wherein In a plan view, the at least one spacer overlaps a portion of the spacer, or the at least one spacer is disposed between the pixel defining layer and the spacer, In the plan view, the entire area of ​​the at least one spacer overlaps with the partition, or in the plan view, the at least one spacer is partially exposed and not covered by the partition, or The spacer includes a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface and having a width greater than a width of the lower surface in a cross-sectional view, and in the cross-sectional view, at least one spacer has a width equal to or greater than the width of the lower surface of the spacer.

3. The display device according to claim 1, wherein The at least one spacer is disposed between the pixel defining layer and the spacer, The spacer includes a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface, and A distance between the pixel defining layer and a portion of the upper surface of the spacer overlapping the at least one spacer is greater than a distance between the pixel defining layer and a portion of the upper surface of the spacer not overlapping the at least one spacer.

4. The display device according to claim 1, wherein The at least one spacer is disposed on the partition, In plan view, the entire area of ​​the at least one spacer overlaps with the partition, The spacer includes a lower surface adjacent to the pixel defining layer and an upper surface opposite to the lower surface, the upper surface having a width greater than a width of the lower surface in a cross-sectional view, and In the cross-sectional view, the at least one spacer has a width equal to or smaller than the width of the upper surface of the spacer.

5. The display device according to claim 1, wherein The partition member includes partition grid lines defining the plurality of partition openings, the partition grid lines including a plurality of first lines extending in a first direction and a plurality of second lines extending in a second direction, The separator includes a plurality of intersections, and the plurality of first lines intersect with the plurality of second lines at the plurality of intersections, The at least one spacer overlaps one of the plurality of intersections, and / or The plurality of intersecting portions include: at least one first intersection portion having a cross shape in plan view; as well as At least one second intersection portion has a T-shape in the plan view.

6. The display device according to claim 5, wherein said at least one spacer overlaps said at least one first intersection portion, In the plan view, the at least one spacer has a quadrilateral shape or a cross shape, and / or The at least one first intersection portion comprises: first intersection area; A first-first line region and a first-second line region of each of the plurality of first lines extend from the first intersection region in directions opposite to each other in the first direction; The second-first line region and the second-second line region of each of the plurality of second lines extend from the first intersection region in directions opposite to each other in the second direction; and A first protruding area protrudes from corresponding line areas adjacent to each other among the first-first line area, the first-second line area, the second-first line area and the second-second line area, wherein the at least one spacer overlaps with at least a portion of each of the first intersection area, the first-first line area and the first-second line area, the second-first line area and the second-second line area and the first protruding area.

7. The display device according to claim 5, wherein said at least one spacer overlaps said at least one second intersection portion, In the plan view, the at least one spacer has a quadrilateral shape, a T shape or a triangular shape, and / or The at least one second intersection portion comprises: The second intersection area; a first to third line region of each of the plurality of first lines extending from the second intersection region in the first direction; The second-third line region and the second-fourth line region of each of the plurality of second lines extend from the second intersection region in directions opposite to each other in the second direction; as well as a second protruding area protruding from corresponding line areas adjacent to each other among the first-third line areas, the second-third line areas, and the second-fourth line areas, and The at least one spacer overlaps at least a portion of each of the second intersection region, the first-third line region, the second-third line region, the second-fourth line region, and the second protrusion region.

8. The display device according to claim 5, wherein The at least one first intersection portion comprises a plurality of first intersection portions, the at least one second intersection portion comprises a plurality of second intersection portions, The at least one spacer comprises a plurality of spacers, and Each of the plurality of first intersection portions and the plurality of second intersection portions overlaps with a corresponding one of the plurality of spacers, or Some of the first intersecting portions among the plurality of first intersecting portions and some of the second intersecting portions among the plurality of second intersecting portions respectively overlap with corresponding spacers among the plurality of spacers, and other first intersecting portions among the plurality of first intersecting portions and other second intersecting portions among the plurality of second intersecting portions do not overlap with any spacers among the plurality of spacers.

9. The display device according to claim 5, wherein The at least one spacer comprises a plurality of spacers, The plurality of spacers include a first spacer and a second spacer, the first spacer overlaps one of the plurality of intersections, and the second spacer is spaced apart from each of the plurality of intersections and overlaps one of the plurality of first lines and the plurality of second lines, or Each of the plurality of spacers is spaced apart from each of the plurality of intersection portions and overlaps one of the plurality of first lines and the plurality of second lines.

10. The display device according to claim 5, wherein The separator further comprises a bent portion, The bending portion comprises: Bending zone; The first to fourth line regions of each of the plurality of first lines extend from the bending region in the first direction; and a second to fifth line region of each of the plurality of second lines extending from the bending region in the second direction, In the plan view, the at least one spacer overlaps the bent portion, The at least one spacer overlapping the bent portion has an L-shape, The at least one spacer comprises a plurality of spacers, The plurality of spacers include a first spacer and a second spacer, and The first spacer overlaps with one of the multiple intersecting portions and the second spacer is spaced apart from each of the multiple intersecting portions and overlaps with the bending portion, or the first spacer is spaced apart from the multiple intersecting portions and overlaps with one of the multiple first lines and the multiple second lines and the second spacer is spaced apart from the multiple intersecting portions and overlaps with the bending portion.

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