Display substrate and display panel

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a first metal layer, a first insulating layer and a second metal layer which are sequentially laminated, wherein the first metal layer comprises a plurality of grid lines extending along a first direction; the second metal layer comprises a plurality of data lines and a plurality of metal wires which extend along a second direction, and the second direction is intersected with the first direction; the insulating material layer is located on the side, away from the first substrate, of the second metal layer, the insulating material layer comprises a color resistance layer, and the orthographic projection, on the first substrate, of at least one part of the data lines and / or the metal wires is located in the orthographic projection, on the first substrate, of the color resistance layer; the first transparent electrode layer is located on the side, away from the first substrate, of the insulating material layer and comprises a plurality of touch electrode blocks, and the touch electrode blocks are connected with the corresponding metal wires. According to the technical scheme, stray capacitance between the metal wires and the touch electrode blocks can be reduced, and the touch performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] TDDI (Touch and Display Driver Integration) technology integrates touch sensing and display driving functions into a single chip. In TDDI technology, touch sensing generally adopts self-capacitance mode. Therefore, the stability of the self-capacitance of the touch electrode block determines the quality of the touch performance.

[0003] In large-size TDDI products, the increase in size causes distortion of touch signals, which reduces the touch performance of large-size products. Utility Model Content

[0004] Embodiments of the present disclosure provide a display substrate and a display panel to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display substrate, including:

[0006] a first substrate;

[0007] A first metal layer, located on one side of the first substrate, includes a plurality of gate lines extending along a first direction;

[0008] A first insulating layer, located on a side of the first metal layer away from the first substrate;

[0009] A second metal layer is located on a side of the first insulating layer away from the first substrate, and includes a plurality of data lines and a plurality of metal traces extending along a second direction, wherein the plurality of data lines and the plurality of gate lines intersect with each other to define a plurality of sub-pixel regions arranged in an array, and the second direction intersects with the first direction;

[0010] an insulating material layer, located on a side of the second metal layer away from the first substrate, the insulating material layer comprising a color resist layer, and an orthographic projection of at least a portion of the data line and / or the metal routing on the first substrate is located within an orthographic projection of the color resist layer on the first substrate;

[0011] The first transparent electrode layer is located on a side of the insulating material layer away from the first substrate, and includes a plurality of touch electrode blocks, and the touch electrode blocks are connected to corresponding metal wirings.

[0012] In some embodiments, the metal routing extends along the second direction within a column of sub-pixel regions, the color resist layer includes a color film located in the sub-pixel region, and the orthographic projection of the portion of the metal routing located in the sub-pixel region on the first substrate is within the orthographic projection of the color film on the first substrate.

[0013] In some embodiments, multiple metal routings are arranged one-to-one in multiple columns of sub-pixel areas, the touch electrode block includes multiple sub-electrode blocks arranged in an array, the sub-electrode block is located between two adjacent gate lines and between two adjacent metal routings, and the orthographic projection of the metal routing on the first substrate does not overlap with the orthographic projection of the sub-electrode block on the first substrate.

[0014] In some embodiments, the orthographic projection of the gate line on the first substrate does not overlap with the orthographic projection of the sub-electrode block on the first substrate, and adjacent sub-electrode blocks in the touch electrode block are connected via a connecting bridge.

[0015] In some embodiments, the color resist layer includes a first color film and a second color film located in two adjacent sub-pixel areas in a first direction. In the first direction, a portion of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the first color film on the first substrate, and another portion of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second color film on the first substrate.

[0016] In some embodiments, in the first direction, half of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the first color filter on the first substrate, and the other half of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second color filter on the first substrate.

[0017] In some embodiments, a thin film transistor is further included between two adjacent sub-pixel regions in the second direction, the thin film transistor includes an active layer, and an orthographic projection of the active layer on the first substrate is within an orthographic projection of the color resist layer on the first substrate.

[0018] In some embodiments, it also includes a second insulating layer and a second transparent electrode layer stacked in sequence on a side of the first transparent electrode layer away from the first substrate, the second transparent electrode layer includes a pixel electrode located in the sub-pixel area, and the second metal layer also includes a connecting wire;

[0019] The display substrate further includes a thin film transistor located between two adjacent sub-pixel regions in the second direction, the second metal layer further includes a first electrode and a second electrode of the thin film transistor, the first electrode is connected to the corresponding data line, and the connecting line is connected to the second electrode;

[0020] The second insulating layer is provided with a first via hole, and the first via hole is located between two adjacent sub-pixel areas in the second direction. The pixel electrode is connected to the connecting wiring through the first via hole. The orthographic projection of the first via hole on the first substrate does not overlap with the orthographic projection of the color resist layer on the first substrate. The orthographic projection of the first via hole on the first substrate does not overlap with the orthographic projection of the first transparent electrode layer on the first substrate.

[0021] In some embodiments, the insulating material layer further includes a third insulating layer and a planarization layer, the third insulating layer is located between the second metal layer and the color resist layer, and the planarization layer is located between the color resist layer and the first transparent electrode layer.

[0022] In some embodiments, it also includes a second insulating layer and a second transparent electrode layer stacked in sequence on a side of the first transparent electrode layer facing away from the first substrate. The display substrate also includes a second via hole, the second via hole is located between two adjacent sub-pixel areas in the second direction, the orthographic projection of the second via hole on the first substrate and the orthographic projection of the color resist layer on the first substrate do not overlap, the second transparent electrode layer includes a first adapter wire, the first adapter wire is connected to the touch electrode block through the second via hole, and is connected to the corresponding metal trace through the second via hole.

[0023] In some embodiments, the display substrate is applied to a display panel, a common voltage signal is input to the touch electrode block when the display panel displays a frame image, and a touch driving signal is input to the touch electrode block between two frame images of the display panel.

[0024] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display panel, including the display substrate of the present disclosure, and also including an opposing substrate, the opposing substrate is located on the side of the display substrate away from the first substrate, and the display panel also includes a liquid crystal located between the display substrate and the opposing substrate.

[0025] In some embodiments, the opposing substrate includes a second substrate and a light-shielding layer disposed on the second substrate, the light-shielding layer includes a plurality of first light-shielding strips extending along a first direction and a plurality of second light-shielding strips extending along a second direction, the orthographic projection of the gate line on the first substrate is located within the orthographic projection of the first light-shielding strip on the first substrate, the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second light-shielding strip on the first substrate, and the orthographic projection of the first via hole and the second via hole of the display substrate on the first substrate is located within the orthographic projection of the first light-shielding strip on the first substrate.

[0026] The display substrate of the disclosed embodiment has a color resist layer disposed on the display substrate, and the color resist layer is located between the first metal layer and the first transparent electrode layer, and between the second metal layer and the first transparent electrode layer. The arrangement of the color resist layer increases the distance between the first metal layer and the first transparent electrode layer, and increases the distance between the second metal layer and the first transparent electrode layer, thereby reducing the parasitic capacitance between the gate line and the touch electrode block, reducing the parasitic capacitance between the data line and the touch electrode block, and reducing the parasitic capacitance between the metal routing and the touch electrode block, thereby improving the effect of the increase in product size on the self-capacitance of the touch electrode block, and improving the touch performance of the touch electrode block as a touch electrode. In addition, the reduction in parasitic capacitance reduces the load within the display substrate surface, thereby reducing the power consumption of the product.

[0027] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0029] Figure 1 It is a partial plan view of a display substrate in one embodiment of the present disclosure;

[0030] Figure 2 for Figure 1 A plan view of the first transparent electrode layer in FIG.

[0031] Figure 3 for Figure 1 AA section diagram in;

[0032] Figure 4 for Figure 1 BB cross-section diagram in;

[0033] Figure 5 for Figure 1 Schematic diagram of CC cross section;

[0034] Figure 6 for Figure 1 DD cross-section diagram in;

[0035] Figure 7 Another cross-sectional schematic diagram of an opposing substrate in a display panel according to an embodiment of the present disclosure.

[0036] Description of reference numerals:

[0037] 11. first substrate; 12. first metal layer; 121. gate line; 122. gate; 13. first insulating layer; 14. active layer; 15. second metal layer; 151. data line; 152. metal wiring; 153. first electrode; 154. connecting wiring; 16. third insulating layer; 17. color resist layer; 171. color filter; 172. shielding part; 18. planarization layer; 19. third insulating layer;

[0038] 21. first transparent electrode layer; 211. sub-electrode block; 212. connection bridge; 22. second transparent electrode layer; 221. pixel electrode; 222. second transfer line; 223. first transfer line. DETAILED DESCRIPTION

[0039] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined arbitrarily without conflict. Therefore, the drawings and descriptions are considered to be illustrative in nature and not restrictive.

[0040] In TDDI technology, the common electrode of the display substrate is usually shared with the touch electrode, that is, multiple touch electrode blocks are set, each touch electrode block is connected to a metal trace separately, and the metal trace connected to the touch electrode block can be called a touch signal line. In the display stage, a common voltage signal Vcom is input to the touch electrode block, so that the touch electrode block is used as a common electrode; in the touch detection stage, a touch drive signal is input to the touch electrode block, so that the touch electrode block is used as a touch electrode.

[0041] In large-size TDDI products, the increase in size leads to an increase in the length of signal lines such as touch signal lines, data lines, and gate lines, which in turn increases the load on each signal line, causing distortion of the touch signal and reducing the touch performance of large-size products.

[0042] In order to improve the touch performance in TDDI products, an embodiment of the present disclosure provides a display substrate.

[0043] Figure 1 is a partial plan view of a display substrate in one embodiment of the present disclosure. Figure 2 for Figure 1 A schematic plan view of the first transparent electrode layer in FIG. Figure 2 The first transparent electrode layer, gate lines, data lines and metal wiring are shown; Figure 3 for Figure 1 AA cross-section diagram in Figure 2, Figure 4 for Figure 1 BB cross-section diagram in Figure 5 for Figure 1 Schematic diagram of CC section, Figure 6 for Figure 1 DD cross-section diagram in Fig. Figure 1-Figure 4 As shown, the display substrate of the embodiment of the present disclosure includes a first substrate 11 , a first metal layer 12 , a first insulating layer 13 , a second metal layer 15 , an insulating material layer and a first transparent electrode layer 21 .

[0044] Among them, the first metal layer 12 is located on one side of the first substrate 11, and the first metal layer 12 includes a plurality of gate lines 121 extending along the first direction X. The first insulating layer 13 is located on the side of the first metal layer 12 away from the first substrate 11. The second metal layer 15 is located on the side of the first insulating layer 13 away from the first substrate 11. The second metal layer 15 includes a plurality of data lines 151 and a plurality of metal traces 152. The data lines 151 extend along the second direction Y. The metal traces 152 extend along the second direction Y. The second direction Y intersects with the first direction X, so that the plurality of data lines 151 and the plurality of gate lines 121 intersect with each other to define a plurality of sub-pixel areas arranged in an array. Exemplarily, the second direction Y can be perpendicular to the first direction X.

[0045] It should be noted that, in this article, object A extends along a certain direction, which should be understood as object A generally tends to extend along a certain direction. For example, the data line 151 and the metal routing 152 extend along the second direction Y, which should be understood as the data line 151 and the metal routing 152 generally tend to extend along the second direction Y.

[0046] The insulating material layer is located on the side of the second metal layer 15 away from the first substrate 11, and the insulating material layer includes a color resist layer 17. The orthographic projection of at least a portion of the data line 151 and / or the metal wiring 152 on the first substrate 11 is located within the orthographic projection of the color resist layer 17 on the first substrate 11, that is, the orthographic projection of at least a portion of the data line 151 on the first substrate 11 is located within the orthographic projection of the color resist layer 17 on the first substrate 11; and / or, the orthographic projection of at least a portion of the metal wiring 152 on the first substrate 11 is located within the orthographic projection of the color resist layer 17 on the first substrate 11.

[0047] It should be noted that at least a portion of a data line can be understood as at least a portion of at least one data line; and at least a portion of a metal trace can be understood as at least a portion of at least one metal trace.

[0048] The first transparent electrode layer 21 is located on a side of the insulating material layer away from the first substrate 11 . The first transparent electrode layer 21 includes a plurality of touch electrode blocks, and the touch electrode blocks are connected to corresponding metal traces 152 .

[0049] In TDDI-related products, the color resist layer 17 is located on the opposing substrate 30. As the product size increases, the length of signal lines such as the touch signal line, the gate line 121, and the data line 151 in the display substrate increases, which in turn causes the parasitic capacitance between the touch electrode block and the signal line to increase, affecting the self-capacitance of the touch electrode block, thereby reducing the touch performance.

[0050] The display substrate of the embodiment of the present disclosure has a color resist layer 17 disposed on the display substrate, and the color resist layer 17 is located between the first metal layer 12 and the first transparent electrode layer 21, and between the second metal layer 15 and the first transparent electrode layer 21. The arrangement of the color resist layer 17 increases the distance between the first metal layer 12 and the first transparent electrode layer 21, and increases the distance between the second metal layer 15 and the first transparent electrode layer 21, thereby reducing the parasitic capacitance between the gate line 121 and the touch electrode block, reducing the parasitic capacitance between the data line 151 and the touch electrode block, and reducing the parasitic capacitance between the metal wiring 152 and the touch electrode block, thereby improving the effect of the increase in product size on the self-capacitance of the touch electrode block, and improving the touch performance of the touch electrode block as a touch electrode. In addition, the reduction of parasitic capacitance reduces the load within the display substrate surface, thereby reducing the power consumption of the product.

[0051] For example, among the multiple metal traces 152, the metal traces 152 connected to the touch electrode block and used to transmit touch signals can be called touch signal lines, and some of the metal traces 152 can be used as touch signal lines, which are connected between the touch electrode block and the control module; and the metal traces 152 not used to transmit touch signals among the multiple metal traces 152 can be called auxiliary connection lines. The touch electrode block can be connected to the auxiliary connection lines, and the auxiliary connection lines made of metal materials have lower resistance, which can reduce the resistance of the touch electrode block, thereby improving the touch performance or display performance.

[0052] like Figure 1 and Figure 3 As shown, a plurality of sub-pixel regions are arranged in an array, and a metal trace 152 extends in a column of sub-pixel regions along the second direction Y. The color resist layer 17 includes a color filter 171 located in the sub-pixel region, and the color filter 171 may include different color filters 171 differentiated by color. The orthographic projection of the portion of the metal trace 152 located in the sub-pixel region on the first substrate 11 is located within the orthographic projection of the color filter 171 on the first substrate 11.

[0053] In this arrangement, the metal wiring 152 is no longer arranged between two adjacent sub-pixel regions, thereby reserving a wider arrangement space for the data line 151, which is conducive to the arrangement of a wider data line 151 and improves data transmission performance. In addition, the orthographic projection of the portion of the metal wiring 152 located in the sub-pixel region on the first substrate 11 is located within the orthographic projection of the color filter 171 on the first substrate 11, so that more portions of the metal wiring 152 can be located below the color filter 171, thereby minimizing the parasitic capacitance between the metal wiring 152 and the touch electrode block, reducing the influence of the metal wiring 152 on the self-capacitance of the touch electrode block, and further improving the touch performance of the touch electrode block.

[0054] For example, each sub-pixel region may be provided with a color filter 171. In the first direction X, the colors of the color filters 171 corresponding to two adjacent sub-pixel regions may be different, and in the second direction Y, the colors of the color filters 171 corresponding to the sub-pixel regions in the same column may be the same.

[0055] Here, it is not limited to which sub-pixel region the metal wiring 152 is specifically arranged, and the metal wiring 152 is arranged in at least one of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region adjacent to each other in the first direction X. For example, Figure 1 As shown, the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region may all be provided with a metal trace 152 extending along the second direction Y.

[0056] The length of each metal trace 152 is not specifically limited, and the extension length of the metal trace 152 can be set as needed. Figure 1 In the embodiment, the touch signal line can extend to the lower frame area of ​​the display substrate to be connected to the corresponding control module; the auxiliary connection line can extend along the second direction Y within the area defined by the corresponding touch electrode block.

[0057] In one embodiment, the plurality of metal traces 152 are disposed in a one-to-one correspondence in the plurality of columns of sub-pixel regions. Figure 1 to Figure 3 As shown, the touch electrode block may include a plurality of sub-electrode blocks 211 arranged in an array. The number of sub-electrode blocks in the touch electrode block may be set as required. The sub-electrode block 211 is located between two adjacent gate lines 121 and between two adjacent metal traces 152. The orthographic projection of the metal trace 152 on the first substrate 11 does not overlap with the orthographic projection of the sub-electrode block 211 on the first substrate 11. Figure 2 and Figure 3 It can be seen from FIG. 1 that the metal wiring 152 is located between two adjacent sub-electrode blocks 211 in the first direction X.

[0058] This arrangement can ensure that the metal trace 152 does not overlap with the touch electrode block, avoid parasitic capacitance between the touch electrode block and the metal trace 152, and avoid the influence of the metal trace 152 on the self-capacitance of the touch electrode block, thereby further improving the touch performance of the touch electrode block.

[0059] like Figure 1 and Figure 2 As shown, the orthographic projection of the gate line 121 on the first substrate 11 does not overlap with the orthographic projection of the sub-electrode block 211 on the first substrate 11. In this way, the gate line 121 and the touch electrode block do not overlap, thereby avoiding parasitic capacitance between the touch electrode block and the gate line 121, avoiding the influence of the gate line 121 on the self-capacitance of the touch electrode block, and further improving the touch performance of the touch electrode block.

[0060] Adjacent sub-electrode blocks 211 in the touch electrode block are connected by a connecting bridge 212. Exemplarily, the connecting bridge 212 may be located in the first transparent electrode layer 21. In this way, multiple sub-electrode blocks 211 in the touch electrode block are connected to each other, and the touch electrode blocks are connected as an integrated structure, which is conducive to improving the touch performance. Exemplarily, the shape of the connecting bridge 212 may be a "[" shape, so that four adjacent sub-electrode blocks 211 in the upper, lower, left, and right directions may be connected as a whole through the connecting bridge 212.

[0061] Exemplarily, the orthographic projection of the connection bridge 212 on the first substrate 11 does not overlap with the orthographic projection of the data line 151 on the first substrate 11, so that parasitic capacitance can be avoided between the data line 151 and the connection bridge 212, thereby preventing the data signal from affecting the touch performance.

[0062] In one embodiment, Figure 1 and Figure 4 As shown, the color resist layer 17 includes a first color film 171 and a second color film 171 located in two adjacent sub-pixel regions in the first direction X, that is, the color films 171 disposed in two adjacent sub-pixel regions in the first direction X can be respectively called the first color film 171 and the second color film 171. In the first direction X, a part of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the first color film 171 on the first substrate 11, and another part of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the second color film 171 on the first substrate 11. Thus, in the first direction X, the data line 151 is located between two adjacent sub-pixel regions, and the orthographic projection of the data line 151 on the first substrate 11 is entirely located within the color resist layer 17, which can further reduce the influence of the signal on the data line 151 on the touch electrode block, thereby improving the touch performance.

[0063] It should be noted that the first color filter and the second color filter are not specifically limited to a color filter 171 of a certain color. Figure 1 In the figure, for the data line 151a, the first color film and the second color film are respectively two color films 171a and 171b located on both sides of the data line 151a in the first direction X; for the data line 151b, the first color film and the second color film are respectively two color films 171b and 171c located on both sides of the data line 151b in the first direction X.

[0064] For example, Figure 1 As shown, a data line 151 is arranged between every two adjacent color filters 171 in the first direction X, a part of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of one of the color filters 171 on the first substrate 11, and another part of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the other color filter 171 on the first substrate 11.

[0065] Exemplarily, in the first direction X, one half of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the first color filter 171 on the first substrate 11, and the other half of the orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the second color filter 171 on the first substrate 11. Thus, the data line 151 is located in the middle of two adjacent sub-pixels, ensuring the uniformity of the sub-pixel performance on both sides of the data line 151.

[0066] In other embodiments, the proportions of the orthographic projection of the data line 151 on the first substrate 11 in the first color filter and the second color filter can be set as needed and are not limited to one half.

[0067] like Figure 1 and Figure 5 As shown, the display substrate further includes a thin film transistor, which is located between two adjacent sub-pixel regions in the second direction Y. The thin film transistor includes an active layer, and the orthographic projection of the active layer on the first substrate 11 is located within the orthographic projection of the color resist layer 17 on the first substrate 11. Exemplarily, the color resist layer 17 may further include a shielding portion located between two adjacent color filters 171 in the second direction Y, and the orthographic projection of the active layer on the first substrate 11 may be located within the orthographic projection of the shielding portion on the first substrate 11.

[0068] It should be noted that, in the process of preparing the color-resist layer 17 , the color filters 171 of the same color are prepared by the same patterning process, and the shielding portion is prepared together with the color filters 171 of the corresponding column.

[0069] The light on the upper side of the display substrate may irradiate the active layer of the thin film transistor, causing negative drift of the thin film transistor and affecting the performance of the thin film transistor. By locating the positive projection of the active layer on the first substrate 11 within the positive projection of the color resist layer 17 on the first substrate 11, the color resist layer 17 can shield the active layer to prevent the light on the upper side of the display substrate from irradiating the active layer, thereby improving the negative drift characteristics of the thin film transistor and improving the performance of the thin film transistor.

[0070] like Figure 1 and Figure 5 As shown, the display substrate may further include a second insulating layer 19 and a second transparent electrode layer 22 stacked in sequence on a side of the first transparent electrode layer 21 away from the first substrate 11. The second transparent electrode layer 22 includes a pixel electrode 221 located in a sub-pixel region.

[0071] The second metal layer 15 further includes a first electrode 153 and a second electrode of the thin film transistor, and the first electrode 153 is connected to the corresponding data line 151. The second metal layer 15 further includes a connecting wire 154, and the connecting wire 154 is located between two adjacent sub-pixel regions in the second direction Y. The connecting wire 154 is connected to the second electrode. One of the first electrode 153 and the second electrode can be a source electrode of the thin film transistor, and the other can be a drain electrode of the thin film transistor.

[0072] The second insulating layer 19 is provided with a first via hole K1. The first via hole K1 is located between two adjacent sub-pixel regions in the second direction Y, and the pixel electrode 221 is connected to the connecting wire 154 through the first via hole K1. For example, the second transparent electrode layer 22 may further include a second adapter line 222, the second adapter line 222 is connected to the pixel electrode 221, and the second adapter line 222 is connected to the connecting wire 154 through the first via hole K1. The orthographic projection of the first via hole K1 on the first substrate 11 does not overlap with the orthographic projection of the color resist layer 17 on the first substrate 11, and the orthographic projection of the first via hole K1 on the first substrate 11 does not overlap with the orthographic projection of the first transparent electrode layer 21 on the first substrate 11.

[0073] The first via K1 is arranged between two adjacent sub-pixel regions, and the orthographic projection of the first via K1 on the first substrate 11 does not overlap with the orthographic projection of the color resist layer 17 on the first substrate 11, thereby preventing the first via K1 from affecting the display of the sub-pixel; the connecting wire 154 and the first via K1 are both arranged between two adjacent sub-pixel regions, and the orthographic projection of the first via K1 on the first substrate 11 does not overlap with the orthographic projection of the first transparent electrode layer 21 on the first substrate 11, thereby achieving that the connecting wire 154 and the first via K1 do not overlap with the sub-electrode block 211, thereby avoiding the influence of the connecting wire 154 and the first via K1 on the touch electrode block, and further improving the touch performance.

[0074] exist Figure 5 In the embodiment, the second transparent electrode layer is located on a side of the first transparent electrode layer away from the first substrate. In other embodiments, the second transparent electrode layer may also be located on a side of the first transparent electrode layer close to the first substrate, for example, the second transparent electrode layer and the second insulating layer are sequentially stacked between the planarization layer and the first transparent electrode layer.

[0075] Exemplarily, the sub-electrode block 211 is a planar electrode, and the pixel electrode 221 includes a plurality of electrode strips spaced apart in the sub-pixel region. In the first direction X, the orthographic projection of the metal trace 152 on the first substrate 11 does not overlap with the orthographic projection of the pixel electrode 221 on the first substrate 11. Figure 3 As shown, this can prevent parasitic capacitance from being formed between the metal line and the pixel electrode 221, avoid the signal on the metal line from affecting the signal on the pixel electrode 221, and improve the display performance.

[0076] For example, Figure 5 As shown, the insulating material layer may further include a third insulating layer 16 and a planarization layer 19 , and the first via hole K1 penetrates the second insulating layer 19 and also penetrates the planarization layer 19 and the third insulating layer 16 .

[0077] like Figure 3 to Figure 5 As shown, the third insulating layer 16 may be located between the second metal layer 15 and the color resist layer 17, and the planarization layer 19 may be located between the color resist layer 17 and the first transparent electrode layer 21. That is, in the insulating material layer, the third insulating layer 16, the color resist layer 17 and the planarization layer 19 are stacked in sequence, and the first transparent electrode layer 21 is located on the side of the planarization layer 19 away from the first substrate 11.

[0078] In another embodiment, the third insulating layer 16 and the planarization layer 19 are stacked, and the planarization layer 19 is close to the first transparent electrode layer 21. The position of the color resist layer 17 in the insulating material layer can be set as needed, for example, the color resist layer 17 can be set between the second metal layer 15 and the third insulating layer 16, or the color resist layer 17 can be set between the planarization layer 19 and the first transparent electrode layer 21.

[0079] like Figure 1 and Figure 6 As shown, the display substrate may further include a second via hole K2, and the second via hole K2 is located between two adjacent sub-pixel regions in the second direction Y. The orthographic projection of the second via hole K2 on the first substrate 11 does not overlap with the orthographic projection of the color resist layer 17 on the first substrate 11. The second transparent electrode layer 22 includes a first adapter line 223, and the first adapter line 223 is connected to the touch electrode block through the second via hole K2, and is connected to the corresponding metal trace 152 through the second via hole K2.

[0080] like Figure 6 As shown, the second via K2 may include a first part and a second part, the first part penetrates the second insulating layer 19 and exposes a part of the connecting bridge 212. The second part penetrates the second insulating layer 19, the planarizing layer 19 and the third insulating layer 16 and exposes a part of the metal trace 152. The first adapter line 223 is connected to the connecting bridge 212 through the first part, and then connected to the sub-electrode block 211 and the touch electrode block; the first adapter line 223 is connected to the metal trace 152 through the second part, so that the touch electrode block is connected to the metal trace 152 through the first adapter line 223. Thus, a touch signal or a common voltage signal can be provided to the touch electrode block through the touch signal line. In this connection mode, when the orthographic projection of the metal trace 152 on the first substrate 11 does not overlap with the orthographic projection of the sub-electrode block 211 on the first substrate 11, the connection between the metal trace 152 and the sub-electrode block 211 is realized.

[0081] In one embodiment, Figure 1 and Figure 2 As shown, a portion of the orthographic projection of the connection bridge 212 on the first substrate 11 overlaps with the orthographic projection of the metal trace 152 on the first substrate 11, so that the connection bridge 212 can be connected to the metal trace 152 through the via hole penetrating the planarization layer 19 and the third insulating layer 16. In another embodiment, the orthographic projection of the portion of the connection bridge 212 extending along the Y direction on the first substrate 11 does not overlap with the orthographic projection of the metal trace 152 on the first substrate 11, which can reduce parasitic capacitance.

[0082] The display substrate of the embodiment of the present disclosure can be applied to a display panel. A common voltage signal is input to the touch electrode block during the process of displaying a frame image on the display panel, and a touch drive signal is input to the touch electrode block between two frame images of the display panel. Thus, the common voltage signal and the touch drive signal share the touch electrode block, realizing a display panel with touch and display driver integration (TDDI) technology.

[0083] The present disclosure also provides a display panel. Figure 4 and Figure 5 As shown, the display panel includes the display substrate in the embodiment of the present disclosure, and also includes an opposing substrate 30. The opposing substrate 30 is located on the side of the display substrate away from the first substrate 11. The display panel may also include liquid crystal located between the display substrate and the opposing substrate 30. Therefore, the display panel is a liquid crystal display panel.

[0084] like Figure 1 , Figure 4 and Figure 5 As shown, the counter substrate 30 includes a second substrate 31 and a light shielding layer 32 disposed on the second substrate 31. The light shielding layer 32 includes a plurality of first light shielding strips 321 extending along a first direction X and a plurality of second light shielding strips 322 extending along a second direction Y. The orthographic projection of the gate line 121 on the first substrate 11 is located within the orthographic projection of the first light shielding strip 321 on the first substrate 11. The orthographic projection of the data line 151 on the first substrate 11 is located within the orthographic projection of the second light shielding strip 322 on the first substrate 11. The orthographic projections of the first via hole K1 and the second via hole K2 of the display substrate on the first substrate 11 are located within the orthographic projection of the first light shielding strip 321 on the first substrate 11.

[0085] Disposing the orthographic projections of the first via hole K1 and the second via hole K2 on the first substrate 11 within the orthographic projections of the first light shielding strip 321 on the first substrate 11 can prevent light leakage at the first via hole K1 and the second via hole K2 and improve the performance of the display panel.

[0086] Figure 7 FIG. 2 is another cross-sectional schematic diagram of an opposing substrate in a display panel according to an embodiment of the present disclosure. Figure 7 As shown, the counter substrate 30 may further include an outer coating layer 33 located on the side of the light shielding layer 32 away from the second substrate 31, and the surface of the outer coating layer 33 on the side away from the second substrate 31 is a flat surface. The counter substrate 30 may further include a support column 34, which is disposed on the side of the outer coating layer 33 away from the second substrate 31, and one end of the support column 34 away from the second substrate 31 is used to abut against the display substrate, so that a preset box thickness is maintained between the display substrate and the counter substrate 30.

[0087] Reference below Figure 1-Figure 6 The preparation process of the display substrate in one embodiment of the present disclosure is described to further illustrate the technical solution of the embodiment of the present disclosure. It can be understood that the "patterning" mentioned herein includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant technology.

[0088] A first metal layer 12 is formed on one side of the first substrate 11 , and the first metal layer 12 includes a gate line 121 and a gate of a thin film transistor.

[0089] A first insulating layer 13 is formed on a side of the first metal layer 12 facing away from the first substrate 11 .

[0090] An active layer of a thin film transistor is formed on a side of the first insulating layer 13 away from the first substrate 11 , and the active layer is located between two adjacent sub-pixel regions in the second direction Y. The orthographic projection of the active layer on the first substrate 11 may be located within the orthographic projection of the gate on the first substrate 11 .

[0091] A second metal layer 15 is formed on a side of the first insulating layer 13 facing away from the first substrate 11 . The second metal layer 15 may include a data line 151 , a metal wiring 152 , a source and a drain of a thin film transistor, and a connecting wiring 154 .

[0092] A third insulating layer 16 is formed on a side of the second metal layer 15 facing away from the first substrate 11 .

[0093] A color resist layer 17 is formed on the side of the third insulating layer 16 facing away from the first substrate 11. The color resist layer 17 may include a red color filter 171, a green color filter 171, and a blue color filter 171. The three color filters 171 are formed respectively by three patterning processes. The color resist layer 17 may also include a shielding portion, which is located between two adjacent color filters 171 in the second direction Y and is an integral structure with the two color filters 171.

[0094] A planarization layer 19 is formed on the side of the color resist layer 17 away from the first substrate 11; the planarization layer 19 and the third insulating layer 16 are patterned to form a third via K3 and a fourth via K4, and the third via K3 and the fourth via K4 are both located between two adjacent sub-pixel regions in the second direction Y. The orthographic projection of the first via K1 on the first substrate 11 is located within the orthographic projection of the third via K3 on the first substrate 11, and the orthographic projection of the fourth via K4 on the first substrate 11 is located within the orthographic projection of the second via K2 on the first substrate 11. The orthographic projections of the third via K3 and the fourth via K4 on the first substrate 11 do not overlap with the orthographic projection of the color resist layer 17 on the first substrate 11. The material of the planarization layer 19 may be an organic material.

[0095] A first transparent electrode layer 21 is formed on the side of the planarization layer 19 facing away from the first substrate 11 . The first transparent electrode layer 21 includes a plurality of sub-electrode blocks 211 and connecting bridges 212 . The sub-electrode blocks 211 are located between two adjacent gate lines 121 and between two adjacent metal traces 152 .

[0096] A second insulating layer 19 is formed on a side of the first transparent electrode layer 21 away from the first substrate 11 , and the second insulating layer 19 is patterned to form a first via hole K1 and a second via hole K2 .

[0097] A second transparent electrode layer 22 is formed on the side of the second insulating layer 19 facing away from the first substrate 11, and the second transparent electrode layer 22 includes a pixel electrode 221, a first adapter line 223, and a second adapter line 222. The first adapter line 223 is connected to the connecting wire 154 through the first via K1 to achieve the connection between the pixel electrode 221 and the second electrode of the thin film transistor. The second adapter line 222 connects the connecting bridge 212 to the metal wire 152 through the second via K2 to achieve the connection between the touch electrode and the metal wire 152.

[0098] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer may be referred to as a gate insulating (GI) layer, the second insulating layer may be referred to as a second passivation layer (PVX2), and the third insulating layer may be referred to as a first passivation layer (PVX1). The metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The material of the first transparent electrode layer and the second transparent electrode layer may be a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The material of the planarization layer may be a resin material, the material of the color resist layer may be a resin material, and different color filters may use different colors of resin materials.

[0099] Based on the inventive concept of the above embodiments, the embodiments of the present disclosure further provide a display device, which includes a display panel using the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0100] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0101] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0102] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0103] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0104] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0105] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or replacements within the technical scope disclosed in the present disclosure. Different parts in different embodiments can be combined with each other without conflict, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: a first substrate; A first metal layer, located on one side of the first substrate, comprising a plurality of gate lines extending along a first direction; a first insulating layer, located on a side of the first metal layer away from the first substrate; a second metal layer, located on a side of the first insulating layer away from the first substrate, comprising a plurality of data lines and a plurality of metal traces extending along a second direction, wherein the plurality of data lines and the plurality of gate lines intersect with each other to define a plurality of sub-pixel regions arranged in an array, and the second direction intersects the first direction; an insulating material layer, located on a side of the second metal layer away from the first substrate, the insulating material layer comprising a color resist layer, and an orthographic projection of at least a portion of the data line and / or the metal routing on the first substrate is located within an orthographic projection of the color resist layer on the first substrate; The first transparent electrode layer is located on a side of the insulating material layer away from the first substrate, and includes a plurality of touch electrode blocks, and the touch electrode blocks are connected to the corresponding metal wirings.

2. The display substrate according to claim 1, characterized in that: The metal routing extends along the second direction in a column of sub-pixel areas, the color resist layer includes a color film located in the sub-pixel area, and the orthographic projection of a portion of the metal routing located in the sub-pixel area on the first substrate is located within the orthographic projection of the color film on the first substrate.

3. The display substrate according to claim 2, characterized in that: A plurality of metal routings are arranged one-to-one in a plurality of columns of sub-pixel areas, the touch electrode block comprises a plurality of sub-electrode blocks arranged in an array, the sub-electrode block is located between two adjacent gate lines and between two adjacent metal routings, and the orthographic projection of the metal routing on the first substrate does not overlap with the orthographic projection of the sub-electrode block on the first substrate.

4. The display substrate according to claim 3, characterized in that: The orthographic projection of the gate line on the first substrate does not overlap with the orthographic projection of the sub-electrode block on the first substrate, and adjacent sub-electrode blocks in the touch electrode block are connected via a connecting bridge.

5. The display substrate according to claim 1, characterized in that: The color resist layer includes a first color filter and a second color filter located in two adjacent sub-pixel areas in the first direction. In the first direction, a portion of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the first color filter on the first substrate, and another portion of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second color filter on the first substrate.

6. The display substrate according to claim 5, characterized in that: In the first direction, half of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the first color filter on the first substrate, and the other half of the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second color filter on the first substrate.

7. The display substrate according to claim 1, characterized in that: It also includes a thin film transistor located between two adjacent sub-pixel regions in the second direction, the thin film transistor includes an active layer, and the orthographic projection of the active layer on the first substrate is located within the orthographic projection of the color resist layer on the first substrate.

8. The display substrate according to claim 1, characterized in that: It also includes a second insulating layer and a second transparent electrode layer stacked in sequence on a side of the first transparent electrode layer away from the first substrate, the second transparent electrode layer includes a pixel electrode located in the sub-pixel area, and the second metal layer also includes a connecting wire; The display substrate further includes a thin film transistor located between two adjacent sub-pixel regions in the second direction, the second metal layer further includes a first electrode and a second electrode of the thin film transistor, the first electrode is connected to the corresponding data line, and the connecting wire is connected to the second electrode; The second insulating layer is provided with a first via hole, the first via hole is located between two adjacent sub-pixel areas in the second direction, the pixel electrode is connected to the connecting wire through the first via hole, the orthographic projection of the first via hole on the first substrate does not overlap with the orthographic projection of the color resist layer on the first substrate, and the orthographic projection of the first via hole on the first substrate does not overlap with the orthographic projection of the first transparent electrode layer on the first substrate.

9. The display substrate according to claim 1, characterized in that: The insulating material layer further includes a third insulating layer and a planarization layer. The third insulating layer is located between the second metal layer and the color resist layer. The planarization layer is located between the color resist layer and the first transparent electrode layer.

10. The display substrate according to claim 9, characterized in that: The display substrate further includes a second insulating layer and a second transparent electrode layer which are sequentially stacked on a side of the first transparent electrode layer away from the first substrate. The display substrate further includes a second via hole, the second via hole is located between two adjacent sub-pixel areas in the second direction, the orthographic projection of the second via hole on the first substrate does not overlap with the orthographic projection of the color resist layer on the first substrate, and the second transparent electrode layer includes a first adapter wire, the first adapter wire is connected to the touch electrode block through the second via hole, and is connected to the corresponding metal trace through the second via hole.

11. The display substrate according to claim 1, characterized in that: The display substrate is applied to a display panel, a common voltage signal is input to the touch electrode block during the process of the display panel displaying a frame image, and a touch driving signal is input to the touch electrode block between two frame images of the display panel.

12. A display panel, characterized in that: The display panel comprises the display substrate according to any one of claims 1 to 11, and further comprises an opposing substrate, wherein the opposing substrate is located on a side of the display substrate away from the first substrate, and the display panel further comprises a liquid crystal located between the display substrate and the opposing substrate.

13. The display panel according to claim 12, characterized in that: The opposing substrate includes a second substrate and a light-shielding layer arranged on the second substrate, the light-shielding layer includes a plurality of first light-shielding strips extending along a first direction and a plurality of second light-shielding strips extending along a second direction, the orthographic projection of the gate line on the first substrate is located within the orthographic projection of the first light-shielding strip on the first substrate, the orthographic projection of the data line on the first substrate is located within the orthographic projection of the second light-shielding strip on the first substrate, and the orthographic projection of the first via hole and the second via hole of the display substrate on the first substrate is located within the orthographic projection of the first light-shielding strip on the first substrate.

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