Undervoltage protection circuit device, chip and electronic equipment

Abstract

The utility model provides an under-voltage protection circuit device, a chip and electronic equipment, and the device comprises a sampling circuit which is used for carrying out the voltage division sampling of a power supply voltage, and obtaining a sampling voltage; the voltage comparison circuit is connected with the sampling circuit and is used for comparing the sampling voltage with the reference voltage and outputting a control signal according to a comparison result; and the output clamping circuit is connected with the voltage comparison circuit and is used for controlling the power supply voltage state when the under-voltage protection circuit device outputs the signal according to the control signal. According to the under-voltage protection circuit device containing the output clamping circuit, the low-voltage output clamping circuit is additionally arranged at the output node of the voltage comparison circuit of the under-voltage protection circuit device, so that the circuit can stably output under the condition of relatively low voltage; and the situation that normal operation of a chip is influenced by output of error signals due to incapability of normal operation at low voltage is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an undervoltage protection circuit device, a chip and an electronic device. Background Art

[0002] In various chip application scenarios, power supply undervoltage protection is essential. After the power supply is undervoltage, various modules inside the chip may not work properly, thereby outputting error signals, affecting the normal operation of the entire system, and even causing chip damage. In recent years, as the industry has developed towards low power consumption and high integration, the normal operating voltage of the chip has become lower and lower, and the undervoltage threshold has also decreased accordingly.

[0003] However, in the process of research and practice of the prior art, the inventor of the present application found that the threshold of the reference voltage circuit is easily affected by the process and has a large deviation, resulting in the situation that the reference voltage logic signal has been issued before the reference voltage is fully established. In the process of establishing the reference voltage, the reference voltage may be lower than the sampling voltage, resulting in the output of an erroneous undervoltage recovery signal, and the remaining circuit parts cannot work normally under low voltage conditions, and then output an erroneous signal, affecting the normal function of the chip; at the same time, if the undervoltage threshold of the chip is close to the reference voltage, the probability of an erroneous comparison will also be greatly increased.

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Utility Model Content

[0005] In view of this, the present application provides an undervoltage protection circuit device, chip and electronic device to solve the problem that the existing undervoltage protection circuit outputs an erroneous undervoltage recovery signal during the reference voltage establishment process, causing the remaining circuit parts to output an erroneous signal after failing to work normally at low voltage, thereby affecting the normal operation of the chip.

[0006] The present application provides an undervoltage protection circuit device, comprising:

[0007] The sampling circuit is used for dividing and sampling the power supply voltage to obtain a sampling voltage;

[0008] A voltage comparison circuit, connected to the sampling circuit, for comparing the sampled voltage with a reference voltage and outputting a control signal according to a comparison result;

[0009] The output clamp circuit is connected to the voltage comparison circuit and is used to control the power supply voltage state of the undervoltage protection circuit device when the undervoltage protection circuit device outputs a signal according to the control signal.

[0010] Optionally, the first end of the sampling circuit is connected to the first end of the voltage comparison circuit, the second end of the sampling circuit is connected to the third end of the output clamp circuit, the second end of the voltage comparison circuit is connected to the reference voltage, the third end of the voltage comparison circuit is connected to the power supply voltage, the fourth end of the voltage comparison circuit is connected to the second end of the output clamp circuit, the first end of the output clamp circuit is connected to the power supply voltage, and the fourth end of the output clamp circuit is connected to the third end of the sampling circuit.

[0011] Optionally, the sampling circuit includes a first resistor, a second resistor, a third resistor and a fourth resistor connected in series in sequence, the other end of the second resistor is the first end of the sampling circuit, connected to one end of the third resistor, the other end of the third resistor is the second end of the sampling circuit, connected to one end of the fourth resistor, and the other end of the fourth resistor is the third end of the sampling circuit; the voltage comparison circuit includes a comparator, the first input end of the comparator is the first end of the voltage comparison circuit, connected to the sampling circuit, the second input end of the comparator is the second end of the voltage comparison circuit, connected to the reference voltage, the third input end of the comparator is the third end of the voltage comparison circuit, connected to the power supply voltage, and the output end of the comparator is the fourth end of the voltage comparison circuit, connected to the output clamping circuit.

[0012] Optionally, the undervoltage protection circuit device also includes: a hysteresis circuit, which is respectively connected to the sampling circuit, the voltage comparison circuit and the output clamping circuit, and is used to provide a high voltage threshold and a low voltage threshold for the undervoltage protection circuit device to form a hysteresis effect and control the output signal of the voltage comparison circuit to flip; wherein the hysteresis circuit includes a first MOS tube.

[0013] Optionally, the output clamp circuit includes a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth resistor, a first current source, a first inverter and a second inverter. The source of the second MOS tube is the first end of the output clamp circuit and is connected to the power supply voltage. The gate of the second MOS tube is the second end of the output clamp circuit and is connected to the fourth end of the voltage comparison circuit. The drain of the second MOS tube is connected to the source of the third MOS tube. The gate of the third MOS tube is the third end of the output clamp circuit and is connected to the second end of the sampling circuit. The drain of the third MOS tube is respectively connected to one end of the first current source, one end of the fifth resistor and the input end of the first inverter. The other end of the first current source is the fourth end of the output clamp circuit and is respectively connected to the third end of the sampling circuit and the source of the fourth MOS tube. The drain of the fourth MOS tube is connected to the other end of the fifth resistor. The output end of the first inverter is connected to the input end of the second inverter. The output end of the second inverter outputs a power supply undervoltage signal.

[0014] Optionally, the output clamping circuit includes a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a sixth resistor, a second current source, a third inverter and a fourth inverter; one end of the second current source is the first end of the output clamping circuit, connected to the power supply voltage and the source of the fifth MOS tube, the drain of the fifth MOS tube is connected to one end of the sixth resistor, the other end of the second current source is respectively connected to the drain of the sixth MOS tube, the other end of the sixth resistor, the input end of the third inverter and the input end of the fourth inverter, the gate of the sixth MOS tube is the second end of the output clamping circuit, connected to the first end of the sampling circuit, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, the gate of the seventh MOS tube is the third end of the output clamping circuit, connected to the fourth end of the voltage comparison circuit, the source of the seventh MOS tube is the fourth end of the output clamping circuit, connected to the third end of the sampling circuit; the second end of the sampling circuit is connected to the first end of the voltage comparison circuit.

[0015] Optionally, the output clamping circuit includes an eighth MOS tube, a ninth MOS tube, a seventh resistor, a fifth inverter and a sixth inverter, the source of the eighth MOS tube is the first end of the output clamping circuit, connected to the power supply voltage, the gate of the eighth MOS tube is the second end of the output clamping circuit, connected to the fourth end of the voltage comparison circuit, the drain of the eighth MOS tube is connected to the source of the ninth MOS tube, the gate of the ninth MOS tube is the third end of the output clamping circuit, connected to the second end of the sampling circuit, the drain of the ninth MOS tube is respectively connected to the first end of the seventh resistor and the input end of the fifth inverter, the other end of the seventh resistor is the fourth end of the output clamping circuit, connected to the third end of the sampling circuit, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the first end of the sampling circuit is connected to the first end of the voltage comparison circuit.

[0016] Optionally, the output clamping circuit includes a tenth MOS tube, an eleventh MOS tube, an eighth resistor, a seventh inverter and an eighth inverter, one end of the eighth resistor is the first end of the output clamping circuit, connected to the power supply voltage, the other end of the eighth resistor is respectively connected to the drain of the tenth MOS tube, the input end of the seventh inverter and the input end of the eighth inverter, the gate of the tenth MOS tube is the second end of the output clamping circuit, connected to the first end of the sampling circuit, the source of the tenth MOS tube is connected to the drain of the eleventh MOS tube, the gate of the eleventh MOS tube is the third end of the output clamping circuit, connected to the fourth end of the voltage comparison circuit, the source of the eleventh MOS tube is the fourth end of the output clamping circuit, connected to the third end of the sampling circuit, and the second end of the sampling circuit is connected to the first end of the voltage comparison circuit.

[0017] The present application also provides a chip, comprising the undervoltage protection circuit device as described above.

[0018] The present application also provides an electronic device, comprising the undervoltage protection circuit device or chip as described above.

[0019] Implementing the embodiments of the present application has the following beneficial effects:

[0020] As described above, the present application provides an undervoltage protection circuit device, chip and electronic device, the undervoltage protection circuit device comprising: a sampling circuit for dividing and sampling the power supply voltage to obtain a sampling voltage; a voltage comparison circuit connected to the sampling circuit for comparing the sampling voltage with the reference voltage and outputting a control signal according to the comparison result; an output clamp circuit connected to the voltage comparison circuit for controlling the power supply voltage state when the undervoltage protection circuit device outputs a signal according to the control signal. The present application provides an undervoltage protection circuit device, by adding an output clamp circuit to the output node of the voltage comparison circuit of the undervoltage protection circuit device, so that the undervoltage protection circuit device can also output a fixed signal under a lower voltage, avoiding the comparison result outputted in advance by the voltage comparison circuit of the previous stage, ensuring that the undervoltage protection threshold converges near the preset undervoltage value, and at the same time will not affect the normal undervoltage protection threshold, so that the undervoltage recovery signal can be normally output during the fast and slow power-on process, solving the problem that some circuits cannot work normally under low voltage and then output error signals to affect the normal function operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0022] Figure 1 It is a structural schematic diagram of an existing undervoltage protection circuit;

[0023] Figure 2 is a schematic diagram of the structure of an undervoltage protection circuit device provided in an embodiment of the present application;

[0024] Figure 3 is a circuit diagram of a first implementation of an undervoltage protection circuit device provided in an embodiment of the present application;

[0025] Figure 4 is a circuit diagram of a second implementation of an undervoltage protection circuit device provided in an embodiment of the present application;

[0026] Figure 5 is a circuit diagram of a third implementation of an undervoltage protection circuit device provided in an embodiment of the present application;

[0027] Figure 6 4 is a circuit diagram of a fourth implementation of the undervoltage protection circuit device provided in an embodiment of the present application.

[0028] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0029] As described in the background art, the undervoltage protection circuit in the prior art outputs an erroneous undervoltage recovery signal during the process of establishing the reference voltage, causing some circuits to output an erroneous signal after failing to work normally at low voltage, thereby affecting the normal operation of the chip.

[0030] The inventor of this application has found that Figure 1 , which is a structural diagram of an existing undervoltage protection circuit. When the power supply voltage VCC is high, the power supply undervoltage signal UV_VCC is high, and the FB feedback signal is low, and M1 is turned on; VCC slowly decreases, and when VCC decreases to (1+R2 / R3)*VREF, VREF is the reference voltage, UV_VCC changes from high to low, and the feedback FB changes from low to high, and M1 is cut off; when VCC slowly rises from low to (1+(R1+R2) / R3)*VREF, UV_VCC changes from low to high, FB changes from high to low, and M1 is turned on. When powered on normally, the voltage reference module BG begins to build, at this time the BG_OK signal is low, and the UVP (undervoltage protection) circuit does not work. When the BG voltage of the voltage reference module is built, the BG_OK signal becomes high, and the UVP circuit starts to work. When the VCC voltage rises to VIP=VIN, the comparator COMP output gradually changes from high to low, UV_VCC changes from low to high, FB changes from high to low, M1 is turned on, the VIN terminal voltage further increases, and the comparator COMP output is quickly pulled down to ground. If the power supply voltage jitters at this time, the UV_VCC state will only change if the jitter amplitude is greater than (R1 / R3)*VREF, which effectively avoids the UV_VCC signal jumping back and forth caused by the jitter when the power supply is powered on. The inventors found that the existing undervoltage protection circuit starts to compare with the BG_OK signal output as high, but the BG_OK threshold of the voltage reference module fluctuates greatly. When the designed undervoltage threshold is low, under process deviation, during the power supply voltage establishment process, the VREF voltage is not established. At this time, the circuit starts to compare and sends out an erroneous undervoltage recovery signal; as the power supply voltage continues to rise, VREF gradually establishes to be greater than the sampling voltage, and the circuit outputs an undervoltage signal; the power supply voltage continues to rise until the sampling voltage is greater than the VREF voltage, at which time the correct undervoltage recovery signal is output; the back and forth switching of the undervoltage signal will cause the rest of the chip circuits to work abnormally, affecting the normal function of the chip.

[0031] In order to overcome the above technical defects, the inventor proposed a new solution, by adding a low-voltage output clamping circuit to the output node of the voltage comparison circuit of the undervoltage protection circuit device, so that some circuits can also output stably under lower voltage conditions, avoiding the situation where they cannot work normally at low voltage and then output error signals that affect the normal operation of the chip.

[0032] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0033] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of an undervoltage protection circuit device provided in one embodiment of the present application.

[0034] In this embodiment, an undervoltage protection circuit device is provided, including:

[0035] The sampling circuit 10 is used to divide the power supply voltage and sample it to obtain a sampled voltage. Specifically, the sampling circuit 10 performs sampling after dividing the voltage through a plurality of resistors, and the sampling voltage VIN and the power supply voltage VCC are in a linear relationship. The input end of the sampling circuit 10 is connected to the power supply voltage, and different output ends of the sampling circuit 10 are respectively connected to the voltage comparison circuit 20 and the output clamping circuit 30. In a specific embodiment, the sampling circuit 10 is also connected to a voltage reference module.

[0036] The voltage comparison circuit 20 is connected to the sampling circuit 10, and is used to compare the sampling voltage with the reference voltage, and output a control signal according to the comparison result. Specifically, the voltage comparison circuit 20 is controlled by the BG_OK voltage reference signal. When the BG_OK signal is valid, the voltage comparison circuit 20 starts to compare the reference voltage VREF and the sampling voltage VIN. Since the conduction state of the first MOS tube M1 is different when the power supply voltage VCC rises and falls, that is, the corresponding power supply voltage is different when the sampling voltage VIN is equal to the reference voltage VREF, the circuit undervoltage threshold and undervoltage recovery threshold are also different.

[0037] The output clamp circuit 30 is connected to the voltage comparison circuit 20 and is used to control the power supply voltage state of the undervoltage protection circuit device when the undervoltage protection circuit device outputs a signal according to the control signal. Specifically, the output clamp circuit 30 is connected to the voltage comparison circuit 20 and the sampling circuit 10 and is used to control the power supply voltage state of the undervoltage protection circuit device according to the control signal output by the voltage comparison circuit 20 of the previous stage.

[0038] Optionally, in some embodiments, the connection method of each component circuit in the undervoltage protection circuit device is as follows: the first end of the sampling circuit 10 is connected to the first end of the voltage comparison circuit 20, the second end of the sampling circuit 10 is connected to the third end of the output clamping circuit 30, the second end of the voltage comparison circuit 20 is connected to the reference voltage, the third end of the voltage comparison circuit 20 is connected to the power supply voltage, the fourth end of the voltage comparison circuit 20 is connected to the second end of the output clamping circuit 30, the first end of the output clamping circuit 30 is connected to the power supply voltage, and the fourth end of the output clamping circuit 30 is connected to the third end of the sampling circuit 10.

[0039] Optionally, in some embodiments, Figure 3 As shown, the sampling circuit 10 includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 connected in series in sequence, the other end of the second resistor R2 is the first end of the sampling circuit 10, connected to one end of the third resistor R3, the other end of the third resistor R3 is the second end of the sampling circuit 10, connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is the third end of the sampling circuit 10; wherein the sampling circuit 10 performs voltage division sampling through a plurality of resistors connected in series in sequence, and the sampling voltage is linearly related to the power supply voltage.

[0040] The voltage comparison circuit 20 includes a comparator, wherein the first input terminal VIN of the comparator is the first terminal of the voltage comparison circuit 20, connected to the sampling circuit 10 to access the sampling voltage, the second input terminal VIP of the comparator is the second terminal of the voltage comparison circuit 20, connected to the reference voltage VREF, the third input terminal of the comparator is the third terminal of the voltage comparison circuit 20, connected to the power supply voltage VCC, and the output terminal of the comparator is the fourth terminal of the voltage comparison circuit 20, connected to the output clamp circuit 30.

[0041] Optionally, in some embodiments, the undervoltage protection circuit device further includes:

[0042] The hysteresis circuit 40 is respectively connected to the sampling circuit 10, the voltage comparison circuit 20 and the output clamp circuit 30, and is used to provide a high voltage threshold and a low voltage threshold for the undervoltage protection circuit device to form a hysteresis effect and control the output signal of the voltage comparison circuit 20 to flip; wherein the hysteresis circuit 40 includes a first MOS tube M1.

[0043] Specifically, the hysteresis circuit 40 in this embodiment includes a first MOS tube M1, which is a PMOS tube. The source of the first MOS tube is connected to the power supply voltage, the drain of the first MOS tube is connected to one end of the sampling circuit 10, and is connected to the sampling voltage, and the gate of the first MOS tube outputs a feedback FB. This embodiment changes the proportional relationship between the sampling voltage and the power supply voltage by controlling the switch end of the first MOS tube M1.

[0044] In a specific embodiment, the undervoltage protection circuit device of this embodiment also includes a voltage reference module 50, which is respectively connected to the hysteresis circuit 40, the voltage comparison circuit 20 and the output clamping circuit 30, and the first end of the voltage reference module 50 is respectively connected to the source of the first MOS tube in the hysteresis circuit 40, the fifth end of the comparator of the voltage comparison circuit 20 and the source of the second MOS tube M2 of the output clamping circuit 30, the second end of the voltage reference module 50 is connected to the reference voltage, and the third end of the voltage reference module 50 outputs a voltage reference signal.

[0045] Alternatively, if Figure 3 As shown, in this embodiment, the output clamp circuit 30 includes a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth resistor R5, a first current source A1, a first inverter D1 and a second inverter D2. The source of the second MOS tube M2 is the first end of the output clamp circuit 30, which is connected to the power supply voltage. The gate of the second MOS tube M2 is the second end of the output clamp circuit 30, which is connected to the fourth end of the voltage comparison circuit 20. The drain of the second MOS tube M2 is connected to the source of the third MOS tube M3. The gate of the third MOS tube M3 is the third end of the output clamp circuit 30, which is connected to the second end of the sampling circuit 10. The drain of the third MOS tube M3 is connected to one end of the first current source A1, one end of the fifth resistor R5 and the input end of the first inverter D1 respectively. The first current source A1 is connected to the input end of the first current source A1, the first end of the fifth resistor R5 and the input end of the first inverter D1 respectively. The other end of 1 is the fourth end of the output clamp circuit 30, which is respectively connected to the third end of the sampling circuit 10 and the source of the fourth MOS tube M4, the drain of the fourth MOS tube M4 is connected to the other end of the fifth resistor R5, the output end of the first inverter D1 is connected to the input end of the second inverter D2, and the output end of the second inverter D2 outputs a power supply undervoltage signal or a power supply undervoltage recovery signal. The power supply undervoltage signal is used to indicate that the reference voltage of the current circuit is greater than the sampling voltage, and the output is high. At this time, the circuit outputs an undervoltage. The power supply undervoltage recovery signal is used to indicate that the sampling voltage of the current circuit is greater than the reference voltage, and the output is low. At this time, the circuit outputs a correct undervoltage recovery signal, the undervoltage does not occur, and the circuit output is normal, so that the operation state of the undervoltage protection circuit device is further controlled according to the power supply undervoltage signal or the power supply undervoltage recovery signal.

[0046] Specifically, the output clamp circuit 30 in this embodiment is composed of a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth resistor R5, a first current source A1, a first inverter D1 and a second inverter D2, wherein the second MOS tube M2 and the third MOS tube M3 are PMOS tubes, and the fourth MOS tube M4 is a PMOS tube.

[0047] In the specific operation process, when the output of the comparator in the voltage comparison circuit 20 of the current stage is low, if the power supply voltage can make the third MOS tube M3 turn on, the output state is flipped; if the power supply voltage cannot make the third MOS tube M3 turn on, it means that the power supply voltage is low at this time, the VREF voltage may not be established, and the comparison result of the comparator may be wrong. The third MOS tube M3 is cut off to keep the output state until the power supply voltage rises to make the third MOS tube M3 turn on, and then the output state is flipped. Among them, the main functions of the fourth MOS tube M4 and the fifth resistor R5 are: when the power supply voltage is low, the current mirror may have no current. At this time, the fourth MOS tube M4 is turned on, giving the output node an initial state of low, preventing the circuit from having an intermediate state and causing an erroneous signal output.

[0048] When the power supply voltage is high, UV_VCC is high, and the feedback FB is low; VCC slowly decreases, and when the VCC voltage drops to VCC=(1+R2 / (R3+R4))*VREF, at this time VIN=VREF, the comparator output state flips, FB gradually changes from low to high, UV_VCC changes from high to low, the fourth MOS tube M4 is turned on, the first MOS tube M1 is turned off, the sampling voltage jumps, and the switching process is accelerated; VCC rises from low to VCC=(1+(R1+R2) / (R3+R4))*VREF, at this time VIN=VREF, the comparator output state flips, FB changes from high to low, UV_VCC changes from low to high, the fourth MOS tube is turned off, the first MOS tube M1 is turned on, the sampling voltage jumps, and the shutdown switching process is accelerated.

[0049] In addition, under some extreme processes, when VCC rises from 0, the voltage of the reference voltage VREF gradually rises, and there is a deviation in the reference voltage VREF corresponding to the BG_OK output. When the reference voltage VREF is not fully established, the BG_OK signal has been output, and the comparator of the undervoltage protection circuit starts to work at this time; since the establishment process of the reference voltage VREF is nonlinear, and the sampling voltage is a linear rising process, before reaching the set undervoltage protection threshold, the sampling voltage may be higher than the VREF voltage, and the comparator output is low; the sampling voltage connected to the gate of the third MOS tube M3 is adjusted so that the minimum operating voltage VCC of the voltage reference module BG>(1+R4 / (R1+R2+R3))*Vthp, when the comparator outputs an error 0 signal, the third MOS tube M3 is in a cut-off state, the comparator output signal is shielded, and the output state remains unchanged. Only when VCC>(1+R4 / (R1+R2+R3))*Vthp, the comparator output signal can be transmitted to the output end, and at this time, the BG minimum operating voltage has been reached, the reference voltage VREF is established, and the comparison result is correct.

[0050] In summary, an undervoltage protection circuit device provided by an embodiment of the present application includes: a sampling circuit for sampling a power supply voltage by voltage division to obtain a sampling voltage; a voltage comparison circuit connected to the sampling circuit for comparing the sampling voltage with a reference voltage and outputting a control signal according to the comparison result; an output clamp circuit connected to the voltage comparison circuit for controlling the power supply voltage state when the undervoltage protection circuit device outputs a signal according to the control signal. The embodiment of the present application adds an output clamp circuit to the output node of the voltage comparison circuit of the undervoltage protection circuit device to ensure that the power supply voltage when the undervoltage protection circuit outputs a signal is higher than the working voltage of the voltage reference circuit, and the voltage compared with the sampling voltage is a reference voltage that has been established, thereby avoiding the output of an erroneous comparison result when the reference voltage is not fully established, so that the undervoltage protection circuit device can also output a fixed signal under a lower voltage, avoiding the comparison result outputted in advance by the voltage comparison circuit of the previous stage, ensuring that the undervoltage protection threshold converges near the preset undervoltage value, and at the same time will not affect the normal undervoltage protection threshold, so that the undervoltage recovery signal can be normally output during the fast and slow power-on process, solving the problem that some circuits cannot work normally under low voltage and then output erroneous signals to affect the normal function operation of the chip.

[0051] Alternatively, if Figure 4As shown, in other embodiments, a second implementation of the output clamp circuit 30 is provided. The output clamp circuit 30 is a clamp circuit using an NMOS tube. In this embodiment, the output clamp circuit 30 includes a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a sixth resistor R6, a second current source A2, a third inverter D3 and a fourth inverter D4; one end of the second current source A2 is the first end of the output clamp circuit 30, connected to the power supply voltage VCC and the source of the fifth MOS tube M5, the drain of the fifth MOS tube M5 is connected to one end of the sixth resistor R6, and the other end of the second current source A2 is connected to The drain of the sixth MOS tube M6, the other end of the sixth resistor R6, the input end of the third inverter D3 and the input end of the fourth inverter D4 are connected. The gate of the sixth MOS tube M6 is the second end of the output clamp circuit 30, connected to the first end of the sampling circuit 10. The source of the sixth MOS tube M6 is connected to the drain of the seventh MOS tube M7. The gate of the seventh MOS tube M7 is the third end of the output clamp circuit 30, connected to the fourth end of the voltage comparison circuit 20. The source of the seventh MOS tube M7 is the fourth end of the output clamp circuit 30, connected to the third end of the sampling circuit 10; the second end of the sampling circuit 10 is connected to the first end of the voltage comparison circuit 20. In this embodiment, by adding a clamp circuit using an NMOS tube to the output node of the voltage comparison circuit, it is avoided that the voltage comparison circuit of the previous stage compares and outputs the comparison result in advance, and ensures that the undervoltage protection threshold converges to the vicinity of the preset undervoltage value, and at the same time does not affect the normal undervoltage protection threshold, so that the undervoltage recovery signal can be normally output during the fast and slow power-on process, solving the problem that some circuits cannot work normally under low voltage and then output error signals to affect the normal function operation of the chip.

[0052] Alternatively, if Figure 5As shown, in other embodiments, a third implementation of the output clamp circuit 30 is also provided. The undervoltage protection circuit device in this embodiment is an undervoltage protection circuit device with a resistive load at the output node. In this embodiment, the output clamp circuit 30 includes an eighth MOS tube M8, a ninth MOS tube M9, a seventh resistor R7, a fifth inverter D5 and a sixth inverter D6. The source of the eighth MOS tube M8 is the first end of the output clamp circuit 30, which is connected to the power supply voltage VCC. The gate of the eighth MOS tube M8 is the second end of the output clamp circuit 30, which is connected to the voltage comparison circuit 2 The fourth end of the eighth MOS tube M8 is connected to the source of the ninth MOS tube M9, the gate of the ninth MOS tube M9 is the third end of the output clamp circuit 30, connected to the second end of the sampling circuit 10, the drain of the ninth MOS tube M9 is respectively connected to the first end of the seventh resistor R7 and the input end of the fifth inverter D5, the other end of the seventh resistor R7 is the fourth end of the output clamp circuit 30, connected to the third end of the sampling circuit 10, the output end of the fifth inverter D5 is connected to the input end of the sixth inverter D6, and the first end of the sampling circuit 10 is connected to the first end of the voltage comparison circuit 20. In this embodiment, by adding a clamp circuit using a resistor load to the output node of the voltage comparison circuit, it is avoided that the comparison result is output in advance due to the comparison of the previous voltage comparison circuit, and the under-voltage protection threshold is ensured to converge to the vicinity of the preset under-voltage value, and at the same time, the normal under-voltage protection threshold is not affected, so that the under-voltage recovery signal can be normally output in the fast and slow power-on process, and the problem that some circuits cannot work normally under low voltage and then output error signals to affect the normal function operation of the chip is solved.

[0053] Alternatively, if Figure 6As shown, in other embodiments, a fourth implementation of the output clamping circuit 30 is also provided. The undervoltage protection circuit device provided in this embodiment is an undervoltage protection circuit device using an NMOS tube clamping resistor load. In this embodiment, the output clamping circuit 30 includes a tenth MOS tube M10, an eleventh MOS tube M11, an eighth resistor R8, a seventh inverter D7 and an eighth inverter D8. One end of the eighth resistor R8 is the first end of the output clamping circuit 30, which is connected to the power supply voltage VCC. The other end of the eighth resistor R8 is connected to the drain of the tenth MOS tube M10, the drain of the seventh inverter D7 and the drain of the eighth inverter D8. The input end of the inverter D7 and the input end of the eighth inverter D8, the gate of the tenth MOS tube M10 is the second end of the output clamp circuit 30, connected to the first end of the sampling circuit 10, the source of the tenth MOS tube M10 is connected to the drain of the eleventh MOS tube M11, the gate of the eleventh MOS tube M11 is the third end of the output clamp circuit 30, connected to the fourth end of the voltage comparison circuit 20, the source of the eleventh MOS tube M11 is the fourth end of the output clamp circuit 30, connected to the third end of the sampling circuit 10, and the second end of the sampling circuit 10 is connected to the first end of the voltage comparison circuit 20. In this embodiment, by adding a clamp circuit using an NMOS tube clamp resistor load to the output node of the voltage comparison circuit, it is avoided that the voltage comparison circuit of the previous stage compares and outputs the comparison result in advance, ensures that the undervoltage protection threshold converges to the vicinity of the preset undervoltage value, and does not affect the normal undervoltage protection threshold, so that the undervoltage recovery signal can be normally output in the fast and slow power-on process, and solves the problem that some circuits cannot work normally under low voltage and then output error signals to affect the normal function operation of the chip.

[0054] In other embodiments, a chip is provided, comprising the undervoltage protection circuit device as described above.

[0055] In other embodiments, an electronic device is provided, including the undervoltage protection circuit device or chip as described above.

[0056] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0057] In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0058] In this application, the word "for example" is used to mean "used as an example, illustration or description". Any embodiment described as "for example" in this application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any person skilled in the art to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation.

[0059] It should be understood that those skilled in the art will recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

Claims

1. An undervoltage protection circuit device, characterized in that: include: The sampling circuit is used for dividing and sampling the power supply voltage to obtain a sampling voltage; A voltage comparison circuit, connected to the sampling circuit, for comparing the sampled voltage with a reference voltage and outputting a control signal according to a comparison result; The output clamp circuit is connected to the voltage comparison circuit and is used to control the power supply voltage state of the undervoltage protection circuit device when the undervoltage protection circuit device outputs a signal according to the control signal.

2. The undervoltage protection circuit device according to claim 1, characterized in that: The first end of the sampling circuit is connected to the first end of the voltage comparison circuit, the second end of the sampling circuit is connected to the third end of the output clamp circuit, the second end of the voltage comparison circuit is connected to the reference voltage, the third end of the voltage comparison circuit is connected to the power supply voltage, the fourth end of the voltage comparison circuit is connected to the second end of the output clamp circuit, the first end of the output clamp circuit is connected to the power supply voltage, and the fourth end of the output clamp circuit is connected to the third end of the sampling circuit.

3. The undervoltage protection circuit device according to claim 1, characterized in that: The sampling circuit comprises a first resistor, a second resistor, a third resistor and a fourth resistor connected in series in sequence, the other end of the second resistor is the first end of the sampling circuit and is connected to one end of the third resistor, the other end of the third resistor is the second end of the sampling circuit and is connected to one end of the fourth resistor, and the other end of the fourth resistor is the third end of the sampling circuit; The voltage comparison circuit includes a comparator, wherein the first input terminal of the comparator is the first terminal of the voltage comparison circuit, connected to the sampling circuit, the second input terminal of the comparator is the second terminal of the voltage comparison circuit, connected to the reference voltage, the third input terminal of the comparator is the third terminal of the voltage comparison circuit, connected to the power supply voltage, and the output terminal of the comparator is the fourth terminal of the voltage comparison circuit, connected to the output clamping circuit.

4. The undervoltage protection circuit device according to claim 1, characterized in that: Also includes: A hysteresis circuit is respectively connected to the sampling circuit, the voltage comparison circuit and the output clamp circuit, and is used to provide a high voltage threshold and a low voltage threshold for the undervoltage protection circuit device to form a hysteresis effect and control the output signal of the voltage comparison circuit to flip; wherein the hysteresis circuit includes a first MOS tube.

5. The undervoltage protection circuit device according to claim 2, characterized in that: The output clamp circuit includes a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth resistor, a first current source, a first inverter and a second inverter. The source of the second MOS tube is the first end of the output clamp circuit and is connected to the power supply voltage. The gate of the second MOS tube is the second end of the output clamp circuit and is connected to the fourth end of the voltage comparison circuit. The drain of the second MOS tube is connected to the source of the third MOS tube. The gate of the third MOS tube is the third end of the output clamp circuit and is connected to the second end of the sampling circuit. The drain of the third MOS tube is respectively connected to one end of the first current source, one end of the fifth resistor and the input end of the first inverter. The other end of the first current source is the fourth end of the output clamp circuit and is respectively connected to the third end of the sampling circuit and the source of the fourth MOS tube. The drain of the fourth MOS tube is connected to the other end of the fifth resistor. The output end of the first inverter is connected to the input end of the second inverter. The output end of the second inverter outputs a power supply undervoltage signal.

6. The undervoltage protection circuit device according to claim 1, characterized in that: The output clamp circuit includes a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a sixth resistor, a second current source, a third inverter and a fourth inverter; one end of the second current source is the first end of the output clamp circuit, connected to the power supply voltage and the source of the fifth MOS tube, the drain of the fifth MOS tube is connected to one end of the sixth resistor, the other end of the second current source is respectively connected to the drain of the sixth MOS tube, the other end of the sixth resistor, the input end of the third inverter and the input end of the fourth inverter, the gate of the sixth MOS tube is the second end of the output clamp circuit, connected to the first end of the sampling circuit, the source of the sixth MOS tube is connected to the drain of the seventh MOS tube, the gate of the seventh MOS tube is the third end of the output clamp circuit, connected to the fourth end of the voltage comparison circuit, the source of the seventh MOS tube is the fourth end of the output clamp circuit, connected to the third end of the sampling circuit; the second end of the sampling circuit is connected to the first end of the voltage comparison circuit.

7. The undervoltage protection circuit device according to claim 1, characterized in that: The output clamp circuit includes an eighth MOS tube, a ninth MOS tube, a seventh resistor, a fifth inverter and a sixth inverter. The source of the eighth MOS tube is the first end of the output clamp circuit and is connected to the power supply voltage. The gate of the eighth MOS tube is the second end of the output clamp circuit and is connected to the fourth end of the voltage comparison circuit. The drain of the eighth MOS tube is connected to the source of the ninth MOS tube. The gate of the ninth MOS tube is the third end of the output clamp circuit and is connected to the second end of the sampling circuit. The drain of the ninth MOS tube is respectively connected to the first end of the seventh resistor and the input end of the fifth inverter. The other end of the seventh resistor is the fourth end of the output clamp circuit and is connected to the third end of the sampling circuit. The output end of the fifth inverter is connected to the input end of the sixth inverter. The first end of the sampling circuit is connected to the first end of the voltage comparison circuit.

8. The undervoltage protection circuit device according to claim 1, characterized in that: The output clamp circuit includes a tenth MOS tube, an eleventh MOS tube, an eighth resistor, a seventh inverter and an eighth inverter. One end of the eighth resistor is the first end of the output clamp circuit and is connected to the power supply voltage. The other end of the eighth resistor is respectively connected to the drain of the tenth MOS tube, the input end of the seventh inverter and the input end of the eighth inverter. The gate of the tenth MOS tube is the second end of the output clamp circuit and is connected to the first end of the sampling circuit. The source of the tenth MOS tube is connected to the drain of the eleventh MOS tube. The gate of the eleventh MOS tube is the third end of the output clamp circuit and is connected to the fourth end of the voltage comparison circuit. The source of the eleventh MOS tube is the fourth end of the output clamp circuit and is connected to the third end of the sampling circuit. The second end of the sampling circuit is connected to the first end of the voltage comparison circuit.

9. A chip, characterized in that: It comprises an undervoltage protection circuit device as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: It comprises the undervoltage protection circuit device as described in any one of claims 1 to 8 or the chip as described in claim 9.

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