Solar cell

Abstract

The utility model discloses a solar cell, which relates to the technical field of solar cell manufacturing and comprises a silicon substrate. The emitting electrode and the first passivation anti-reflection structure are arranged on one side of the silicon substrate in the thickness direction from inside to outside, and the first passivation anti-reflection structure comprises a first passivation anti-reflection layer and a second passivation anti-reflection layer; the tunneling oxide layer, the doped polycrystalline silicon layer and the second passivation anti-reflection structure are arranged on the other side of the thickness direction of the silicon substrate from inside to outside, the second passivation anti-reflection structure comprises a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, and the second passivation anti-reflection layer and the fourth passivation anti-reflection layer are arranged on the edge area of the silicon substrate. According to the embodiment, the thickness of the passivation anti-reflection layer on the edge of the silicon substrate is effectively increased, and the passivation performance and the photoelectric conversion efficiency of the edge of the solar cell are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cell manufacturing, in particular to a solar cell preparation method and a back contact solar cell. Background Art

[0002] Existing tunnel oxide passivation contact solar cells prepare an ultra-thin silicon oxide layer (also known as a tunnel oxide layer) and a highly doped polysilicon layer on the silicon surface, and utilize the ultra-thin silicon oxide layer's selective permeability to carriers and the highly doped polysilicon layer's good field passivation effect with the substrate to effectively suppress the recombination of minority carriers on the silicon surface and improve the cell's opening voltage. However, as the area of ​​solar cells continues to increase, during the mass production of solar cells, due to the influence of edge airflow, uneven heating will occur, resulting in a thinner silicon oxide layer at the edge, affecting the passivation uniformity of the entire cell, thereby affecting the cell's conversion efficiency. Utility Model Content

[0003] In view of this, an embodiment of the utility model provides a solar cell and a preparation method thereof. By providing a first passivation anti-reflection structure including a first passivation anti-reflection layer and a second passivation anti-reflection layer, and a second passivation anti-reflection structure including a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, the thickness of the passivation anti-reflection layer at the edge of the silicon substrate can be effectively increased, and the passivation performance of the edge of the solar cell can be improved, thereby increasing the overall photoelectric conversion efficiency of the solar cell.

[0004] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0005] In a first aspect, the utility model provides a solar cell, comprising: a silicon substrate; an emitter and a first passivation anti-reflection structure arranged from the inside to the outside on one side in the thickness direction of the silicon substrate, wherein the first passivation anti-reflection structure comprises a first passivation anti-reflection layer and a second passivation anti-reflection layer, and the second passivation anti-reflection layer is arranged in an edge region on the silicon substrate; a tunneling oxide layer, a doped polysilicon layer and a second passivation anti-reflection structure arranged from the inside to the outside on the other side in the thickness direction of the silicon substrate, wherein the second passivation anti-reflection structure comprises a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, and the fourth passivation anti-reflection layer is arranged in an edge region of the silicon substrate.

[0006] Optionally, the first passivation anti-reflection layer and the fourth passivation anti-reflection layer are formed simultaneously, and the second passivation anti-reflection layer and the third passivation anti-reflection layer are formed simultaneously.

[0007] Optionally, the fourth passivation anti-reflection layer is formed by controlling the fitting distance between the silicon substrate and the carrier when preparing the first passivation anti-reflection layer by coating; the second passivation anti-reflection layer is formed by controlling the fitting distance between the silicon substrate and the carrier when preparing the third passivation anti-reflection layer by coating.

[0008] Optionally, the second passivation anti-reflection layer is arranged outside the first passivation anti-reflection layer; and the fourth passivation anti-reflection layer is arranged between the doped polysilicon layer and the third passivation anti-reflection layer.

[0009] Optionally, the second passivation anti-reflection layer is arranged between the first passivation anti-reflection layer and the emitter; and the fourth passivation anti-reflection layer is arranged outside the third passivation anti-reflection layer.

[0010] Optionally, the width of the second passivation anti-reflection layer is 0.5 mm to 10 mm; and / or the width of the fourth passivation anti-reflection layer is 0.5 mm to 10 mm.

[0011] Optionally, the first passivation anti-reflection layer and / or the fourth passivation anti-reflection layer include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride; and / or the second passivation anti-reflection layer and / or the third passivation anti-reflection layer include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride.

[0012] Optionally, the thickness of the first passivation anti-reflection layer and / or the fourth passivation anti-reflection layer is 20 nm to 180 nm; and / or the thickness of the second passivation anti-reflection layer and / or the third passivation anti-reflection layer is 25 nm to 200 nm.

[0013] Optionally, the thickness of the tunnel oxide layer is 0.5 nm to 5 nm; and / or the thickness of the doped polysilicon layer is 30 nm to 200 nm.

[0014] In a second aspect, the utility model provides a method for preparing the above-mentioned solar cell, comprising:

[0015] Step 1, preparing an emitter on one side in the thickness direction of the silicon substrate;

[0016] Step 2, preparing a tunneling oxide layer and a doped polysilicon layer in sequence from inside to outside on the other side in the thickness direction of the silicon substrate;

[0017] Step 3, preparing a first passivation anti-reflection structure and a second passivation anti-reflection structure on the outside of the emitter and the outside of the doped polysilicon layer, respectively; wherein the first passivation anti-reflection structure includes a first passivation anti-reflection layer and a second passivation anti-reflection layer, and the second passivation anti-reflection layer is arranged in the edge area of ​​the silicon substrate; the second passivation anti-reflection structure includes a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, and the fourth passivation anti-reflection layer is arranged in the edge area of ​​the silicon substrate.

[0018] The technical solution of the first aspect of the above-mentioned utility model has the following advantages or beneficial effects: by providing a first passivation anti-reflection structure including a first passivation anti-reflection layer and a second passivation anti-reflection layer, and a second passivation anti-reflection structure including a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, the thickness of the passivation anti-reflection layer at the edge of the silicon substrate can be effectively increased, and the passivation performance of the edge of the solar cell can be improved, thereby increasing the overall photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to better understand the present invention and do not constitute an improper limitation on the present invention.

[0020] Figure 1 It is a schematic diagram of the overall structure of a graphite boat carrier according to an embodiment of the utility model;

[0021] Figure 2 is a front view of a graphite boat carrier with a silicon substrate inserted therein according to an embodiment of the utility model;

[0022] Figure 3 is a schematic cross-sectional structure diagram of a solar cell structure provided according to an embodiment of the utility model;

[0023] Figure 4 is a schematic cross-sectional structure diagram of another solar cell structure provided according to an embodiment of the utility model;

[0024] Figure 5 It is a schematic diagram of a process of preparing a solar cell provided according to an embodiment of the utility model;

[0025] Figure 6 is a schematic cross-sectional structure diagram of a silicon substrate prepared in step S501 according to an embodiment of the present utility model;

[0026] Figure 7 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared in step S502 according to an embodiment of the present utility model;

[0027] Figure 8 It is a schematic diagram of a specific process for preparing a first passivation anti-reflection structure and a second passivation anti-reflection structure according to an embodiment of the utility model;

[0028] Fig. 9 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared in step S801 according to an embodiment of the present utility model;

[0029] Fig.10 is a schematic diagram of the cross-sectional structure of a silicon substrate prepared in step S802 according to an embodiment of the present utility model;

[0030] Fig.11 It is another specific process diagram of preparing a first passivation anti-reflection structure and a second passivation anti-reflection structure according to an embodiment of the utility model;

[0031] Fig.12 It is a schematic diagram of the cross-sectional structure of the silicon substrate prepared in step S1101 according to an embodiment of the present utility model;

[0032] Fig.13 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared in step S1102 according to an embodiment of the present utility model;

[0033] Fig.14 It is the PL result of the solar cell obtained according to the first embodiment provided by the embodiment of the utility model;

[0034] Fig.15 This is the PL result of the solar cell obtained according to Comparative Example 1 provided in the embodiment of the present utility model.

[0035] The reference numerals are as follows:

[0036] 1-silicon substrate; 2-emitter; 3-first passivation anti-reflection structure; 31-first passivation anti-reflection layer; 32-second passivation anti-reflection layer; 4-first metal electrode; 5-tunneling oxide layer; 6-doped polysilicon layer; 7-second passivation anti-reflection structure; 71-third passivation anti-reflection layer; 72-fourth passivation anti-reflection layer; 8-second metal electrode. DETAILED DESCRIPTION

[0037] A solar cell is a photoelectric semiconductor wafer that uses sunlight to generate electricity directly. It is also called a "solar chip" or "photovoltaic cell". As long as it is illuminated by light that meets certain illumination conditions, it can instantly output voltage and generate current in the presence of a circuit. In physics, it is called solar photovoltaic (PV), or photovoltaic for short. In order to conveniently and clearly describe the method for preparing a solar cell and the solar cell of the utility model, the following exemplary embodiments of the utility model are described in conjunction with the accompanying drawings, including various details of the embodiments of the utility model to facilitate understanding, and they should be considered to be merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the utility model. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0038] In recent years, with the development of monocrystalline solar cells, especially the successful industrialization of passivated emitter and back field (PERC) technology, the efficiency improvement of mass-produced cells on P-type silicon wafers has reached a bottleneck. More attention has been paid to N-type cells with higher body minority carrier lifetime and lower attenuation. Three types of cell structures, including N-type PERT, heterojunction (HJT) and tunneling oxide passivated contact (TOPCon), have also gradually attracted attention from the industry. Among them, TOPCon cells, or passivated contact cells, have a structure in which an ultra-thin silicon oxide layer and a highly doped polysilicon layer are prepared on the silicon surface. The selective permeability of ultra-thin silicon oxide to carriers and the good field passivation effect of highly doped polysilicon and the substrate are used to effectively suppress the recombination of minority carriers on the silicon surface and increase the cell opening voltage.

[0039] However, existing passivation contact cells usually use a whole-layer deposition method to deposit an oxide layer and a doped polysilicon layer in sequence. During the mass production of solar cells, due to the influence of edge airflow, uneven heating will occur, resulting in a thinner oxide layer and doped polysilicon layer at the edge, affecting the passivation uniformity of the entire cell, thereby affecting the conversion efficiency of the cell. For this, the current solutions are to improve the structure of the production equipment or adjust the process parameters of the deposition method to obtain a more uniform film layer, which not only has a high optimization cost, but also has a complex process and poor effect. Therefore, the embodiment of the utility model solves this problem by improving the structure of the solar cell.

[0040] In one embodiment of the utility model, this embodiment provides a solar cell, comprising: a silicon substrate 1; an emitter 2 and a first passivation anti-reflection structure 3 arranged from the inside to the outside on one side of the silicon substrate 1 in the thickness direction, wherein the first passivation anti-reflection structure 3 includes a first passivation anti-reflection layer 31 and a second passivation anti-reflection layer 32, and the second passivation anti-reflection layer 32 is arranged in the edge area of ​​the silicon substrate 1; a tunneling oxide layer 5, a doped polycrystalline silicon layer 6 and a second passivation anti-reflection structure 7 arranged from the inside to the outside on the other side of the silicon substrate 1 in the thickness direction, wherein the second passivation anti-reflection structure 7 includes a third passivation anti-reflection layer 71 and a fourth passivation anti-reflection layer 72, and the fourth passivation anti-reflection layer 72 is arranged in the edge area of ​​the silicon substrate 1.

[0041] Among them, the first passivation anti-reflection layer 31 and the third passivation anti-reflection layer 71 can be understood as the front passivation anti-reflection layer and the back passivation anti-reflection layer of the conventional structure in the prior art, which are deposited on the outer side of the emitter 2 on the front side of the silicon substrate 1 and the outer side of the doped polysilicon layer 6 on the back side, respectively, and cover the outer side of the emitter 2 and the outer side of the doped polysilicon layer 6. The second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are only arranged on the edge area of ​​the silicon substrate 1. It can be understood that if the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are also arranged as a whole layer deposition, although the thickness of the edge area of ​​the silicon substrate 1 can be increased, it will also affect the light absorption of the middle part of the silicon substrate 1. Therefore, in order to achieve the problem of uneven thickness of the edge oxide layer solved by the embodiment of the utility model, the passivation anti-reflection layer is only additionally arranged in the edge area to increase the thickness of the passivation anti-reflection layer in the edge area. In an optional embodiment, when the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 are formed simultaneously, the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 are formed simultaneously. It should be noted that the embodiment of the utility model does not add an additional preparation process, but on the basis of the existing preparation of the first passivation anti-reflection layer 31 and the third passivation anti-reflection layer 71, the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are formed simultaneously, without adding an additional process, and on the basis of ensuring the existing process, an additional technical effect is added.

[0042] Specifically, the embodiment of the utility model realizes the synchronous preparation process of the above-mentioned passivation anti-reflection layers on different sides by controlling the fitting distance between the silicon substrate 1 and the carrier, wherein the carrier can be understood as a carrier or container for loading the silicon substrate 1 and depositing the passivation anti-reflection layer, usually a graphite boat carrier. In an optional embodiment, the fourth passivation anti-reflection layer 72 is formed by controlling the fitting distance between the silicon substrate 1 and the carrier during the preparation of the first passivation anti-reflection layer 31 by plating; the second passivation anti-reflection layer 32 is formed by controlling the fitting distance between the silicon substrate 1 and the carrier during the preparation of the third passivation anti-reflection layer 71 by plating. It can be understood that since the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 are formed by wrapping, they can be formed by wrapping in multiple edge areas around the silicon substrate 1, that is, taking the silicon substrate 1 as a rectangular silicon wafer as an example, they can be formed by wrapping on the four sides of the rectangle respectively, or they can be formed by wrapping only on the two sides parallel to the metal electrode or the two sides perpendicular to the metal electrode according to actual needs. The utility model does not make specific limitations on this and can be set according to actual conditions.

[0043] For example, Figure 1 and Figure 2 The positional relationship between the silicon substrate 1 and the graphite boat carrier is described by taking the silicon substrate 1 as an example. Figure 1 This is a schematic diagram of the overall structure of the graphite boat carrier. Figure 2 FIG. 1 is a front view of a graphite boat carrier into which a silicon substrate 1 is inserted. Figure 1 It can be seen that the graphite boat carrier 100 includes a plurality of partitions, and a longitudinal loading space (such as Figure 1 The position indicated by the arrow in the middle), that is, during the preparation process, the silicon substrate 1 is longitudinally inserted into the interior of the graphite boat carrier 100 for deposition. Figure 1 and Figure 2It can be seen that a plurality of graphite boat clamping points a, i.e., fulcrums for clamping the silicon substrate 1, are provided on the graphite boat carrier 100. By controlling the left and right, as well as the up and down positions of the plurality of graphite boat clamping points, on the one hand, the silicon substrate 1 can be firmly clamped inside the graphite boat carrier 100 without displacement, and on the other hand, the specific placement position of the silicon substrate 1 in the graphite boat carrier 100 and the fitting distance with the graphite boat carrier 100 can be controlled, and the fitting distance between the silicon substrate 1 and the graphite boat carrier 100 can determine whether wrap-around plating occurs during the deposition of the passivation anti-reflection layer. It can be understood that within a certain range, the greater the fitting distance between the silicon substrate 1 and the graphite boat carrier 100 (i.e., the greater the gap spacing), the greater the width of the passivation anti-reflection layer to be plated, and the smaller the fitting distance between the silicon substrate 1 and the graphite boat carrier 100 (i.e., the smaller the gap spacing), the smaller the width of the passivation anti-reflection layer to be plated. However, the width of the plating process itself is limited to a certain extent. It is impossible for the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 formed by the plating process to cover the entire first passivation anti-reflection layer 31 and the outside of the third passivation anti-reflection layer. Therefore, the embodiment of the utility model can effectively control the width of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 formed by the plating process by controlling the fitting distance between the silicon substrate 1 and the graphite boat carrier 100, thereby controlling the quality of the final solar cell.

[0044] In an optional embodiment, the widths of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 should not be too large or too small. Specifically, the width of the second passivation anti-reflection layer 32 is 0.5 mm to 10 mm, such as 0.5 mm, 1 mm, 2.5 mm, 3.5 mm, 5 mm, 6.5 mm, 8 mm, 9 mm, 10 mm, etc.; when the positional relationship between the silicon substrate 1 and the graphite boat carrier 100 is not changed, the width of the fourth passivation anti-reflection layer 72 can also be set to 0.5 mm to 10 mm, such as 0.5 mm, 1 mm, 2.5 mm, 3.5 mm, 5 mm, 6.5 mm, 8 mm, 9 mm, 10 mm, etc. It is understandable that if the width of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 is set too large, the light absorption in the middle part of the silicon substrate 1 will be lost, affecting the light conversion efficiency of the solar cell. If the width of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 is set too small, the problem of thin oxide layer thickness cannot be effectively improved. Therefore, the embodiment of the utility model sets the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 to 0.5mm~10mm, which can achieve the technical effect to be achieved by the utility model without affecting the performance of the solar cell.

[0045] In the embodiments of the present invention, when different preparation orders are used to prepare the passivation anti-reflection layer, different solar cell structures will be formed. Therefore, the present invention describes the solar cell structures obtained by preferentially preparing the front passivation anti-reflection layer and preferentially preparing the back passivation anti-reflection layer. Specifically, Figure 3 and Figure 4 As shown. Among them, Figure 3 The solar cell structure obtained by preferentially preparing the front passivation anti-reflection layer is shown. Figure 4 The solar cell structure obtained by preferentially preparing a back-side passivation anti-reflection layer is shown.

[0046] like Figure 3 As shown, the second passivation anti-reflection layer 32 is arranged outside the first passivation anti-reflection layer 31, and the fourth passivation anti-reflection layer 72 is arranged between the doped polysilicon layer 6 and the third passivation anti-reflection layer 71. It can be understood that since the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 are formed synchronously, when the first passivation anti-reflection layer 31 on the front side of the silicon substrate 1 is preferentially prepared, the fourth passivation anti-reflection layer 72 will be synchronously formed at both ends of the edge on the back side of the silicon substrate 1, so when the third passivation anti-reflection layer 71 is prepared outside the fourth passivation anti-reflection layer on the back side of the silicon substrate 1, the synchronously formed second passivation anti-reflection layer 32 will be outside the first passivation anti-reflection layer 31.

[0047] like Figure 4 As shown, the second passivation anti-reflection layer 32 is disposed between the first passivation anti-reflection layer 31 and the emitter 2, and the fourth passivation anti-reflection layer 72 is disposed outside the third passivation anti-reflection layer 71. Similar to the above process, when the passivation anti-reflection layer on the back side of the silicon substrate 1 is prepared first, the third passivation anti-reflection layer 71 will be located between the fourth passivation anti-reflection layer 72 and the doped polysilicon layer 6, and when the fourth passivation anti-reflection layer 72 is prepared first, the second passivation anti-reflection layer 32 will also be formed on the front side first, and then the first passivation anti-reflection layer 31 will be formed outside the second passivation anti-reflection layer 32.

[0048] Through the above Figure 3 and Figure 4 It can be seen that the embodiments of the utility model can obtain solar cells with different structures through two different preparation sequences, both of which can achieve the purpose of increasing the thickness of the passivation anti-reflection layer at the edge of the silicon substrate, improving the passivation performance of the edge of the solar cell, and thus increasing the overall photoelectric conversion efficiency of the solar cell.

[0049] As for the material of the passivation anti-reflection layer, since the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 are formed at the same time, and the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 are formed at the same time, the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 are made of the same material, and the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 are made of the same material. In an optional embodiment, the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride; the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 include at least one of the following materials: aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride. It should be noted that the passivation anti-reflection layer actually includes a passivation layer and an anti-reflection layer, which is usually a multilayer structure stacked together. Therefore, the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 in the embodiment of the utility model are actually formed by a combination of at least two of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, and silicon oxynitride.

[0050] It can be understood that when the materials of the first passivation anti-reflection layer 31, the second passivation anti-reflection layer 32, the third passivation anti-reflection layer 71 and the fourth passivation anti-reflection layer 72 are the same, the embodiment of the present invention provides Figure 3 as well as Figure 4 The structures are substantially the same, and when the first passivation anti-reflection layer 31 and the second passivation anti-reflection layer 32 are made of different materials, the embodiment of the utility model provides Figure 3 as well as Figure 4 The above mentioned structural differences exist.

[0051] As for the thickness of the deposition, generally, the thickness of the first passivation anti-reflection layer 31 and the fourth passivation anti-reflection layer 72 deposited simultaneously are the same, and the thickness of the second passivation anti-reflection layer 32 and the third passivation anti-reflection layer 71 deposited simultaneously are the same. In an optional embodiment, the thickness of the first passivation anti-reflection layer 31 and / or the fourth passivation anti-reflection layer 72 is 20nm to 180nm, for example, 20nm, 30nm, 50nm, 80nm, 100nm, 120nm, 150nm, 160nm, 180nm, etc. At the same time, the thickness of the second passivation anti-reflection layer 32 and / or the third passivation anti-reflection layer 71 is 25nm to 200nm, for example, 25nm, 40nm, 60nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, etc.

[0052] For the thickness of the tunnel oxide layer 5, in an optional embodiment, it can be 0.5nm to 5nm, such as 0.5nm, 0.8nm, 1.2nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, etc. For the thickness of the doped polysilicon layer 6, in an optional embodiment, it can be 30nm to 200nm, such as 30nm, 80nm, 150nm, 200nm, etc. In order to ensure the photoelectric conversion performance of the solar cell, it is necessary to ensure that the concentration of the doping element in the doped polysilicon layer 6 is 1E20 to 1E21atom / cm 3 , where E can be understood as the value 10, 1E20 = 1*10 20 At the same time, it is also necessary to ensure that the concentration of the doping element in the emitter 2 is 1E18~1E19atom / cm 3 .

[0053] In addition, in an optional embodiment, a first metal electrode 4 is provided on one side of the silicon substrate 1 in the thickness direction, and a second metal electrode 8 is provided on the other side of the silicon substrate 1 in the thickness direction, wherein the first metal electrode 4 penetrates the first passivation anti-reflection layer 31 and is electrically connected to the emitter 2, and the second metal electrode 8 penetrates the third passivation anti-reflection layer 71 and is electrically connected to the doped polysilicon layer 6.

[0054] In summary, the solar cell provided by the embodiment of the utility model can effectively increase the thickness of the passivation anti-reflection layer at the edge of the silicon substrate and improve the passivation performance of the edge of the solar cell, thereby increasing the overall photoelectric conversion efficiency of the solar cell, by providing a first passivation anti-reflection structure including a first passivation anti-reflection layer and a second passivation anti-reflection layer, and a second passivation anti-reflection structure including a third passivation anti-reflection layer and a fourth passivation anti-reflection layer.

[0055] Figure 5 A schematic diagram of a process for preparing a solar cell provided by an embodiment of the utility model is shown, such as Figure 5 As shown, the method for preparing a solar cell provided by the utility model includes:

[0056] Step S501, preparing an emitter 2 on one side in the thickness direction of the silicon substrate 1;

[0057] Step S502, preparing a tunneling oxide layer 5 and a doped polysilicon layer 6 in sequence from the inside to the outside on the other side of the silicon substrate 1 in the thickness direction;

[0058] Step S503, preparing a first passivation anti-reflection structure 3 and a second passivation anti-reflection structure 7 on the outside of the emitter 2 and the outside of the doped polysilicon layer 6, respectively; wherein the first passivation anti-reflection structure 3 includes a first passivation anti-reflection layer 31 and a second passivation anti-reflection layer 32, and the second passivation anti-reflection layer 32 is arranged in the edge area of ​​the silicon substrate 1; the second passivation anti-reflection structure 5 includes a third passivation anti-reflection layer 71 and a fourth passivation anti-reflection layer 72, and the fourth passivation anti-reflection layer 72 is arranged in the edge area of ​​the silicon substrate 1.

[0059] The silicon substrate structure prepared in step S501 is as follows: Figure 6 As shown, the silicon substrate structure prepared in step S502 is as follows Figure 7 As shown. Figure 6 and Figure 7 It can be seen that after step S501 and step S502, a P+ emitter and a passivation contact structure (tunneling oxide layer and doped polysilicon layer) have been formed on both sides of the silicon substrate 1 in the thickness direction, respectively. Regardless of whether the front passivation anti-reflection layer or the back passivation anti-reflection layer is prepared first, before preparing the passivation anti-reflection layer, step S501 and step S502 are the same.

[0060] In an optional embodiment, when the passivation anti-reflection layer on the front side of the silicon substrate 1 is prepared first, step S503 can be as follows: Figure 8 As shown, including:

[0061] Step S801, while preparing the first passivation anti-reflection layer 31 on the outer side of the emitter 2, a fourth passivation anti-reflection layer 72 is formed on the outer side of the doped polysilicon layer 6;

[0062] Step S802 , while preparing the third passivation anti-reflection layer 71 outside the fourth passivation anti-reflection layer 72 and outside the doped polysilicon layer 6 , the second passivation anti-reflection layer 32 is formed outside the first passivation anti-reflection layer 31 .

[0063] Below through Fig. 9 and Fig.10 For the above Figure 8 The process shown is described in detail, wherein: Fig. 9 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S801; Fig.10 FIG. 4 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S802. Fig. 9 and Fig.10It can be seen that after step S801, a whole layer of the first passivation anti-reflection layer 31 is first deposited on the front side of the silicon substrate 1, and at the same time, a fourth passivation anti-reflection layer 72 arranged at both ends in the width direction of the silicon substrate 1 is formed by circumferential plating on the back side of the silicon substrate 1, and then after step S802, on the basis of the fourth passivation anti-reflection layer 72 having been formed, a third passivation anti-reflection layer 71 is prepared on the back side of the silicon substrate 1 and a second passivation anti-reflection layer 32 is formed by circumferential plating on the outside of the first passivation anti-reflection layer 31. Wherein, W1 represents the width of the second passivation anti-reflection layer 32, and W2 represents the width of the fourth passivation anti-reflection layer 72.

[0064] In another optional embodiment, when the passivation anti-reflection layer on the back side of the silicon substrate 1 is prepared first, step S503 can be as follows: Fig.11 As shown, including:

[0065] Step S1101, while preparing the third passivation anti-reflection layer 71 on the outside of the doped polysilicon layer 6, the second passivation anti-reflection layer 32 is formed on the outside of the emitter 2;

[0066] Step S1102 , while preparing the first passivation anti-reflection layer 31 outside the second passivation anti-reflection layer 32 and outside the emitter 2 , the fourth passivation anti-reflection layer 72 is formed outside the third passivation anti-reflection layer 71 .

[0067] Below through Fig.12 and Fig.13 For the above Fig.11 The process shown is described in detail, wherein: Fig.12 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S1101; Fig.13 FIG. 4 is a schematic diagram of the cross-sectional structure of the silicon substrate formed after step S1102. Fig.12 and Fig.13 It can be seen that after step S1101, a whole layer of the third passivation anti-reflection layer 71 is first deposited on the back side of the silicon substrate 1, and at the same time, a second passivation anti-reflection layer 32 arranged at both ends of the silicon substrate 1 in the width direction is formed on the front side of the silicon substrate 1 by circumferential plating, and then after step S1102, on the basis of the second passivation anti-reflection layer 32 having been formed, a first passivation anti-reflection layer 31 is prepared on the front side of the silicon substrate 1 and a fourth passivation anti-reflection layer 72 is formed by circumferential plating on the outside of the third passivation anti-reflection layer 71. Wherein, W1 represents the width of the second passivation anti-reflection layer 32, and W2 represents the width of the fourth passivation anti-reflection layer 72.

[0068] In an optional embodiment, in order to accurately control the width of the second passivation anti-reflection layer 32 and the fourth passivation anti-reflection layer 72 formed by wrap-around plating, the utility model embodiment sets the fitting distance between the silicon substrate 1 and the carrier at 80μm-400μm to prepare the first passivation anti-reflection structure 3 and the second passivation anti-reflection structure 7, for example, 80μm, 150μm, 200μm, 250μm, 300μm, 350μm, 400μm, etc., so that the width of the second passivation anti-reflection layer 32 and / or the fourth passivation anti-reflection layer 72 is 0.5mm~10mm.

[0069] In an optional embodiment, after step S503, the method further includes: preparing a first metal electrode 4 and a second metal electrode 8 on both sides of the silicon substrate 1 in the thickness direction. The silicon substrate structure obtained after preparing the metal electrodes is Figure 3 and Figure 4 The solar cell structure shown.

[0070] In summary, the method for preparing a solar cell provided by an embodiment of the utility model can effectively increase the thickness of the passivation anti-reflection layer at the edge of the silicon substrate, improve the passivation performance of the edge of the solar cell, and thereby increase the overall photoelectric conversion efficiency of the solar cell by preparing a first passivation anti-reflection structure including a first passivation anti-reflection layer and a second passivation anti-reflection layer on one side of the silicon substrate in the thickness direction, and preparing a second passivation anti-reflection structure including a third passivation anti-reflection layer and a fourth passivation anti-reflection layer on the other side of the silicon substrate in the thickness direction.

[0071] Embodiment 1

[0072] S1. The n-type silicon substrate is subjected to alkali texturing (the alkali solution is a sodium hydroxide solution with a volume concentration of 1%, the texturing temperature is 80°C, and the immersion time is 400s), and a velvet structure is formed on both sides of the silicon substrate in the thickness direction;

[0073] S2. Place the n-type silicon wafer with a velvet structure in a high-temperature diffusion furnace (reactants such as boron trichloride, boron tribromide and other boron-containing compounds and oxygen are mixed and reacted at a temperature of 1000°C for a reaction time of 3 hours) to perform a diffusion / oxidation process of the boron doping element to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of the boron element in the p+ emitter is 5E18atoms / cm3;

[0074] S3. Using a 30% volume concentration of hydrofluoric acid solution to remove the silicon glass layer formed by coating the back surface and side surfaces of the n-type silicon substrate;

[0075] S4. The positive surface of the n-type silicon substrate is polished with alkali solution (the alkali solution is a sodium hydroxide solution with a volume concentration of 2%, the reaction temperature is 60°C, and the immersion time is 200s);

[0076] S5. A tunneling oxide layer and an n+ doped polysilicon layer are sequentially prepared on the back surface of the n-type silicon substrate; wherein the tunneling oxide layer is a silicon oxide layer deposited by LPCVD, the reaction temperature is 600°C, the deposition time is 15 min, and the thickness is 2 nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0077] S6. Using hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphorus silicon glass layer coated on the front side of the n-type silicon substrate, the non-coated area on the front side, and the phosphorus silicon glass layer coated on the side;

[0078] S7. Cleaning the n-type silicon substrate (using RCA cleaning technology);

[0079] S8. A first passivation anti-reflection layer is deposited on the front side of the silicon substrate by ALD (atomic layer deposition) method at 320° C. and PECVD is used at 550° C., pressure 255 Pa, and RF power 10000 W, and a fourth passivation anti-reflection layer is simultaneously formed by plating on the back side of the silicon substrate, wherein the first passivation anti-reflection layer and the fourth passivation anti-reflection layer are both composite film layers of aluminum oxide (passivation layer) and silicon oxynitride (anti-reflection layer), with an overall thickness of 95 nm, and the width of the fourth passivation anti-reflection layer is 8 mm;

[0080] S9. Depositing a third passivation anti-reflection layer on the back side of the silicon substrate by PECVD at 550° C., a pressure of 255 Pa, and a radio frequency power of 10000 W, and simultaneously forming a second passivation anti-reflection layer on the front side of the silicon substrate by plating, wherein the second passivation anti-reflection layer and the third passivation anti-reflection layer are silicon oxynitride layers with an overall thickness of 100 nm, and the width of the second passivation anti-reflection layer is 8 mm;

[0081] S10. Prepare a first metal electrode and a second metal electrode on the front and back sides of the silicon substrate respectively by screen printing, wherein the first metal electrode penetrates the first passivation anti-reflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation anti-reflection layer and is electrically connected to the n+ doped polysilicon layer.

[0082] Embodiment 2

[0083] S1. The n-type silicon substrate is subjected to alkali texturing (the alkali solution is a sodium hydroxide solution with a volume concentration of 1%, the texturing temperature is 80°C, and the immersion time is 400s), and a velvet structure is formed on both sides of the silicon substrate in the thickness direction;

[0084] S2. Place the n-type silicon wafer with a velvet structure in a high-temperature diffusion furnace (reactants such as boron trichloride, boron tribromide and other boron-containing compounds and oxygen are mixed and reacted at a temperature of 1000°C for a reaction time of 3 hours) to perform a diffusion / oxidation process of the boron doping element to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of the boron element in the p+ emitter is 5E18atoms / cm3;

[0085] S3. Using a 30% volume concentration of hydrofluoric acid solution to remove the silicon glass layer formed by coating the back surface and side surfaces of the n-type silicon substrate;

[0086] S4. The positive surface of the n-type silicon substrate is polished with alkali solution (the alkali solution is a sodium hydroxide solution with a volume concentration of 2%, the reaction temperature is 60°C, and the immersion time is 200s);

[0087] S5. A tunneling oxide layer and an n+ doped polysilicon layer are sequentially prepared on the back surface of the n-type silicon substrate; wherein the tunneling oxide layer is a silicon oxide layer deposited by LPCVD, the reaction temperature is 600°C, the deposition time is 15 min, and the thickness is 2 nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0088] S6. Using hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphorus silicon glass layer coated on the front side of the n-type silicon substrate, the non-coated area on the front side, and the phosphorus silicon glass layer coated on the side;

[0089] S7. Cleaning the n-type silicon substrate (using RCA cleaning technology);

[0090] S8. A third passivation anti-reflection layer is deposited on the back side of the silicon substrate by ALD (atomic layer deposition) method at 320° C. and PECVD is used at 550° C., pressure 255 Pa, and RF power 10000 W, and a second passivation anti-reflection layer is formed by plating on the front side of the silicon substrate, wherein the third passivation anti-reflection layer and the second passivation anti-reflection layer are both composite film layers of aluminum oxide (passivation layer) and silicon oxynitride (anti-reflection layer), with an overall thickness of 95 nm, and the width of the second passivation anti-reflection layer is 8 mm;

[0091] S9. Depositing a first passivation anti-reflection layer on the front side of the silicon substrate by PECVD at 550° C., a pressure of 255 Pa, and a radio frequency power of 10000 W, and simultaneously forming a fourth passivation anti-reflection layer by plating on the back side of the silicon substrate, wherein the first passivation anti-reflection layer and the fourth passivation anti-reflection layer are silicon oxynitride layers with an overall thickness of 100 nm, and the width of the fourth passivation anti-reflection layer is 8 mm;

[0092] S10. Prepare a first metal electrode and a second metal electrode on the front and back sides of the silicon substrate respectively by screen printing, wherein the first metal electrode penetrates the first passivation anti-reflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation anti-reflection layer and is electrically connected to the n+ doped polysilicon layer.

[0093] Comparative Example 1

[0094] S1. The n-type silicon substrate is subjected to alkali texturing (the alkali solution is a sodium hydroxide solution with a volume concentration of 1%, the texturing temperature is 80°C, and the immersion time is 400s), and a velvet structure is formed on both sides of the silicon substrate in the thickness direction;

[0095] S2. Place the n-type silicon wafer with a velvet structure in a high-temperature diffusion furnace (reactants such as boron trichloride, boron tribromide and other boron-containing compounds and oxygen are mixed and reacted at a temperature of 1000°C for a reaction time of 3 hours) to perform a diffusion / oxidation process of the boron doping element to form a p+ emitter on the front surface of the n-type silicon substrate; wherein the doping concentration of the boron element in the p+ emitter is 5E18atoms / cm3;

[0096] S3. Using a 30% volume concentration of hydrofluoric acid solution to remove the silicon glass layer formed by coating the back surface and side surfaces of the n-type silicon substrate;

[0097] S4. The positive surface of the n-type silicon substrate is polished with alkali solution (the alkali solution is a sodium hydroxide solution with a volume concentration of 2%, the reaction temperature is 60°C, and the immersion time is 200s);

[0098] S5. A tunneling oxide layer and an n+ doped polysilicon layer are sequentially prepared on the back surface of the n-type silicon substrate; wherein the tunneling oxide layer is a silicon oxide layer deposited by LPCVD, the reaction temperature is 600°C, the deposition time is 15 min, and the thickness is 2 nm; the doping concentration of the n+ doped polysilicon layer is 4.5E20 atoms / cm3;

[0099] S6. Using hydrofluoric acid with a volume concentration of 10% to remove the boron + phosphorus silicon glass layer coated on the front side of the n-type silicon substrate, the non-coated area on the front side, and the phosphorus silicon glass layer coated on the side;

[0100] S7. Cleaning the n-type silicon substrate (using RCA cleaning technology);

[0101] S8. Depositing only a first passivation anti-reflection layer with a thickness of 95 nm on the front side of the silicon substrate by ALD (atomic layer deposition) at 320° C. and by PECVD at 550° C., pressure 255 Pa, and RF power 10,000 W, and depositing only a third passivation anti-reflection layer with a total thickness of 100 nm on the back side of the silicon substrate by PECVD at 550° C., pressure 255 Pa, and RF power 10,000 W;

[0102] S9. Prepare a first metal electrode and a second metal electrode on the front and back sides of the silicon substrate respectively by screen printing, wherein the first metal electrode penetrates the first passivation anti-reflection layer and is electrically connected to the p+ emitter, and the second metal electrode penetrates the third passivation anti-reflection layer and is electrically connected to the n+ doped polysilicon layer.

[0103] By performing performance tests on the solar cells prepared in the above embodiments and comparative examples, the performance comparison results shown in the following table were obtained:

[0104] Table 1

[0105]

[0106] It can be seen from Table 1 that the open circuit voltage (Voc) of the solar cells prepared in Example 1 and Example 2 is about 1 mV higher than that in Comparative Example 1, the fill factor (FF) of the solar cells prepared in Example 1 and Example 2 is about 0.1% higher than that in Comparative Example 1, the cell conversion efficiency (Eta) of the solar cells prepared in Example 1 and Example 2 is about 0.06% higher than that in Comparative Example 1, and the black edge defective ratio of the solar cells prepared in Example 1 and Example 2 is about 1% lower than that in Comparative Example 1.

[0107] At the same time, the solar cells prepared in the above-mentioned embodiment 1 and comparative example 1 are respectively subjected to PL (photoluminescence) detection, and the following results can be obtained: Fig.14 as well as Fig.15 The PL results shown are Fig.14 The PL result of the solar cell obtained in Example 1 is shown in FIG. Fig.15 The PL result of the solar cell obtained in Comparative Example 1 is shown in FIG. Fig.14 as well as Fig.15 It can be clearly seen that the black edge defect area in the edge region of the solar cell prepared in Example 1 of the utility model is significantly reduced.

[0108] From the above performance comparison results, it can be seen that by providing a first passivation anti-reflection structure including a first passivation anti-reflection layer and a second passivation anti-reflection layer, and a second passivation anti-reflection structure including a third passivation anti-reflection layer and a fourth passivation anti-reflection layer, the thickness of the passivation anti-reflection layer at the edge of the silicon substrate can be effectively increased, and the passivation performance of the edge of the solar cell can be improved, thereby increasing the overall photoelectric conversion efficiency of the solar cell.

[0109] The introduction provided in the above steps is only used to help understand the structure, method and core idea of ​​the utility model. For ordinary technicians in this technical field, the utility model can also be improved and modified without departing from the principle of the utility model, and these improvements and modifications also fall within the scope of protection of the claims of the utility model.

Claims

1. A solar cell, characterized in that: include: Silicon substrate (1); An emitter (2) and a first passivation anti-reflection structure (3) are arranged from inside to outside on one side in the thickness direction of the silicon substrate (1), wherein the first passivation anti-reflection structure (3) comprises a first passivation anti-reflection layer (31) and a second passivation anti-reflection layer (32), and the second passivation anti-reflection layer (32) is arranged in an edge region of the silicon substrate (1); A tunneling oxide layer (5), a doped polysilicon layer (6) and a second passivation anti-reflection structure (7) are arranged from inside to outside on the other side of the silicon substrate (1) in the thickness direction, wherein the second passivation anti-reflection structure (7) comprises a third passivation anti-reflection layer (71) and a fourth passivation anti-reflection layer (72), and the fourth passivation anti-reflection layer (72) is arranged in the edge region of the silicon substrate (1).

2. The solar cell according to claim 1, characterized in that: The first passivation anti-reflection layer (31) and the fourth passivation anti-reflection layer (72) are formed simultaneously, and the second passivation anti-reflection layer (32) and the third passivation anti-reflection layer (71) are formed simultaneously.

3. The solar cell according to claim 2, characterized in that: The fourth passivation anti-reflection layer (72) is formed by controlling the bonding distance between the silicon substrate (1) and the carrier, and is formed by plating when preparing the first passivation anti-reflection layer (31); The second passivation anti-reflection layer (32) is formed by controlling the bonding distance between the silicon substrate (1) and the carrier and by plating during the preparation of the third passivation anti-reflection layer (71).

4. The solar cell according to any one of claims 1 to 3, characterized in that: The second passivation anti-reflection layer (32) is arranged outside the first passivation anti-reflection layer (31); The fourth passivation anti-reflection layer (72) is arranged between the doped polysilicon layer (6) and the third passivation anti-reflection layer (71).

5. The solar cell according to any one of claims 1 to 3, characterized in that: The second passivation anti-reflection layer (32) is arranged between the first passivation anti-reflection layer (31) and the emitter (2); The fourth passivation anti-reflection layer (72) is arranged outside the third passivation anti-reflection layer (71).

6. The solar cell according to claim 1, characterized in that The width of the second passivation anti-reflection layer (32) is 0.5 mm to 10 mm; and / or, The width of the fourth passivation anti-reflection layer (72) is 0.5 mm to 10 mm.

7. The solar cell according to claim 1, characterized in that The first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) comprises at least one of the following: an aluminum oxide layer, a silicon oxide layer, a gallium oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer; and / or, The second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) comprises at least one of the following: an aluminum oxide layer, a silicon oxide layer, a gallium oxide layer, a silicon nitride layer, an aluminum nitride layer, and a silicon oxynitride layer.

8. The solar cell according to claim 1, characterized in that The thickness of the first passivation anti-reflection layer (31) and / or the fourth passivation anti-reflection layer (72) is 20 nm to 180 nm; and / or, The thickness of the second passivation anti-reflection layer (32) and / or the third passivation anti-reflection layer (71) is 25 nm to 200 nm.

9. The solar cell according to claim 1, characterized in that: The thickness of the tunnel oxide layer (5) is 0.5 nm to 5 nm; and / or, The thickness of the doped polysilicon layer (6) is 30 nm to 200 nm.

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