Half-bridge switching power supply and driving circuit thereof

Abstract

The utility model discloses a half-bridge switching power supply and a driving circuit thereof, and the driving circuit comprises a pair of driving control circuits which converts a pair of PWM signals into a pair of driving signals so as to control an upper power tube and a lower power tube respectively. The drive control circuit comprises: a signal processing circuit for performing signal processing on a PWM signal to obtain an intermediate signal; the level detection circuit detects the level state of the received intermediate signal and controls the working state of the signal processing circuit according to the level state; the driving signal generating circuit receives the intermediate signal so as to generate a driving signal according to the intermediate signal. The level detection circuit adjusts the transmission delay of the PWM signal in the signal processing circuit according to the level state so as to adjust the jump edge delay of the driving signal relative to the PWM signal, so that the conduction time of the upper power tube and the conduction time of the lower power tube are completely staggered, the dead zone time of the output driving signal cannot be shortened, and direct connection of the upper power tube and the lower power tube is avoided.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a half-bridge switching power supply and a driving circuit thereof. Background Art

[0002] A switching power supply is a power supply that uses a power tube to control the charging and discharging process of an energy storage element to provide power, and maintains a stable output voltage and / or output current by controlling the on and off time ratio of the power tube. Figure 1a shows a schematic diagram of a conventional half-bridge switching power supply and its half-bridge driving circuit, Figure 1b-1d Shows Figure 1a Partial waveform diagram of the half-bridge switching power supply. Figure 1a As shown, the switching power supply includes an upper power tube M1, a lower power tube M2 and a control circuit, and the control circuit includes a PWM controller 10 and a half-bridge drive circuit 20. The PWM controller 10 provides a PWM signal PWMH and a PWM signal PWML to the half-bridge drive circuit 20, and the half-bridge drive circuit 20 converts the PWMH signal and the PWML signal into a drive signal HO and a drive signal LO, respectively, to drive the upper power tube M1 and the lower power tube M2, respectively.

[0003] like Figure 1b As shown, in order to ensure that the upper power tube and the lower power tube are turned on alternately, the high level areas of the PWMH signal and the PWML signal do not overlap, and there is usually a dead time Td after one power tube is turned off and before the other power tube is turned on. During the dead time, both power tubes are turned off, thereby preventing the bridge arm from directly passing through and damaging the circuit, or the system power consumption is too large and the performance is reduced. However, the driving signal formed by the PWM signal after passing through the half-bridge driving circuit 20 will have a certain delay. Figure 1c , taking the PWMH signal as an example, after passing through the half-bridge drive circuit 20, it is output as a drive signal HO, the rising edge delay is Tond, and the falling edge delay is Toffd. The rising edge delay and the falling edge delay may be equal or unequal. In practical applications, it is generally required that the rising edge delay Tond and the falling edge delay Toffd are consistent, so that the input dead time and the output dead time after passing through the half-bridge drive circuit are equal to avoid the risk of direct pass. However, the rising edge delay and the falling edge delay of the PWM signal in circuit transmission are currently determined by the circuit structure or the characteristics of the device itself. There is a certain offset in the circuit parameters of different chip individuals, so it is difficult to ensure that different chips can meet the signal rising edge delay and falling edge delay. There may even be a situation where the rising edge delay is shorter than the falling edge delay, such as Figure 1d, the dead time of PWMH signal and PWML signal is Td1, the rising edge delay Tond of PWMH (or PWML) signal converted into HO signal (or LO signal) is less than the falling edge delay Toffd, then the dead time Td2 of HO signal and LO signal is very small, and even there may be no dead time, which may easily cause the risk of direct conduction of upper power tube and lower power tube, resulting in poor circuit effect. Utility Model Content

[0004] In order to solve the above technical problems, the present application provides a half-bridge switching power supply and a driving circuit thereof to solve the problems in the prior art.

[0005] According to one aspect of the utility model, a driving circuit of a half-bridge switching power supply is provided, comprising a pair of driving control circuits, which convert a pair of PWM signals into a pair of driving signals to respectively control an upper power tube and a lower power tube of the switching power supply, wherein the driving control circuit comprises:

[0006] A signal processing circuit performs signal processing on the PWM signal to obtain an intermediate signal;

[0007] a level detection circuit, detecting a level state of the received intermediate signal, and controlling a working state of the signal processing circuit according to the level state; and

[0008] a driving signal generating circuit, receiving the intermediate signal to generate the driving signal accordingly,

[0009] Among them, the level detection circuit adjusts the transmission delay of the PWM signal in the signal processing circuit according to the level state, so as to adjust the delay of the driving signal relative to the jump edge of the PWM signal, so that the conduction time of the upper power tube and the conduction time of the lower power tube are completely staggered.

[0010] Optionally, the transition edge includes a rising edge and a falling edge, and the level detection circuit adjusts the transmission delay according to the level state so that the rising edge delay of the drive signal relative to the PWM signal is greater than the falling edge delay.

[0011] Optionally, the level state includes a low level and a high level. When the level detection circuit detects that the intermediate signal is at a low level, it increases the transmission delay of the PWM signal, so that the delay of the driving signal relative to the rising edge of the PWM signal increases, and / or, when the level detection circuit detects that the intermediate signal is at a high level, it reduces the transmission delay of the PWM signal, so that the delay of the driving signal relative to the falling edge of the PWM signal decreases.

[0012] Optionally, the signal processing circuit includes a filtering circuit and a signal shaping circuit, the level detection circuit adjusts the transmission time of the PWM signal in the filtering circuit according to the level state to adjust the transmission delay, and / or the level detection circuit adjusts the level jump speed in the signal shaping circuit according to the level state to adjust the transmission delay.

[0013] Optionally, the filtering circuit includes a filtering network, and the level detection circuit adjusts the impedance and / or capacitance of the filtering network according to the level state to adjust the transmission time of the PWM signal in the filtering circuit, the transmission time increases when the impedance increases, and the transmission time decreases when the impedance decreases; the transmission time increases when the capacitance increases, and the transmission time decreases when the capacitance decreases.

[0014] Optionally, the filtering circuit includes a filtering network and a transmission control unit, the transmission control unit is used to adjust the transmission delay of the filtering network, and the level detection circuit controls the transmission control unit to establish or disconnect the circuit connection with the filtering network according to the level state.

[0015] Optionally, the transmission control unit is connected to the input end of the filter network, or is connected between the filter network and the signal shaping circuit, and the transmission control unit includes a resistor, an even number of inverters connected in series, an even number of NOT gates connected in series, a buffer or a delay device;

[0016] When the level detection circuit detects that the intermediate signal is at a low level, the level detection circuit controls the transmission control unit to establish a connection with the filter network; when the level detection circuit detects that the intermediate signal is at a high level, the level detection circuit controls the transmission control unit to disconnect from the filter network.

[0017] Optionally, the signal shaping circuit includes:

[0018] A transition detection circuit detects the flipping moment of the level state of the PWM signal to generate a corresponding transition edge;

[0019] Wherein, the level detection circuit adjusts the speed at which the transition detection circuit generates the transition edge according to the level state.

[0020] Optionally, the transition detection circuit includes a comparator and a bias current source, the bias current source provides a bias current for the comparator, and the comparator outputs the transition edge;

[0021] After the level state changes from a high level to a low level, the level detection circuit controls the bias current to decrease, and after the level state changes from a low level to a high level, the level detection circuit controls the bias current to increase.

[0022] The utility model also provides a half-bridge switching power supply, comprising an upper power tube and a lower power tube, characterized in that the switching power supply further comprises:

[0023] A PWM controller provides a pair of PWM signals; and

[0024] According to the driving circuit described above, the driving circuit outputs a pair of driving signals according to a pair of PWM signals to respectively control the upper power tube and the lower power tube of the switching power supply.

[0025] The beneficial effects of the utility model include at least:

[0026] The utility model provides a half-bridge switching power supply and a driving circuit thereof, wherein a signal processing circuit processes a PWM signal into an intermediate signal, and a level detection circuit detects the level state of the intermediate signal, thereby adjusting the transmission delay of the PWM signal in the signal processing circuit according to the level state, so as to adjust the transmission delay of the driving signal outputted finally relative to the transition edge of the PWM signal. The length of the dead time is ensured by controlling the transmission delay of the transition edge of the driving signal, so that the rising edge delay of the driving signal relative to the PWM signal is greater than the falling edge delay, so that the conduction time of the upper power tube and the conduction time of the lower power tube are completely staggered, thereby avoiding the risk caused by the direct conduction of the upper power tube and the lower power tube, and improving reliability.

[0027] Furthermore, when the level state of the intermediate signal is low, the transmission delay of the PWM signal is increased to delay the output of the rising edge of the drive signal, or, when the level state of the intermediate signal is high, the transmission delay of the PWM signal is reduced to advance the output of the falling edge of the drive signal. Alternatively, the rising edge delay output and the falling edge advance output exist simultaneously, so that the pulse width of the output drive signal is slightly reduced, ensuring that the dead time of the drive signal formed after the PWM signal passes through the drive circuit will not be shortened, thereby ensuring that the upper and lower power tubes of the half-bridge will not be directly connected, thereby improving the reliability of the system.

[0028] Furthermore, the signal processing circuit includes a filter circuit and a signal shaping circuit, and the level detection circuit separately adjusts the transmission time of the PWM signal in the filter circuit according to the level state to adjust the transmission delay, or the level detection circuit separately adjusts the level jump speed in the signal shaping circuit according to the level state to adjust the transmission delay, thereby expanding the possibility of circuit implementation and expanding the use scenarios and application scope of the drive circuit. Of course, the transmission time and jump speed of the PWM signal can also be adjusted at the same time to further ensure that the upper and lower power tubes will not pass directly.

[0029] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a A schematic diagram of a conventional half-bridge switching power supply and a half-bridge driving circuit thereof is shown;

[0031] Figure 1b-1d Shows Figure 1a Schematic diagram of some waveforms of a half-bridge switching power supply;

[0032] Figure 2 A schematic diagram of a half-bridge switching power supply and a driving circuit thereof according to an embodiment of the utility model is shown;

[0033] Figure 3 A schematic block diagram of a drive control circuit according to a first embodiment of the present utility model is shown;

[0034] Figure 4a and Figure 4b They are shown respectively Figure 3 Schematic circuit diagrams of two different structures of filter circuits in a drive control circuit;

[0035] Figure 5 shows a schematic block diagram of a drive control circuit according to a second embodiment of the utility model;

[0036] Figure 6 Shows Figure 5 A schematic circuit diagram of a signal shaping circuit in a drive control circuit;

[0037] Figure 7 shows a schematic block diagram of a drive control circuit according to a third embodiment of the present utility model;

[0038] Figure 8 A schematic diagram of signal waveforms of a driving circuit according to an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0039] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively with reference to the relevant drawings. The drawings provide preferred embodiments of the present invention. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0040] Figure 2 A schematic diagram of a half-bridge switching power supply and a driving circuit thereof according to an embodiment of the utility model is shown.

[0041] like Figure 2As shown, the half-bridge switching power supply of this embodiment includes an upper power tube M1, a lower power tube M2 and a control circuit. The upper power tube M1 and the lower power tube M2 are connected in series between an input terminal and a ground terminal. The input terminal receives an input voltage Vin. The common node of the upper power tube M1 and the lower power tube M2 generates a node voltage HS. The common node is connected to an energy storage element to provide energy for the subsequent stage. The energy storage element is, for example, an inductor. The control circuit includes a PWM controller 10 and a half-bridge drive circuit 20 and other circuit modules, such as an overvoltage protection circuit, a zero-crossing detection circuit and an over-temperature protection circuit. The PWM controller 10 is used to generate a pair of PWM signals with opposite level states, and provide a PWM signal PWMH and a PWM signal PWML to the half-bridge drive circuit 20. The half-bridge drive circuit 20 converts the PWMH signal and the PWML signal into a drive signal HO and a drive signal LO respectively, so as to drive the upper power tube M1 and the lower power tube M2 respectively.

[0042] The driving circuit 20 of this embodiment includes a pair of driving control circuits to convert a pair of PWM signals (PWMH signal and PWML signal) into a pair of driving signals (HO signal and LO signal) to control the upper power tube M1 and the lower power tube M2 of the switching power supply respectively. Specifically, the driving circuit 20 includes an upper driving control circuit 100 and a lower driving control circuit 200. The upper driving control circuit 100 converts the PWM signal PWMH into the upper driving signal HO, and the lower driving control circuit 200 converts the PWM signal PWML into the lower driving signal LO. The waveform diagrams of the PWMH signal and the PWML signal can be referred to. Figure 1b , there is a set dead time Td between the two. The upper drive control circuit 100 and the lower drive control circuit 200 can be exactly the same, that is, the circuit structure and working principle inside the two can be exactly the same. The upper drive control circuit 100 includes a signal processing circuit 110, a drive signal generating circuit 120 and a level detection circuit 130, then the lower drive control circuit 200 also includes a signal processing circuit 210, a drive signal generating circuit 220 and a level detection circuit 230. Since the upper drive control circuit 100 and the lower drive control circuit 200 can be exactly the same, this embodiment can only introduce one of the drive control circuits, for example, the upper drive control circuit 100 is used as an example in the following description.

[0043] exist Figure 2In the embodiment, the upper driving control circuit 100 is connected between one of the input terminals and one of the output terminals of the driving circuit 20, and the signal processing circuit 110 is connected to the input terminal, receives the PWMH signal, and performs signal processing on it to obtain the intermediate signal PHI, and the signal processing includes, for example, filtering and shaping. The intermediate signal can be regarded as a delayed signal of the corresponding PWM signal. The driving signal generating circuit 120 is connected between the signal processing circuit 110 and the output terminal, receives the intermediate signal PHI and processes it to obtain the driving signal HO and output it, for example, amplifies it, and the amplification process may include amplifying the current or amplifying the voltage. The level detection circuit 130 is used to detect the level state of the received intermediate signal PHI, and control the working state of the signal processing circuit 110 according to the level state. The level detection circuit 130 specifically adjusts the transmission delay of the PWMH signal in the signal processing circuit 110 according to the level state, so as to adjust the jump edge delay between the driving signal HO and the PWMH signal, so that the conduction time of the upper power tube M1 and the conduction time of the lower power tube M2 are completely staggered. Furthermore, the transition edge includes a rising edge and a falling edge. The level detection circuit 130, for example, adjusts the transmission delay of the PWMH signal in the signal processing circuit 110 according to the level state, so that the rising edge delay between the generated drive signal HO and the PWMH signal is greater than the falling edge delay. Since the upper drive control circuit 100 and the lower drive control circuit 200 are exactly the same, the level detection circuit 230 also adjusts the transmission delay of the PWML signal in the signal processing circuit 210 according to the level state of the intermediate signal PLI, so that the rising edge delay between the generated drive signal LO and the PWMH signal is greater than the falling edge delay. Thus, the high level areas of the generated drive signal HO and the drive signal LO will not overlap, and have a certain dead time, ensuring that the upper power tube M1 and the lower power tube M2 will not be directly connected.

[0044] Specifically, in this embodiment, the transition edge includes a rising edge and a falling edge, and the level detection circuit 130 can, for example, adjust the transmission time of the PWMH signal in the signal processing circuit 110 according to the level state of the intermediate signal PHI to adjust the transmission delay. The signal processing of the PWM signal by the signal processing circuit 110 may include signal filtering and signal shaping, etc., and the signal processing circuit 110 may include a filtering circuit and a signal shaping circuit. Then, the level detection circuit 130 can adjust the filtering time of the PWMH signal in the filtering circuit according to the level state of the intermediate signal PHI, or adjust the transition speed of the level in the signal shaping circuit, or simultaneously adjust the filtering time and the transition speed of the level of the PWMH signal to adjust the transmission delay.

[0045] Further, the level state includes a low level and a high level. The level detection circuit 130 can increase the transmission delay of the signal processing circuit 110 when detecting that the intermediate signal PHI is at a low level, so that the rising edge delay between the drive signal HO and the PWMH signal increases, so that the rising edge delay is greater than the falling edge delay (the falling edge delay can be regarded as the delay in the initial state of the signal processing circuit, that is, the delay when the intermediate signal is at a high level). Alternatively, the level detection circuit 130 can reduce the transmission delay of the signal processing circuit 110 when detecting that the intermediate signal PHI is at a high level, so that the falling edge delay between the drive signal HO and the PWMH signal is reduced, so that the rising edge delay is greater than the falling edge delay (the rising edge delay can be regarded as the delay in the initial state of the signal processing circuit, that is, the delay when the intermediate signal is at a low level). Alternatively, the level detection circuit 130 may also increase the transmission delay of the signal processing circuit 110 when the intermediate signal PHI is detected to be at a low level, and reduce the transmission delay of the signal processing circuit 110 when the intermediate signal PHI is detected to be at a high level, further ensuring that the rising edge delay is greater than the falling edge delay (the increase in the rising edge delay and the reduction in the falling edge delay are relative to the delay in the initial state of the signal processing circuit). The following is an introduction in combination with different embodiments.

[0046] Figure 3 A schematic block diagram of a drive control circuit according to a first embodiment of the utility model is shown.

[0047] like Figure 3 As shown, taking the above drive control circuit 100 as an example, the signal processing circuit 110 includes a filter circuit 111 and a signal shaping circuit 112. As one of the examples in this article, the drive signal generating circuit 120 includes a level shift circuit 121 and a totem pole drive circuit 122. The filter circuit 111 is used to filter the PWMH signal to reduce interference, and the signal shaping circuit 112 is used to shape the filtered PWMH signal so that the signal waveform is more consistent with the shape of the square wave. The level shift circuit 121 is used to perform potential matching so that the output drive signal HO can drive the main power tube M1, and the totem pole drive circuit 122 is used to match the current size of the drive signal. For example, a smaller current can be used to amplify through the totem pole drive circuit 122 to drive the main power tube M1 to work.

[0048] The level detection circuit 130 can, for example, adjust the transmission time (i.e., filtering time) of the PWMH signal in the filter circuit 111 according to the level state of the intermediate signal PHI to adjust the transmission delay. Alternatively, the level detection circuit 130 can adjust the transition speed of the transition edge of the level in the signal shaping circuit 112 according to the level state of the intermediate signal PHI to adjust the transmission delay. Alternatively, the level detection circuit 130 simultaneously adjusts the transmission time of the PWMH signal in the filter circuit 111 and the transition speed of the transition edge of the level in the signal shaping circuit 112 according to the level state of the intermediate signal PHI to adjust the transmission delay. In this embodiment, the example of the level detection circuit 130 adjusting the transmission time of the PWMH signal in the filter circuit 111 according to the level state of the intermediate signal PHI to adjust the transmission delay is used for explanation.

[0049] Specifically, see Figure 3 , the level detection circuit 130 can actively adjust the filtering parameters of the filter circuit 111 according to the state of the intermediate signal PHI. For example, when the current intermediate signal PHI is detected to be at a low level, the transmission time of the PWMH signal in the filter circuit 111 is extended, so that the transmission delay between the rising edge of the PWMH signal and the rising edge of the intermediate signal PHI becomes longer, that is, the rising edge delay is increased. Alternatively, the level detection circuit 130 can also reduce the transmission time of the PWMH signal in the filter circuit 111 when the current intermediate signal PHI is detected to be at a high level, so that the transmission delay between the falling edge of the PWMH signal and the falling edge of the intermediate signal PHI becomes shorter, that is, the falling edge delay is reduced. Alternatively, when the level detection circuit 130 detects that the current intermediate signal PHI is at a low level, the transmission time of the PWMH signal in the filter circuit 111 is extended, and when the current intermediate signal PHI is detected to be at a high level, the transmission time of the PWMH signal in the filter circuit 111 is reduced, so as to simultaneously increase the rising edge delay and reduce the falling edge delay, so as to avoid the upper power tube M1 and the lower power tube M2 being directly connected.

[0050] Figure 4a and Figure 4b They are shown respectively Figure 3 Schematic circuit diagram of two different structures of the filter circuit in the drive control circuit.

[0051] like Figure 4aAs shown, the filter circuit 111 includes a filter network, which may be an RC filter network or an LC filter network, and may include a single-stage filter network or a multi-stage series filter network. Here, a single-stage RC filter network is taken as an example, and the filter network includes a resistor R1 and a capacitor C1. The level detection circuit 130 can adjust the impedance and / or capacitance of the filter network according to the level state of the intermediate signal PHI to adjust the transmission time of the PWMH signal in the filter circuit. The transmission time is related to the impedance and capacitance. When the impedance is large, the transmission time is also large (i.e., the filtering time is long), and when the capacitance is large, the transmission time is also large (i.e., the filtering time is long). For example, the resistance of the resistor R1 can be adjusted, or the resistance of the resistor R1 can be adjusted by other components to adjust the transmission time of the PWMH signal in the filter circuit. When the resistance increases, the transmission time of the signal in the filter network will increase. Then, when the intermediate signal PHI is detected to be at a low level, the resistance of the resistor R1 is increased, so that when the PWMH signal changes from a low level to a high level, the rising edge needs more time to pass through the filter network, thereby increasing the rising edge delay. On the contrary, when the intermediate signal PHI is detected as a high level, the resistance of the resistor R1 is reduced, so that when the PWMH signal changes from a high level to a low level, the falling edge takes less time to pass through the filter network, thereby reducing the falling edge delay. Then, the resistance of the resistor R1 can be increased when the intermediate signal PHI is detected as a low level, and the resistance of the resistor R1 is not adjusted when the intermediate signal PHI is detected as a high level. It is also possible to reduce the resistance of the resistor R1 when the intermediate signal PHI is detected as a high level, and not adjust the resistance of the resistor R1 when the intermediate signal PHI is detected as a low level. It is also possible to increase the resistance of the resistor R1 when the intermediate signal PHI is detected as a low level, and reduce the resistance of the resistor R1 when the intermediate signal PHI is detected as a high level.

[0052] Similarly, the capacitance of capacitor C1 can be adjusted, or the capacitance of capacitor C1 can be adjusted equivalently by other components to adjust the transmission time of the PWMH signal in the filter circuit, which will not be introduced in detail here. Among them, the equivalent impedance of resistor R1 can be formed by connecting resistors and switches, and the impedance of resistor R1 can be adjusted by controlling the state of the switch. The specific number of resistors and switches can be set according to actual applications. Similarly, capacitors and switches can be set to form the equivalent capacitance of capacitor C1, and the specific number of capacitors and switches can be set according to actual needs.

[0053] Further, in some other embodiments, the filter circuit 111 includes a filter network and a transmission control unit 1111, and the transmission control unit 1111 can adjust the filtering time of the PWM signal in the filter network, for example, increase the filtering time. The filter network can still include a single-stage or multi-stage RC network or LC network, and a single-stage RC network is taken as an example here. The level detection circuit 130 can control the transmission control unit 1111 to establish a circuit connection or disconnect the circuit connection with the filter network according to the level state of the intermediate signal PHI. Specifically, when the level detection circuit 130 detects that the intermediate signal PHI is at a low level, the transmission control unit 1111 is controlled to establish a connection with the filter network, and when the intermediate signal PHI is detected to be at a high level, the transmission control unit 1111 is controlled to disconnect from the filter network.

[0054] When the transmission control unit 1111 is connected to the input end of the filter network, or connected between the output end of the filter network and the signal shaping circuit 112, that is, when the transmission control unit 1111 is connected to the path where the resistor R1 and the signal shaping circuit 112 are located, the transmission control unit 1111 may include a resistor, an even number of inverters connected in series, an even number of NOT gates connected in series, a buffer or a delay device, etc. The even number of inverters or the even number of NOT gates are, for example, multiple inverters or NOT gates connected in series end to end. Figure 4a , the transmission control unit 1111 may include a resistor R2, which is connected before or after the resistor R1, and the switch S1 is connected in parallel at both ends of the resistor R2. When the level detection circuit 130 detects that the intermediate signal PHI is at a low level, the switch S1 is disconnected, and the resistor R2 is connected in the circuit, that is, the transmission control unit 1111 is connected to the filter network to increase the transmission delay; and when the intermediate signal PHI is detected to be at a high level, the switch S1 is closed, and the resistor R2 is short-circuited, which is equivalent to disconnecting the circuit connection between the transmission control unit 1111 and the filter network, and will not affect the falling edge delay. However, the rising edge delay is still greater than the falling edge delay, which avoids the direct connection of the upper and lower power tubes. Figure 4a This is just an example of changing the impedance of the filter network. Other variations can be made to set the impedance under different intermediate signal states to achieve the same function.

[0055] In another embodiment, one end of the transmission control unit 1111 is connected to the filter network, and the other end is connected to the reference ground. Figure 4b, the transmission control unit 1111 is connected to both ends of the capacitor C1 to equivalently adjust the capacitance of the capacitor C1 to adjust the transmission time of the PWMH signal in the filter circuit. When the capacitance increases, the transmission time of the signal increases, so that when the PWMH signal changes from a low level to a high level, the capacitance increases, and the rising edge requires more time to pass through the filter network, increasing the rising edge delay. Conversely, when the capacitance decreases, the transmission time of the signal decreases, and when the PWMH signal changes from a high level to a low level, the capacitance decreases, and the falling edge requires less time to pass through the filter network, thereby reducing the falling edge delay. Then, the capacitance of the capacitor C1 can be increased only when the intermediate signal PHI is detected to be a low level, or the capacitance of the capacitor C1 can be reduced only when the intermediate signal PHI is detected to be a high level. It is also possible to increase the capacitance of the capacitor C1 when the intermediate signal PHI is detected to be a low level, and reduce the capacitance of the capacitor C1 when the intermediate signal PHI is detected to be a high level. The transmission control unit 1111 includes an energy storage element, and the energy storage element, for example, includes at least one capacitor. In Figure 4b In the embodiment, the transmission control unit 1111 includes a capacitor C2, which is connected to both ends of the capacitor C1, and a switch S2 is connected in series with the capacitor C2. When the level detection circuit 130 detects that the intermediate signal PHI is at a low level, the switch S2 is closed, and the capacitor C2 is connected in the circuit, that is, the transmission control unit 1111 is connected to the filter network, increasing the transmission delay; and when the intermediate signal PHI is detected to be at a high level, the switch S2 is disconnected, and the capacitor C2 is disconnected from the RC network, which is equivalent to disconnecting the circuit connection between the transmission control unit 1111 and the filter network, and will not affect the falling edge delay. However, the rising edge delay is still greater than the falling edge delay, which avoids the direct connection of the upper and lower power tubes.

[0056] Figure 5 A schematic block diagram of a drive control circuit according to a second embodiment of the utility model is shown.

[0057] like Figure 5 As shown, in this embodiment, the signal processing circuit 110 includes a filter circuit 111 and a signal shaping circuit 112, and the drive signal generating circuit 120 includes a level shift circuit 121 and a totem pole driving circuit 122. The level detection circuit 130 separately adjusts the transition speed of the level transition edge in the signal shaping circuit 112 according to the level state of the intermediate signal PHI to adjust the transmission delay as an example for description. Figure 5 and Figure 3 The similarities will not be repeated here.

[0058] Figure 6 Shows Figure 5 Schematic circuit diagram of the signal shaping circuit in the drive control circuit.

[0059] like Figure 6As shown, the signal shaping circuit 112 includes a transition detection circuit 1121 and an edge shaping circuit 1122. The transition detection circuit 1121 detects the flipping moment of the level state of the filtered PWMH signal to generate a corresponding transition edge, and the edge shaping circuit 1122 shapes the waveform of the generated transition edge. The level detection circuit 130 adjusts the speed at which the transition detection circuit 1121 generates the transition edge according to the level state of the intermediate signal PHI. In one embodiment, the transition detection circuit 1121 includes a comparator U1 and a bias current source A1 and a bias current source A2. The bias current sources A1 and A2 provide bias currents for the comparator U1, and the comparator U1 outputs a transition edge. The positive input terminal of the comparator U1 is, for example, connected to the filter circuit 111, and the negative input terminal receives the reference voltage Vref. When the rising edge of the PWMH signal is detected, the output of the comparator U1 is changed from a low level to a high level, that is, a corresponding rising edge is generated, and when the falling edge of the PWMH signal is detected, the output of the comparator U1 is changed from a high level to a low level, that is, a corresponding falling edge is generated. The speed at which the comparator U1 generates a rising edge or a falling edge can be adjusted by adjusting the magnitude of the bias current provided by the bias current source. The edge shaping circuit 1122 performs signal shaping on the generated rising edge and falling edge to make it more consistent with the waveform of the PWMH signal. The comparator U1 in this embodiment can, for example, be a hysteresis comparator.

[0060] Specifically, the level detection circuit 130 can adjust the magnitude of the bias current provided by the bias current source according to the level state of the intermediate signal PHI to adjust the jump speed of the comparator U1 in the signal shaping circuit 112. When the level state is a low level, the level detection circuit 130 controls the bias current to decrease, and when the level state is a high level, the level detection circuit 130 controls the bias current to increase (the increase or decrease of the bias current is relative to the previous state of the bias current). For example, a switch S3 can be connected in series with the bias current source A2, and the level detection circuit 130 controls the on and off of the switch S3 according to the level state of the intermediate signal PHI. When the level state of the intermediate signal PHI is a low level, the level detection circuit 130 controls the switch S3 to be disconnected, and the bias current provided is reduced. When the level state is a high level, the level detection circuit 130 controls the switch S3 to be closed, and the bias current is larger than when the switch S3 is disconnected. It is also possible to set three or even more bias current sources. When the intermediate signal PHI is detected to be at a low level, one bias current source can provide current. When the intermediate signal PHI is detected to be at a high level, three bias current sources can provide current together. Similar situations are not described here one by one. Of course, the bias current sources A1 and A2 can also be replaced by the voltage-controlled current source I1. The level detection circuit 130 adjusts the magnitude of the control voltage received by the voltage-controlled current source I1 according to the level state of the intermediate signal PHI to adjust the bias current. Of course, other circuit elements can also be used to adjust the bias current, which are not introduced here one by one.

[0061] Then this embodiment can actively adjust the level flip speed of the comparator U1 output signal according to the level state of the intermediate signal PHI. When the intermediate signal PHI is detected to be at a low level, the bias current of the comparator U1 is reduced, so that the speed at which the signal output by the comparator U1 jumps from a low level to a high level is slowed down. When the intermediate signal PHI is detected to be at a high level, the bias current of the comparator U1 is increased, so that the speed at which the signal output by the comparator U1 jumps from a high level to a high level is accelerated. Thereby, the rising edge delay is greater than the falling edge delay, avoiding the upper and lower power tubes from directly connecting to damage the circuit.

[0062] Figure 7 A schematic block diagram of a drive control circuit according to a third embodiment of the present utility model is shown.

[0063] like Figure 7 As shown, the signal processing circuit 110 of this embodiment includes a filter circuit 111 and a signal shaping circuit 112, and in this embodiment, the level detection circuit 130 adjusts the transmission time of the PWMH signal in the filter circuit 111 according to the level state of the intermediate signal PHI to adjust the transmission delay. At the same time, the level detection circuit 130 also adjusts the level jump speed in the signal shaping circuit 112 according to the level state of the intermediate signal PHI to adjust the transmission delay. This embodiment can be a combination of the first embodiment and the second embodiment, that is, Figure 4a or Figure 4b The filter circuit 111 and Figure 6 Substitute the signal shaping circuit 112 into Figure 7 In , similar control is implemented to make the rising edge delay greater than the falling edge delay.

[0064] Figure 8 A schematic diagram of signal waveforms of a driving circuit according to an embodiment of the utility model is shown.

[0065] like Figure 8As shown, the utility model actively controls the transmission delay of the rising edge and falling edge of the PWMH signal and the PWML signal during the circuit transmission process, so that the rising edge delay is greater than the falling edge delay. Specifically, take the dead time Td1 of the PWMH signal and the PWML signal generated by the PWM controller 10 as an example (of course, the dead time can also be set in other ways, for example, the rising edge delay and the falling edge delay can be the same or different). After passing through the drive circuit 20 of this embodiment, the rising edge delay Tond of the drive signal HO relative to the PWMH signal is slightly greater than the falling edge delay Toffd, and similarly, the rising edge delay Tond of the drive signal LO relative to the PWML signal is slightly greater than the falling edge delay Toffd. Therefore, after the PWMH signal and the PWML signal pass through the drive circuit 20, the dead time Td2 of the drive signal HO and the drive signal LO generated is slightly increased relative to Td1, and the pulse width of the drive signal HO and the drive signal LO is slightly reduced. That is, the high level regions of the driving signal HO and the driving signal LO do not overlap at all, so that the conduction time of the upper power tube M1 and the lower power tube M2 can be completely staggered, and there is no risk of direct conduction between the upper power tube M1 and the lower power tube M2.

[0066] Figure 3-Figure 7 Only several possible forms of the upper drive control circuit 100 of the utility model are shown. In other embodiments, other components and circuit modules can also be used to form the upper drive control circuit 100 and the lower drive control circuit 200 to achieve the above functions, which are not listed one by one here.

[0067] In summary, the half-bridge switching power supply and its driving circuit provided by the utility model processes the PWM signal into an intermediate signal by the signal processing circuit, and the level detection circuit detects the level state of the intermediate signal, thereby adjusting the transmission delay of the PWM signal in the signal processing circuit according to the level state, so as to adjust the transmission delay of the final output drive signal relative to the transition edge of the PWM signal. The length of the dead time is ensured by the transmission delay of the transition edge, so that the conduction time of the upper power tube and the conduction time of the lower power tube are completely staggered, thereby avoiding the risk caused by the direct conduction of the upper power tube and the lower power tube, and improving reliability.

[0068] Furthermore, when the level state of the intermediate signal is low, the transmission delay of the PWM signal is increased to delay the output of the rising edge of the drive signal, or, when the level state of the intermediate signal is high, the transmission delay of the PWM signal is reduced to advance the output of the falling edge of the drive signal. Alternatively, the rising edge delay output and the falling edge advance output exist simultaneously, so that the pulse width of the output drive signal is slightly reduced, ensuring that the dead time of the drive signal formed after the PWM signal passes through the drive circuit will not be shortened, thereby ensuring that the upper and lower power tubes of the half-bridge will not be directly connected, thereby improving the reliability of the system.

[0069] Furthermore, the signal processing circuit includes a filter circuit and a signal shaping circuit, and the level detection circuit separately adjusts the transmission time of the PWM signal in the filter circuit according to the level state to adjust the transmission delay, or the level detection circuit separately adjusts the level jump speed in the signal shaping circuit according to the level state to adjust the transmission delay, thereby expanding the possibility of circuit implementation and expanding the use scenarios and application scope of the drive circuit. Of course, the transmission time and jump speed of the PWM signal can also be adjusted at the same time to further ensure that the upper and lower power tubes will not pass directly.

[0070] It should be noted that the numerical values ​​in this article are only used for exemplary description. In other embodiments of the present invention, other numerical values ​​can also be sampled to implement this solution. The specific settings should be reasonable according to the actual situation, and the present invention does not limit this.

[0071] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

[0072] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. A driving circuit of a half-bridge switching power supply, comprising a pair of driving control circuits, which convert a pair of PWM signals into a pair of driving signals to respectively control an upper power tube and a lower power tube of the switching power supply, characterized in that: The drive control circuit comprises: A signal processing circuit performs signal processing on the PWM signal to obtain an intermediate signal; a level detection circuit, detecting a level state of the received intermediate signal, and controlling a working state of the signal processing circuit according to the level state; and a driving signal generating circuit, receiving the intermediate signal to generate the driving signal accordingly, Among them, the level detection circuit adjusts the transmission delay of the PWM signal in the signal processing circuit according to the level state, so as to adjust the delay of the driving signal relative to the jump edge of the PWM signal, so that the conduction time of the upper power tube and the conduction time of the lower power tube are completely staggered.

2. The driving circuit according to claim 1, characterized in that: The transition edge includes a rising edge and a falling edge, and the level detection circuit adjusts the transmission delay according to the level state so that the rising edge delay of the drive signal relative to the PWM signal is greater than the falling edge delay.

3. The driving circuit according to claim 2, characterized in that: The level state includes a low level and a high level. When the level detection circuit detects that the intermediate signal is at a low level, it increases the transmission delay of the PWM signal, so that the delay of the driving signal relative to the rising edge of the PWM signal increases, and / or, when the level detection circuit detects that the intermediate signal is at a high level, it reduces the transmission delay of the PWM signal, so that the delay of the driving signal relative to the falling edge of the PWM signal decreases.

4. The driving circuit according to claim 1, characterized in that: The signal processing circuit includes a filtering circuit and a signal shaping circuit. The level detection circuit adjusts the transmission time of the PWM signal in the filtering circuit according to the level state to adjust the transmission delay, and / or the level detection circuit adjusts the level jump speed in the signal shaping circuit according to the level state to adjust the transmission delay.

5. The driving circuit according to claim 4, characterized in that: The filtering circuit includes a filtering network. The level detection circuit adjusts the impedance and / or capacitance of the filtering network according to the level state to adjust the transmission time of the PWM signal in the filtering circuit. When the impedance increases, the transmission time increases, and when the impedance decreases, the transmission time decreases; when the capacitance increases, the transmission time increases, and when the capacitance decreases, the transmission time decreases.

6. The driving circuit according to claim 4, characterized in that: The filtering circuit includes a filtering network and a transmission control unit, wherein the transmission control unit is used to adjust the transmission delay of the filtering network, and the level detection circuit controls the transmission control unit to establish or disconnect the circuit connection with the filtering network according to the level state.

7. The driving circuit according to claim 6, characterized in that: The transmission control unit is connected to the input end of the filter network, or is connected between the filter network and the signal shaping circuit, and the transmission control unit includes a resistor, an even number of inverters connected in series, an even number of NOT gates connected in series, a buffer or a delay device; When the level detection circuit detects that the intermediate signal is at a low level, the level detection circuit controls the transmission control unit to establish a connection with the filter network; when the level detection circuit detects that the intermediate signal is at a high level, the level detection circuit controls the transmission control unit to disconnect from the filter network.

8. The driving circuit according to any one of claims 4 to 7, characterized in that: The signal shaping circuit comprises: A transition detection circuit detects the flipping moment of the level state of the PWM signal to generate a corresponding transition edge; Wherein, the level detection circuit adjusts the speed at which the transition detection circuit generates the transition edge according to the level state.

9. The driving circuit according to claim 8, characterized in that: The transition detection circuit includes a comparator and a bias current source, wherein the bias current source provides a bias current for the comparator, and the comparator outputs the transition edge; After the level state changes from a high level to a low level, the level detection circuit controls the bias current to decrease, and after the level state changes from a low level to a high level, the level detection circuit controls the bias current to increase.

10. A half-bridge switching power supply, comprising an upper power tube and a lower power tube, characterized in that: The switching power supply further comprises: A PWM controller provides a pair of PWM signals; and According to the driving circuit according to any one of claims 1 to 9, the driving circuit outputs a pair of driving signals according to a pair of PWM signals to respectively control the upper power tube and the lower power tube of the switching power supply.

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