Filter packaging structure and electronic equipment

Abstract

The utility model discloses a filter packaging structure and an electronic device, and the filter packaging structure comprises a piezoelectric film which is provided with a first surface and a second surface which are opposite to each other, and the first surface is provided with a circuit structure and a plurality of resonators which are electrically connected with the circuit structure; the sealing cover structure is arranged on the first surface, a cavity is defined by the sealing cover structure and the first surface, the resonators are located in the cavity, and gaps are formed between the resonators and the sealing cover structure; the substrate is arranged on the second surface, and the piezoelectric film and the substrate are provided with corresponding through via holes; the inductance wire is arranged on one side, back to the piezoelectric film, of the substrate, and the inductance wire is electrically connected with the circuit structure through the via hole. No extra substrate is needed, the packaging size is reduced, and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency filtering, in particular to a filter packaging structure and electronic equipment. Background Art

[0002] The RF front end of communication equipment generally includes a filter to filter the RF signal. Acoustic wave filter is a type of filter, which includes surface acoustic wave (SAW) filter and bulk acoustic wave (BAW) filter. Surface acoustic wave (SAW) filter is widely used in RF front end because of its high operating frequency, wide bandwidth, good frequency selection characteristics, small size and light weight, simple manufacturing and low cost.

[0003] In the prior art, filters are generally composed of multiple resonators connected in series and parallel. Generally, capacitors or inductors are added to the filter circuit to improve the performance of the filter, such as improving out-of-band suppression. There are usually two ways to set the inductor. The first way is to set the inductor inside the filter, on the same side as the resonator, and package it as a whole, but this method will increase the package size, and the integration process is complicated and costly. The second way is to set the inductor on the substrate. On the one hand, this method will greatly increase the design difficulty of the module, and on the other hand, it will occupy the module substrate space, resulting in an increase in the number of substrate layers, thereby increasing costs. Utility Model Content

[0004] In view of this, the utility model proposes a filter packaging structure and an electronic device.

[0005] The first aspect of the utility model provides a filter packaging structure, comprising:

[0006] The piezoelectric film has a first surface and a second surface opposite to each other, wherein a circuit structure and a plurality of resonators electrically connected to the circuit structure are disposed on the first surface;

[0007] A cover structure, disposed on the first surface and enclosed with the first surface to form a cavity, wherein the plurality of resonators are located in the cavity, and there is a gap between the plurality of resonators and the cover structure;

[0008] A substrate is provided on the second surface, and the piezoelectric film and the substrate are provided with corresponding through holes;

[0009] The inductor wiring is arranged on a side of the substrate facing away from the piezoelectric film, and the inductor wiring is electrically connected to the circuit structure through the via hole.

[0010] In some embodiments, the circuit structure includes a first solder pad and a circuit trace, wherein the circuit trace is used to realize electrical connection between the plurality of resonators and between the first solder pad and the resonator; wherein the input end of the inductor trace is electrically connected to the first solder pad through the via so that the inductor trace is electrically connected to the resonator, and the output end of the inductor trace is grounded.

[0011] In some embodiments, a second pad is further provided on the side of the substrate facing away from the piezoelectric film, the first pad includes a first input pad, a first output pad and a first ground pad, and the second pad includes a second input pad, a second output pad and a second ground pad; wherein the number of the vias is at least three, and the at least three vias include a first via, a second via and a third via, the first input pad is electrically connected to the second input pad through the first via, the first output pad is electrically connected to the second output pad through the second via, the first ground pad is electrically connected to the input end of the inductor trace through the third via, and the output end of the inductor trace is electrically connected to the second ground pad.

[0012] In some embodiments, the plurality of resonators include at least two first resonators arranged in series and at least two second resonators arranged in parallel; one end of the at least two first resonators arranged in series is electrically connected to the first input pad, and the other end of the at least two first resonators arranged in series is electrically connected to the first output pad; one end of at least one second resonator is electrically connected to the first resonator, and the other end is electrically connected to the inductor trace through the first ground pad and the via.

[0013] In some embodiments, the second pad and the inductor trace are integrally formed and / or provided on a common layer.

[0014] In some embodiments, the thickness of the inductor trace is 3 μm-20 μm; and / or the inductor trace includes at least two stacked sub-layers.

[0015] In some embodiments, a dielectric layer is further provided on the side of the substrate facing away from the piezoelectric film, and the inductor trace is provided between the substrate and the dielectric layer, and passes through the dielectric layer to the side of the dielectric layer facing away from the substrate; wherein the relative dielectric constant of the dielectric layer is less than or equal to 10, and / or the material of the dielectric layer is silicon dioxide, silicon nitride or polyimide resin.

[0016] In some embodiments, the filter further includes a protective layer, which is disposed on a side of the substrate facing away from the piezoelectric film and covers the inductor trace.

[0017] In some embodiments, the material of the protective layer is resin or green oil; and / or, a second pad is provided on the side of the substrate facing away from the piezoelectric film, the second pad is electrically connected to the circuit structure through the via, the second pad is provided with a solder ball, the solder ball is used to electrically connect the second pad to an external circuit board, and the protective layer is provided with a window at the solder ball to expose the solder ball.

[0018] In some embodiments, the covering structure includes a cover plate and a retaining wall, wherein the retaining wall is formed on the first surface, the cover plate covers the retaining wall, and is combined with the retaining wall and the first surface to form the cavity; wherein the retaining wall includes a side wall and a top wall, wherein the side wall is formed on the first surface and extends in a direction perpendicular to the first surface, the top wall is connected to a side of the side wall away from the first surface, and the top wall is connected to the cover plate.

[0019] In some embodiments, the filter includes at least one of the following features: the side walls are arranged on at least two sides of the first solder pad, and the top wall is located between the first solder pad and the cover plate; the thickness of the side walls and / or the top wall is 5μm-20μm; the retaining wall is made of resin; the cover plate is made of resin or dielectric substrate material, and the dielectric substrate material is silicon, glass or sapphire.

[0020] In some embodiments, the filter includes at least one of the following features: the height of the cavity is greater than 3 μm; the thickness of the substrate is 100 μm-300 μm; a temperature compensation layer is also provided between the piezoelectric film and the substrate; the thickness of the piezoelectric film is less than or equal to 2 μm; the relative dielectric constant of the substrate is less than the relative dielectric constant of the piezoelectric film.

[0021] A second aspect of the present invention provides an electronic device, comprising the filter packaging structure mentioned above.

[0022] It can be seen from the above technical solutions that the filter packaging structure proposed by the utility model sets the inductor trace on the back of the substrate and electrically connects it to the circuit structure through a via, so that the inductor trace is electrically connected to the resonator on the first side of the piezoelectric film, and no additional substrate is required. On the one hand, the package size is reduced and the cost is reduced, and on the other hand, the package structure is optimized and the difficulty of applying the package structure in the module is reduced. In addition, the film morphology of the piezoelectric film is easy to etch to form a via, which can facilitate the processing of the via. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained like these drawings without paying creative labor.

[0024] Figure 1 It is a structural schematic diagram of the filter packaging structure proposed in an embodiment of the present application.

[0025] Figure 2 It is a structural schematic diagram of a deformation method of the filter packaging structure proposed in an embodiment of the present application.

[0026] Figure 3 It is a circuit topology diagram of the filter packaging structure proposed in the embodiment of the present application.

[0027] Figure 4 This is a schematic diagram of the inductor routing on the back side of the substrate proposed in an embodiment of the present application being arranged on the same layer.

[0028] Figure 5 It is a schematic diagram of a layered arrangement of the inductor wiring on the back side of the substrate proposed in an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 100, filter packaging structure; 10, piezoelectric film; 11, first surface; 12, second surface; 13, circuit structure; 131, first pad; 1311, first input pad; 1312, first output pad; 1313, first ground pad; 132, circuit routing; 14, resonator; 141, first resonator; 142, second resonator; 15, metal thickening layer; 20, cover structure; 21, cover plate; 22, retaining wall; 2 21. Side wall; 222. Top wall; 30. Cavity; 40. Substrate; 50. Via; 51. First via; 52. Second via; 53. Third via; 60. Inductor trace; 61. First layer trace; 62. Second layer trace; 63. Through hole; 70. Temperature compensation layer; 80. Second pad; 81. Second input pad; 82. Second output pad; 83. Second ground pad; 84. Solder ball; 90. Dielectric layer; 110. Protective layer. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0032] It should be understood that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0033] It should also be understood that when an element is referred to as being "fixed" or "disposed on" another element, it can be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or it can be indirectly connected to the other element through an intermediate element.

[0034] The terms used in this specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. For example, the descriptions of "first", "second", etc. in the present application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0035] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0036] The filter is generally composed of multiple resonators connected in series and parallel. Generally, capacitors or inductors are added to the filter circuit to improve the performance of the filter. For example, the inductor is connected to the parallel resonator in the filter circuit to improve out-of-band suppression.

[0037] Usually, there are two ways to package filters, one is CSP (Chip-Scale Package), and the other is WLP (Wafer Level Package). Compared with CSP, WLP has a smaller package size and is usually used in RF integrated module products. If the filter uses WLP packaging, in some related technologies, the inductor in the filter circuit is usually set in two ways. The first way is to set the inductor on the filter piezoelectric substrate, on the same side as the resonator, and package it as a whole, but this method will increase the size of the filter chip, and the integration process of the inductor and SAW is very complicated and costly. The second way is to package the filter WLP and set the inductor outside the filter. This method requires winding the inductor in the module substrate. On the one hand, this will greatly increase the difficulty of module design, and on the other hand, it will occupy the module substrate space, resulting in an increase in the number of substrate layers, thereby increasing costs.

[0038] Therefore, the embodiment of the present application proposes a filter packaging structure, in which the inductor routing is arranged on the back side of the substrate, without the need for an additional base plate. On the one hand, it reduces the package size and packaging cost; on the other hand, it reduces the difficulty of applying WLP packaging devices in modules.

[0039] See also Figures 1 to 3 As shown, the embodiment of the present application proposes a filter packaging structure 100, including: a piezoelectric film 10, having a first surface 11 and a second surface 12 opposite to each other. For example, the first surface 11 can be the front side of the piezoelectric film 10, and the second surface 12 can be the back side of the piezoelectric film 10. A circuit structure 13 and a plurality of resonators 14 electrically connected to the circuit structure 13 are provided on the first surface 11; a cover structure 20 is provided on the first surface 11, and is enclosed with the first surface 11 to form a cavity 30, and a plurality of resonators 14 are located in the cavity 30, and a gap is provided between the plurality of resonators 14 and the cover structure 20; a substrate 40 is provided on the second surface 12, and the piezoelectric film 10 and the substrate 40 are provided with corresponding through holes 50; an inductor trace 60 is provided on the side of the substrate 40 facing away from the piezoelectric film 10, and the inductor trace 60 is electrically connected to the circuit structure 13 through the via 50.

[0040] It can be understood that the resonator 14 includes a piezoelectric substrate and an interdigital transducer and a reflective grating arranged on the piezoelectric substrate. The piezoelectric substrate of the resonator 14 includes a piezoelectric film 10 and a substrate 40. Multiple resonators 14 in the filter are arranged on the same piezoelectric substrate, that is, they share the piezoelectric film 10 and the substrate 40. The piezoelectric substrate of the resonator 14 has the above structure, which can improve the Q value of the resonator, and the temperature compensation coefficient of the resonator is small, thereby improving the performance of the filter.

[0041] The filter packaging structure 100 proposed in the embodiment of the present application sets the inductor trace 60 on the back of the substrate 40 and electrically connects it to the circuit structure 13 through the via 50, so that the inductor trace 60 is electrically connected to the resonator 14 on the first surface 11 of the piezoelectric film 10, and no additional substrate is required. On the one hand, the package size is reduced and the cost is reduced, and on the other hand, the package structure is optimized and the difficulty of applying the package structure in the module is reduced. In addition, the film morphology of the piezoelectric film 10 is easy to etch to form the via 50, which can facilitate the processing of the via 50.

[0042] Exemplarily, there are gaps between the multiple resonators 14 and the cover structure 20, which means that there are gaps around and above the multiple resonators 14 and the cover structure 20, that is, there is no direct contact between the cover structure 20 and the resonator 14 to avoid affecting the performance of the resonator 14.

[0043] In some embodiments, the material of the piezoelectric film 10 may be lithium tantalate (LT), lithium niobate (LN), aluminum nitride (AlN), or quartz.

[0044] In some embodiments, the thickness of the piezoelectric film 10 is less than or equal to 2 μm. For example, the thickness of the piezoelectric film 10 can be 2 μm, 1.5 μm, 1 μm or even thinner. Since it is difficult to etch if the piezoelectric material such as LT or LN is too thick, it is difficult to prepare the via 50. Therefore, the piezoelectric material such as LT or LN is set to a thin film form, which is easy to etch to form the via 50, thereby facilitating the processing of the via 50. In addition, setting the piezoelectric material to a thin film form can also reduce interference with the inductor trace 60 to a certain extent.

[0045] It should be noted that, when the piezoelectric substrate of the resonator 14 includes a piezoelectric film 10 and a substrate 40, the inductor trace 60 in the filter circuit is arranged on the side of the substrate 40 facing away from the piezoelectric film 10, relative to being arranged on the back side of the piezoelectric film 10, that is, between the piezoelectric film 10 and the substrate 40, so that the distance from the interdigital transducer arranged on the front side of the piezoelectric film 10 can be increased, thereby avoiding affecting the working performance of the resonator 14, such as the possible generation of parasitic capacitance.

[0046] In some embodiments, the substrate 40 may be an insulating substrate such as silicon material, sapphire or spinel with high resistivity. The use of the above materials for the substrate 40 is beneficial to improving the Q value of the resonator 14 and reducing the risk of damage to the substrate 40 when forming the via 50.

[0047] In some embodiments, the thickness of the substrate 40 is 100 μm-300 μm. For example, the thickness of the substrate 40 may be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, etc. The substrate 40 is disposed on the back of the piezoelectric film 10, and the thickness of the substrate 40 is controlled within the range of 100 μm-300 μm. The ICP deep silicon etching process may be used to realize the TSV through hole.

[0048] In some embodiments, the relative dielectric constant of the substrate 40 is smaller than the relative dielectric constant of the piezoelectric film 10. This helps to improve the Q value (Quality Factor) of the wiring inductance.

[0049] In some embodiments, Figure 1 and Figure 2 As shown, a temperature compensation layer 70 is further provided between the piezoelectric film 10 and the substrate 40. Thus, the temperature compensation layer 70 is provided to compensate for the performance changes caused by temperature changes, thereby ensuring the stability and reliability of the piezoelectric film 10 at different temperatures. Exemplarily, the temperature compensation layer 70 may be made of silicon dioxide (SiO). Thus, the piezoelectric film 10, the temperature compensation layer 70 and the substrate 40 are stacked to form a composite structure.

[0050] In some embodiments, Figures 1 to 3As shown, the circuit structure 13 includes a first pad 131 and a circuit trace 132, and the circuit trace 132 is used to realize the electrical connection between the multiple resonators 14 and between the first pad 131 and the resonator 14; wherein, the input end of the inductor trace 60 is electrically connected to the first pad 131 through the via 50, so that the inductor trace 60 is electrically connected to the resonator 14, and the output end of the inductor trace 60 is grounded. Therefore, the circuit trace 132 is arranged on the first surface 11, that is, the front side of the piezoelectric film 10, the inductor trace 60 is arranged on the back side of the substrate 40, and the output end of the inductor trace 60 is grounded, which not only reduces the package size, but also makes one inductor only need one via 50 to lead out the signal, reducing the processing cost. In addition, the inductor trace 60 is arranged on the back side of the substrate 40, without the need for an additional substrate, so that the inductor trace 60 can use a thicker metal layer, thereby improving the Q value of the inductor trace 60.

[0051] In some embodiments, a second pad is further provided on the side of the substrate facing away from the piezoelectric film, the first pad includes a first input pad, a first output pad and a first ground pad, and the second pad includes a second input pad, a second output pad and a second ground pad; wherein, the number of vias is at least three, and the at least three vias include a first via, a second via and a third via, the first input pad is electrically connected to the second input pad through the first via, the first output pad is electrically connected to the second output pad through the second via, the first ground pad is electrically connected to the input end of the inductor trace through the third via, and the output end of the inductor trace is electrically connected to the second ground pad.

[0052] For example, Figure 1 and Figure 2As shown, the first pad 131 is arranged on the front side 11 of the piezoelectric film 10, and the first pad 131 includes a first input pad 1311, a first output pad 1312 and a first ground pad 1313. The second pad 80 is arranged on the side of the substrate 40 facing away from the piezoelectric film 10, and the second pad 80 includes a second input pad 81, a second output pad 82 and a second ground pad 83; wherein the via 50 includes a first via 51, a second via 52 and a third via 53, the first input pad 1311 is electrically connected to the second input pad 81 through the first via 51, the first output pad 1312 is electrically connected to the second output pad 82 through the second via 52, the first ground pad 1313 is electrically connected to the input end of the inductor trace 60 through the third via 53, and the output end of the inductor trace 60 is electrically connected to the second ground pad 83. Therefore, when the filter circuit only needs one inductor and grounding, the number of vias 50 can be set to three. Of course, the filter circuit can also be provided with multiple inductors and grounding terminals, then the number of vias 50 of the package structure can also be four, five or even more. For example, the filter circuit is provided with three inductors and needs to be grounded separately, then the number of vias 50 corresponding to the package structure needs to be five, so that the inductor traces 60 are electrically connected to the resonator 14 through different vias 50. Of course, the filter circuit can also be provided with multiple grounding terminals, which do not need to be connected to the inductor. In this case, multiple grounding terminals can share one via and share the ground through the via, or each grounding terminal can correspond to one via.

[0053] Understandably, Figure 1 and Figure 2 The example shown is only one example. In other examples, the components corresponding to 81, 82 and 83 are not limited to being the second input pad, the second output pad and the second ground pad, respectively. It is also possible that all three pads are ground pads, while the input pad and the output pad are not shown. It is also possible that 83 is not a ground pad, and one of 81 or 82 is a ground pad, and one end of the routing inductor can be connected to 81 or 82 and share the ground. Of course, there may be other examples, which will not be repeated here.

[0054] In some embodiments, the plurality of resonators 14 include at least two first resonators 141 arranged in series and at least two second resonators 142 arranged in parallel; one end of the at least two first resonators 141 arranged in series is electrically connected to the first input pad 1311, and the other end of the at least two first resonators 141 arranged in series is electrically connected to the first output pad 1312; one end of at least one second resonator 142 is electrically connected to the first resonator 141, and the other end is electrically connected to the inductor trace 60 through the first ground pad 1313 and the via 50. Therefore, the inductor trace 60 only needs one via 50 to be electrically connected to the second resonator 142 arranged in parallel, thereby achieving filter out-of-band suppression.

[0055] For example, Figures 1 to 3 As shown, the number of the first resonators 141 can be three, namely, resonator S1, resonator S2 and resonator S3 arranged in series from left to right, resonator S1 is electrically connected to the first input pad 1311, the first input pad 1311 is electrically connected to the second input pad 81 through the first via 51, resonator S2 is electrically connected to the first output pad 1312, and the first output pad 1312 is electrically connected to the second output pad 82 through the second via 52. The number of the second resonators 142 may be four, namely resonator P1, resonator P2, resonator P3, and resonator P4. One end of resonator P1 is connected to the common end of the first output pad 1312 and resonator S1, and one end of resonator P2 is connected to the common end of resonator S1 and resonator S2. At this time, the other end of resonator P1 is connected to the other end of resonator P2, so that the common end of resonator P1 and resonator P2 is electrically connected to the first ground pad 1313. The first ground pad is connected to the inductor trace 60 through the third via 53, and the inductor trace 60 is grounded through the second ground pad 83. Of course, in other examples, resonator P1 and resonator P2 may also be grounded separately. One end of the resonator P3 is connected to the common end of the resonator S2 and the resonator S3, and one end of the resonator P4 is connected to the common end of the resonator S3 and the first output pad 1312. At this time, the other end of the resonator P3 is connected to the other end of the resonator P4, so that the common end of the resonator P3 and the resonator P4 is grounded through another via (not shown). Of course, in other examples, the resonators P3 and P4 can also be grounded separately.

[0056] Understandably, Figure 1-Figure 3 The example shown is only one example. In other examples, the ground pad shown in 83 may also be a ground pad correspondingly connected to the resonator P3 and the resonator P4. Of course, there may be other examples, which will not be described here.

[0057] It should be noted that the arrangement of the first resonator 141 and the second resonator 142 is not limited to the above manner, for example, the number of the first resonators 141 can be two, four or even more, and the number of the second resonators 142 can be two, three, five or even more.

[0058] In some embodiments, Figure 1 and Figure 2 As shown, the second pad 80 and the inductor trace 60 are integrally formed and / or co-layered. Thus, during processing, the second pad 80 and the inductor trace 60 are integrally formed and share a layer of metal, which facilitates processing and reduces processing costs. Of course, in other embodiments, the second pad 80 and the inductor trace 60 can also be layered.

[0059] In some embodiments, the thickness of the inductor trace 60 is 3 μm-20 μm. Exemplarily, the thickness of the inductor trace 60 can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm. Thus, setting the thickness of the inductor trace 60 within the above range can meet the Q value requirement of the inductor. The thicker the thickness of the inductor trace 60 is set, the higher the Q value of the inductor is, so that the out-of-band suppression performance of the filter can be improved to a certain extent, and the insertion loss of the filter can be reduced.

[0060] Optionally, if the required inductance value is not very large, the inductor trace 60 can be arranged in the same layer, that is, arranged on the same surface. Of course, if a larger inductance value is required, or the inductor trace needs to be longer, and the area of ​​the same layer is not enough, the inductor trace 60 can be arranged in layers.

[0061] In some embodiments, the inductor trace 60 may be made of a single layer of metal, or may include at least two stacked sub-layers. For example, the inductor trace 60 may also be a three-layer, four-layer or even more metal stacked layer. By stacking multiple layers of metal, the inductor trace 60 can achieve a thicker metal thickness, thereby improving the Q value of the inductor. Exemplarily, the inductor trace 60 may use an electroplating process to facilitate the preparation of a multi-layer metal structure, so that the required metal layer thickness can be achieved.

[0062] For example, Figure 4 FIG. 1 is a schematic diagram of the case where the inductor traces are arranged on the same layer. After the signal is led out from the via to the first ground pad 1313, it passes through a section of the inductor trace 60 to reach the second ground pad 83. The layout of the second input pad 82 and the second output pad 83 can be as follows: Figure 4 As shown, other layouts are also possible. Figure 4 The pad layout in Figure 1 , Figure 2 The pad layout is different.

[0063] For example, Figure 5 The figure shows a schematic diagram of the inductor routing in a layered arrangement. For example, the inductor routing 60 includes two layers, namely, the first layer routing 61 and the second layer routing 62. The first layer routing 61 and the second layer routing 62 are arranged on different surfaces. The first layer routing 61 and the second layer routing 62 can be connected through a through hole 63. Through multi-layer routing, a larger inductance value can be achieved. After the signal is led out from the via hole to the first ground pad 1313, it passes through the first layer routing 61 and is connected to the second layer routing 62 through the through hole 63, and then reaches the second ground pad 83. The layout of the second input pad 82 and the second output pad 83 can be as follows: Figure 5 As shown, other layouts are also possible. Figure 5 The pad layout in Figure 1 , Figure 2 The pad layout is different.

[0064] Of course, in other examples, if the inductor trace 60 is divided into two layers and arranged on two different surfaces and cannot achieve the inductance value required by the filter circuit, the inductor trace 60 can also be divided into three layers, four layers or even more layers to arrange the inductor trace 60 on different surfaces, thereby achieving a larger inductance value.

[0065] For example, when the substrate 40 is made of silicon material, an IPD (Integrated Passive Device) process may be used on the silicon surface to implement multi-layer wiring with a simpler process and cost to achieve greater inductance.

[0066] Furthermore, a dielectric layer 90 may be provided on the side of the substrate 40 facing away from the piezoelectric film 10, and the inductor trace 60 is provided between the substrate 40 and the dielectric layer 90, and passes through the dielectric layer 90 to the side of the dielectric layer 90 facing away from the substrate 40. Figure 2 As shown, when the inductor trace 60 is arranged in layers, it includes a first-layer trace 61 and a second-layer trace 62. The first-layer trace 61 is arranged on the side of the dielectric layer 90 facing the substrate 40, and the second-layer trace 62 is arranged on the side of the dielectric layer 90 facing away from the substrate 40. The dielectric layer 90 is provided with a through hole, so that the first-layer trace 61 passes through the dielectric layer 90, thereby connecting with the second-layer trace 62 on the side of the dielectric layer 90 facing away from the substrate 40. Therefore, the arrangement of the dielectric layer 90 can support the packaging structure to form a longer inductor trace 60 to achieve a larger inductance value.

[0067] It should be noted that, in other examples, when the inductor trace 60 is arranged in the same layer, a dielectric layer 90 may also be arranged on the back of the substrate 40 to cover the inductor trace 60. Of course, when a longer inductor trace 60 is not required, the inductor trace 60 arranged in the same layer may be arranged on the side of the dielectric layer 90 facing away from the substrate 40. Of course, there may be other examples, which will not be described in detail here.

[0068] In some embodiments, the relative dielectric constant of the dielectric layer 90 is less than or equal to 10. Exemplarily, the dielectric layer 90 may be made of a material with a relative dielectric constant of 10, 9, 8, 7, 6, 5, 4, 3 or 2 or a smaller value. The dielectric layer 90 uses a material with a relatively small dielectric constant to reduce coupling capacitance and improve the inductor Q value.

[0069] In some embodiments, the dielectric layer 90 is made of silicon dioxide, silicon nitride or polyimide resin. Therefore, by using the above materials with a relatively small relative dielectric constant, the coupling capacitance can be reduced and the inductor Q value can be increased.

[0070] In some embodiments, Figure 1 and Figure 2 As shown, the filter further includes a protective layer 110, which is disposed on the side of the substrate 40 facing away from the piezoelectric film 10 and covers the inductor trace 60. Thus, the inductor trace 60 on the back of the substrate 40 can be protected by the provision of the protective layer 110.

[0071] In some embodiments, the material of the protective layer 110 is resin or green oil. Therefore, the material of the protective layer 110 can be either resin or green oil. Resin usually has good physical and chemical properties, such as high viscosity, thermal stability and electrical insulation, and can protect the inductor trace 60. Green oil not only has excellent acid and alkali resistance, solvent resistance, high temperature resistance and other properties, but also has a large viscosity, which can effectively prevent the inductor trace 60 from chemically reacting with oxygen in the environment, thereby reducing the degree of corrosion. The use of resin or green oil to protect the inductor trace 60 on the back of the substrate 40 does not require the use of a multi-layer dielectric substrate, so there is no need for an expensive wafer bonding process, reducing costs.

[0072] In some embodiments, Figure 1 and Figure 2 As shown, the second pad 80 is provided with a solder ball 84, and the solder ball 84 is used for electrically connecting the second pad 80 to an external circuit board. The protective layer 110 is provided with a window at the solder ball 84 to expose the solder ball 84. Thus, the solder ball 84 can ensure that the filter packaging structure 100 can be reliably connected to the circuit board. Exemplarily, the solder ball 84 can be a tin ball made of pure tin or a tin alloy, and the tin ball has good electrical conductivity and welding performance. The solder ball 84 can also be a copper column combined with a solder layer, which combines the advantages of copper and solder. The copper column provides good mechanical support and electrical conductivity, while the solder layer ensures reliable connection with other components.

[0073] Illustratively, during the manufacturing process, the protective layer 110 is first spread all over the back side of the substrate 40, and then windows are opened only at the solder balls 84, so that the solder balls 84 are exposed after welding is completed, and no windows are opened elsewhere, so as to protect the wiring and avoid short circuit failure caused by solder flow during welding.

[0074] In some embodiments, Figure 1 and Figure 2As shown, the cover structure 20 includes a cover plate 21 and a retaining wall 22, wherein the retaining wall 22 is formed on the first surface 11, the cover plate 21 covers the retaining wall 22, and forms a cavity 30 together with the retaining wall 22 and the first surface 11; wherein the retaining wall 22 includes a side wall 221 and a top wall 222, wherein the side wall 221 is formed on the first surface 11 and extends in a direction perpendicular to the first surface 11, and the top wall 222 is connected to a side of the side wall 221 away from the first surface 11, and the top wall 222 is connected to the cover plate 21. Thus, the piezoelectric film 10 is connected and the cover plate 21 is supported by the retaining wall 22, and the height of the cover plate 21 can be controlled by the thickness of the retaining wall 22, and the cover plate 21 and the retaining wall 22 form a cavity 30 together, thereby providing protection for the resonator 14.

[0075] In some embodiments, the side walls 221 are disposed on at least two sides of the first pad 131, and the top wall 222 is located between the first pad 131 and the cover plate 21. That is, the side walls 221 can be disposed on both sides of the first pad 131 to support the top wall 222 above the first pad 131, with a compact structure, saving space, and reducing the overall size of the packaging structure. Of course, the side walls 221 can also be disposed on three sides or all around the first pad 131 to improve stability, leaving a gap for routing. Exemplarily, the side walls 221 and the first pad 131 can be in contact to save space, or they can be non-contacting to leave a gap.

[0076] Of course, in other embodiments, the top wall 222 may not be disposed above the first pad 131, that is, the side wall 221 and the top wall 222 may be disposed at other free positions of the piezoelectric film 10, capable of supporting the cover plate 21 to enclose the cavity 30, and leaving a gap between the resonator 14.

[0077] In some embodiments, the thickness of the side wall 221 and / or the top wall 222 is 5 μm-20 μm. Exemplarily, the thickness of the side wall 221 and the top wall 222 may be equal or unequal, and the thickness of the side wall 221 and the top wall 222 may be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc. The height of the cover plate 21 is controlled by the thickness of the top wall 222, and the structural stability is ensured by the thickness of the side wall 221.

[0078] In some embodiments, the retaining wall 22 can be made of resin, and the cover plate 21 can be made of resin, dry film or dielectric substrate, and together with the retaining wall 22, form a cavity 30 to provide protection for the IDT. The resin has high viscosity, thermal stability and electrical insulation, and can form a more reliable cover structure 20.

[0079] If the cover plate 21 is made of resin or dry film, it needs to be made of a material with a large Young's modulus to have a certain degree of anti-molding ability to prevent the cavity from collapsing when the packaging structure is sealed. In this way, the structural stability of the cover plate 21 and the retaining wall 22 can be improved. Of course, the cover plate 21 can also be made of silicon wafer, sapphire or glass.

[0080] In some embodiments, the height of the cavity 30 is greater than 3 μm, and the height of the cavity 30 can be controlled by the retaining wall 22 and the cover plate 21 to meet the working performance requirements of the resonator 14 .

[0081] In some embodiments, a metal thickening layer 15 may be disposed above the first pad 131 to reduce resistance and protect the first pad 131. For example, except for the IDT and the reflector, the circuit trace 132 and the first pad 131 may be provided with a metal thickening layer 15.

[0082] In a specific application, the interdigital transducer and the reflective grating of the resonator 14 are generally manufactured together with the circuit trace 132 and the first pad 131. After the manufacturing is completed, the metal thickening layer 15 of the circuit trace 132 and the first pad 131 is processed to increase the heat dissipation effect and improve the power tolerance of the device.

[0083] The embodiment of the present application also provides an electronic device, including the filter packaging structure 100. For example, the electronic device may include but is not limited to electronic devices or components with PCBs such as LED panels, tablet computers, notebooks, computers, navigators, mobile phones, and electronic watches, and the present application does not limit this.

[0084] The structure and function of the filter packaging structure in the electronic device proposed in the embodiment of the present application are the same as those in the above embodiment. For details, please refer to the description of the above embodiment, and this embodiment will not be repeated.

[0085] Those skilled in the art may combine and associate different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0086] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the utility model, and these modifications or replacements should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A filter packaging structure, characterized in that: include: The piezoelectric film has a first surface and a second surface opposite to each other, wherein a circuit structure and a plurality of resonators electrically connected to the circuit structure are disposed on the first surface; A cover structure, disposed on the first surface and enclosed with the first surface to form a cavity, wherein the plurality of resonators are located in the cavity, and there is a gap between the plurality of resonators and the cover structure; A substrate is provided on the second surface, and the piezoelectric film and the substrate are provided with corresponding through holes; The inductor wiring is arranged on a side of the substrate facing away from the piezoelectric film, and the inductor wiring is electrically connected to the circuit structure through the via hole.

2. The filter packaging structure according to claim 1, characterized in that: The circuit structure includes a first pad and a circuit trace, wherein the circuit trace is used to realize electrical connection between the plurality of resonators and between the first pad and the resonator; The input end of the inductor line is electrically connected to the first pad through the via hole, so that the inductor line is electrically connected to the resonator, and the output end of the inductor line is grounded.

3. The filter packaging structure according to claim 2, characterized in that: A second pad is further provided on a side of the substrate facing away from the piezoelectric film, wherein the first pad includes a first input pad, a first output pad and a first ground pad, and the second pad includes a second input pad, a second output pad and a second ground pad; Among them, the number of the vias is at least three, and the at least three vias include a first via, a second via and a third via, the first input pad is electrically connected to the second input pad through the first via, the first output pad is electrically connected to the second output pad through the second via, the first ground pad is electrically connected to the input end of the inductor trace through the third via, and the output end of the inductor trace is electrically connected to the second ground pad.

4. The filter packaging structure according to claim 3, characterized in that: The plurality of resonators include at least two first resonators arranged in series and at least two second resonators arranged in parallel; One end of at least two of the first resonators arranged in series is electrically connected to the first input pad, and the other end of at least two of the first resonators arranged in series is electrically connected to the first output pad; One end of at least one of the second resonators is electrically connected to the first resonator, and the other end of the at least one of the second resonators is electrically connected to the inductor trace through the first ground pad and the via hole.

5. The filter packaging structure according to claim 3, characterized in that: The second pad and the inductor trace are integrally formed and / or arranged on a common layer.

6. The filter packaging structure according to claim 1, characterized in that: The thickness of the inductor wiring is 3 μm-20 μm; and / or, The inductor trace includes at least two stacked sub-layers.

7. The filter packaging structure according to claim 1, characterized in that: A dielectric layer is further provided on the side of the substrate facing away from the piezoelectric film, and the inductor wiring is provided between the substrate and the dielectric layer and passes through the dielectric layer to the side of the dielectric layer facing away from the substrate; Wherein, the relative dielectric constant of the dielectric layer is less than or equal to 10, and / or the dielectric layer is made of silicon dioxide, silicon nitride or polyimide resin.

8. The filter packaging structure according to claim 1, characterized in that: The filter further comprises a protective layer, which is arranged on a side of the substrate facing away from the piezoelectric film and covers the inductor trace.

9. The filter packaging structure according to claim 8, characterized in that: The material of the protective layer is resin or green oil; and / or, A second pad is also provided on the side of the substrate facing away from the piezoelectric film. The second pad is electrically connected to the circuit structure through the via. The second pad is provided with a solder ball for electrically connecting the second pad to an external circuit board. The protective layer is provided with a window at the solder ball to expose the solder ball.

10. The filter packaging structure according to claim 2, characterized in that: The sealing structure comprises a cover plate and a retaining wall, wherein the retaining wall is formed on the first surface, and the cover plate is sealed on the retaining wall and enclosed with the retaining wall and the first surface to form the cavity; The retaining wall includes a side wall and a top wall, wherein the side wall is formed on the first surface and extends in a direction perpendicular to the first surface, the top wall is connected to a side of the side wall away from the first surface, and the top wall is connected to the cover plate.

11. The filter packaging structure according to claim 10, characterized in that: The filter comprises at least one of the following features: The side walls are arranged on at least two sides of the first pad, and the top wall is located between the first pad and the cover plate; The thickness of the side wall and / or the top wall is 5 μm-20 μm; The retaining wall is made of resin; The cover plate is made of resin or dielectric substrate material, and the dielectric substrate material is silicon, glass or sapphire.

12. The filter packaging structure according to claim 1, characterized in that: The filter comprises at least one of the following features: The height of the cavity is greater than 3 μm; The thickness of the substrate is 100 μm-300 μm; A temperature compensation layer is also provided between the piezoelectric film and the substrate; The thickness of the piezoelectric film is less than or equal to 2 μm; The relative dielectric constant of the substrate is smaller than the relative dielectric constant of the piezoelectric film.

13. An electronic device, characterized in that: It comprises the filter packaging structure as claimed in any one of claims 1 to 12.

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