Trench isolation structure and semiconductor device
By designing trenches of different depths in semiconductor devices and setting dense isolators and dielectric layers, the problem of low avalanche breakdown voltage in deep trenches is solved, and the effect of increasing the avalanche breakdown voltage is achieved.
Patent Information
- Application Number
- CN202421582061.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-04
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-07-04
AI Technical Summary
In the prior art, the avalanche breakdown voltage in the deep trench region is low, causing the chip to break down in advance in this region, reducing the avalanche breakdown voltage of the device.
A trench isolation structure is provided, including a first groove and a second groove provided on the base body. The depth of the first groove is greater than the depth of the second groove. An isolation body is provided at the bottom of the grooves of each groove, and a dielectric layer is formed on the side walls. The isolation material is deposited by high-density plasma deposition to form a dense isolation body to improve the isolation effect.
By combining the isolator and the dielectric layer that occupy a certain depth, the problem of uneven dielectric layer thickness is avoided, the avalanche breakdown voltage in the deep trench area is improved, and the service life of the device is extended.
Smart Images
Figure CN222885081U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a trench isolation structure and a semiconductor device. Background Art
[0002] In today's semiconductor manufacturing process, trench isolation is one of the most important and complex processes in the front-end process of the semiconductor manufacturing process. The trench isolation process has been widely used in semiconductor manufacturing process technology below 0.25 microns. As the feature size continues to decrease, the trench isolation process is also constantly improving and developing. The basic requirement for the shallow trench isolation process is that when a large number of transistor devices are integrated into smaller and smaller chips, it can well insulate and isolate each tiny device without affecting the working characteristics of these devices. Specifically, multiple trenches are formed on the wafer and a dielectric layer is formed on the bottom wall, side wall and outer edge of the trench to achieve insulation isolation of each tiny device.
[0003] In the prior art, when making the gate oxide layer of a trench transistor, the gate oxide layer is formed by depositing oxide to fill the trench and then etching. Since the etching atmosphere is unevenly distributed in the trench, the thickness of the dielectric layer at the bottom of the trench is relatively thin. When the transistor is working, the electric field is concentrated at the bottom of the trench. In addition, due to the increase in the trench width and depth, the gate polysilicon is closer to the substrate, and the electric field concentration is more obvious. Therefore, compared with the cell area, the avalanche voltage value of the deep trench area is lower, and the chip breaks down in advance in this area, which reduces the avalanche breakdown voltage of the device. Utility Model Content
[0004] The purpose of the present application is to provide a trench isolation structure and a semiconductor device, which can improve the avalanche breakdown voltage in a deep trench region.
[0005] On the one hand, an embodiment of the present application provides a trench isolation structure, including a substrate, the substrate including at least a first groove and a second groove, wherein the depth of the first groove is greater than the depth of the second groove, a first insulator is arranged at the bottom of the first groove, and a second insulator is arranged at the bottom of the second groove, the upper surfaces of the first insulator and the second insulator are equidistant from the upper surface of the substrate, and the side walls of the first groove and the second groove are also provided with a dielectric layer.
[0006] As an practicable manner, an isolation material is deposited in the first groove and the second groove and then etched, so that the isolation material forms a first isolation body in the first groove and a second isolation body in the second groove.
[0007] As an practicable manner, both the deposition of the isolation material in the first groove and the deposition of the isolation material in the second groove are carried out by high-density plasma deposition.
[0008] As an implementable manner, gate connections are provided between the dielectric layer and the first insulator, and between the dielectric layer and the second insulator.
[0009] As an practicable manner, the gate connection is polysilicon.
[0010] As an practicable manner, the dielectric layer is a gate oxide layer, and the material of the gate oxide layer is silicon oxide.
[0011] As an practicable manner, the first insulator is a silicon oxide insulator or a silicon nitride insulator, and the second insulator is a silicon oxide insulator or a silicon nitride insulator.
[0012] As an practicable manner, the width of the second groove is greater than the width of the first groove.
[0013] As an implementable manner, the base includes a substrate and a body region disposed on the substrate, and the first groove and the second groove are disposed on one side of the body region and extend into the substrate.
[0014] Another aspect of an embodiment of the present application provides a semiconductor device, comprising the above-mentioned trench isolation structure.
[0015] The beneficial effects of the embodiments of the present application include:
[0016] The trench isolation structure provided by the present application includes a substrate, and the substrate includes at least a first groove and a second groove, wherein the depth of the first groove is greater than the depth of the second groove, a first insulator is arranged at the bottom of the first groove, and a second insulator is arranged at the bottom of the second groove, and the upper surfaces of the first insulator and the second insulator are at the same distance from the upper surface of the substrate, and the sidewalls of the first groove and the second groove are also provided with a dielectric layer. Among them, the first insulator is used to set the gate connection, and because the depth of the first groove is greater than the depth of the second groove, the depth occupied by the dielectric is smaller, and it is not easy to have uneven thickness, and the first insulator and the second insulator occupy the bottom of the first groove and the second groove, and the first insulator and the second insulator have dielectric properties, which can achieve isolation, so that it is not easy to have premature breakdown at the bottom of the groove. Therefore, the trench isolation structure of the embodiment of the present application can improve the avalanche breakdown voltage in the deep trench area. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1One of the schematic diagrams of a trench isolation structure provided in an embodiment of the present application;
[0019] Figure 2 One of the state diagrams of a preparation process of a trench isolation structure provided in an embodiment of the present application;
[0020] Figure 3 A second state diagram of a preparation process of a trench isolation structure provided in an embodiment of the present application;
[0021] Figure 4 A third state diagram of a preparation process of a trench isolation structure provided in an embodiment of the present application;
[0022] Figure 5 A fourth state diagram of a preparation process of a trench isolation structure provided in an embodiment of the present application;
[0023] Figure 6 A fifth state diagram of a manufacturing process of a trench isolation structure provided in an embodiment of the present application;
[0024] Figure 7 This is a second schematic diagram of a trench isolation structure provided in an embodiment of the present application.
[0025] Icon: 100 - trench isolation structure; 110 - base; 111 - substrate; 112 - body region; 121 - first groove; 122 - second groove; 131 - first isolation body; 132 - second isolation body; 141 - isolation material; 151 - gate connection; 161 - dielectric layer. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0029] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0030] Trench isolation is a device isolation technology widely used in very large scale integrated circuits.
[0031] The present application embodiment provides a trench isolation structure 100, such as Figure 1 As shown, it includes a substrate 110, and the substrate 110 includes at least a first groove 121 and a second groove 122, wherein the depth of the first groove 121 is greater than the depth of the second groove 122, a first insulator 131 is arranged at the bottom of the first groove 121, and a second insulator 132 is arranged at the bottom of the second groove 122, the upper surfaces of the first insulator 131 and the second insulator 132 are equidistant from the upper surface of the substrate 110, and a dielectric layer 161 is also arranged on the side walls of the first groove 121 and the second groove 122.
[0032] The trench isolation structure 100 of the embodiment of the present application is applied to semiconductor devices to isolate various tiny devices, wherein the first groove 121 has a shallow depth, which is shallow trench isolation, and the second groove 122 has a deep depth, which is deep trench isolation. Specifically, the embodiment of the present application respectively sets a first isolator 131 and a second isolator 132 in the first groove 121 and the second groove 122, and the distance between the upper surface of the first isolator 131 and the upper surface of the substrate 110 is equal to the distance between the upper surface of the second isolator 132 and the upper surface of the substrate 110, so that the upper surfaces of the first isolator 131 and the second isolator 132 are flush, so that when the dielectric layer 161 is subsequently deposited, the dielectric is set on the side walls of the first groove 121 and the second groove 122 where the isolators are not set. Since the first insulator 131 and the second insulator 132 occupy a certain depth, the depth occupied by the dielectric is relatively small, and uneven thickness is not likely to occur. In addition, the first insulator 131 and the second insulator 132 occupy the bottom of the first groove 121 and the second groove 122. The first insulator 131 and the second insulator 132 have dielectric properties and can achieve isolation, so that premature breakdown is not likely to occur at the bottom of the groove. Therefore, the trench isolation structure 100 of the embodiment of the present application can increase the avalanche breakdown voltage in the deep trench area.
[0033] Among them, the specific materials of the first insulator 131 and the second insulator 132 are not limited in the embodiment of the present application, as long as electrical isolation can be achieved. Those skilled in the art can select appropriate materials according to actual conditions. For example, the first insulator 131 is a silicon oxide insulator or a silicon nitride insulator, and the second insulator 132 is a silicon oxide insulator or a silicon nitride insulator. Silicon oxide and silicon nitride have high dielectric properties and are commonly used dielectric materials in the semiconductor field. They have good maturity in the deposition and etching processes, and can improve the quality of the first insulator 131 and the second insulator 132, thereby improving the isolation effect.
[0034] It can be understood that the depth of the first groove 121 is greater than the depth of the second groove 122, and the upper surface of the first isolator 131 is flush with the upper surface of the second isolator 132, so that the depth occupied by the first isolator 131 is greater than the depth of the second isolator 132, that is, the height of the first isolator 131 is greater than the height of the second isolator 132. Figure 1 shown.
[0035] In addition, a gate connection 151 is provided in the first groove 121 and the second groove 122 as a gate of the element. The first groove 121 is located in the cell region, and the second groove 122 is located in the deep trench region. Figure 1 As shown, Figure 1 The middle dotted line divides the first groove 121 and the second groove 122 into two areas. Components are respectively arranged in the two areas, and the first groove 121 and the second groove 122 serve as connection points of the two components.
[0036] The trench isolation structure 100 provided in the present application includes a first groove 121 and a second groove 122, and the depth of the first groove 121 is greater than the depth of the second groove 122, a first insulator 131 is arranged at the bottom of the first groove 121, and a second insulator 132 is arranged at the bottom of the second groove 122, the upper surfaces of the first insulator 131 and the second insulator 132 are at the same distance from the upper surface of the substrate 110, and the side walls of the first groove 121 and the second groove 122 are also provided with a dielectric layer 161. Among them, the first insulator 131 is used to set the gate connection 151. Since the depth of the first groove 121 is greater than the depth of the second groove 122, the depth occupied by the dielectric layer 161 is smaller, and uneven thickness is not easy to occur. The first insulator 131 and the second insulator 132 occupy the bottom of the first groove 121 and the second groove 122. The first insulator 131 and the second insulator 132 have dielectric properties and can achieve isolation, so that premature breakdown is not easy to occur at the bottom of the groove. Therefore, the trench isolation structure 100 of the embodiment of the present application can increase the avalanche breakdown voltage in the deep trench area.
[0037] Optional, such as Figure 3 and Figure 4As shown, an isolation material is deposited and etched in the first groove 121 and the second groove 122 , and the isolation material forms a first isolation body in the first groove 121 and a second isolation body in the second groove 122 .
[0038] The specific steps of forming the trench isolation structure 100 are as follows:
[0039] Step 1: Figure 2 As shown, a first groove 121 and a second groove 122 are formed on the base 110, and the first groove 121 and the second groove 122 have different depths;
[0040] Step 2: If Figure 3 As shown, an isolation material 141 is deposited on the substrate 110 , and the isolation material 141 fills the first groove 121 and the second groove 122 ;
[0041] It should be noted that since the first groove 121 and the second groove 122 have a certain depth, the upper surface of the filling material is concave in the first groove 121 and the second groove 122. At this time, mechanical grinding or other processes can be used to make its surface flat and parallel to the surface of the substrate 110.
[0042] Step 3, such as Figure 4 As shown, the isolation material 141 in the first groove 121 and the second groove 122 is etched from top to bottom. The material remaining in the first groove 121 after etching is the first isolation body 131, and the material remaining in the second groove 122 after etching is the second isolation body 132, thereby forming the first isolation body 131 and the second isolation body 132.
[0043] Because the filling materials of the first groove 121 and the second groove 122 are both the isolation material 141, which are the same material, they have the same etching rate for the etching gas or etching solution with the same parameters. In this way, when the parameters of the etching gas are controlled to be the same, the etching rates of the first groove 121 and the second groove 122 are the same. In this way, it is only necessary to control the etching time of the two grooves to be the same to make the etching depth the same, so that the upper surfaces of the first insulator 131 and the second insulator 132 are located on the same plane.
[0044] Step 4: Figure 5 As shown, a dielectric layer 161 is formed on the sidewalls of the first groove 121 and the second groove 122 , and the dielectric layer 161 serves as a gate isolation layer to isolate the gate.
[0045] In one achievable manner of the embodiment of the present application, both the deposition of the isolation material 141 in the first groove 121 and the deposition of the isolation material 141 in the second groove 122 are carried out by high-density plasma deposition.
[0046] High-density plasma deposition enhances the chemical vapor deposition process through a high-energy, high-density plasma environment. Specifically, high-density plasma deposition uses a special plasma generation method, such as inductively coupled plasma or electron cyclotron resonance, to generate a plasma with a very high ion density. This high-density plasma can provide more active particles, thereby increasing the deposition rate and the density of the film, reducing voids and bridging phenomena, thereby increasing the density of the isolation material 141, which can improve the density of the first isolation body 131 and the second isolation body 132, and further improve their isolation capabilities.
[0047] Optional, such as Figure 6 As shown, the gate connection 151 is provided between the dielectric layer 161 and the first isolation body 131 , and between the dielectric layer 161 and the second isolation body 132 .
[0048] From the above, it can be seen that the connection points for forming the gate are formed in the first groove 121 and the second groove 122, and the gate connection 151 is set between the dielectric layer 161 and the first insulator 131, and between the dielectric layer 161 and the second insulator 132. The gate connection 151 serves as a gate connection point and is connected to external signals to realize the control of the component.
[0049] In one achievable manner of the embodiment of the present application, the gate connection 151 is polysilicon.
[0050] The gate connection 151 is made of polysilicon because polysilicon has good electrical conductivity and can be used as an electrode, and can also withstand high temperature processing, which is essential for subsequent high temperature steps such as annealing in semiconductor device manufacturing. In addition, polysilicon is compatible with existing semiconductor manufacturing processes and can be easily formed by methods such as chemical vapor deposition.
[0051] Optional, such as Figure 6 As shown, the dielectric layer 161 is a gate oxide layer, and the material of the gate oxide layer is silicon oxide.
[0052] Silicon material is a commonly used material for semiconductors and is relatively easy to obtain, making silicon dioxide relatively easy to prepare. In addition, when silicon dioxide is used as a gate oxide layer, the isolation effect is better.
[0053] The thickness of the dielectric layer 161 is not limited in the embodiment of the present application, and those skilled in the art may make specific settings based on the isolation effect and isolation voltage.
[0054] In one implementable manner of the embodiment of the present application, the first insulator 131 is a silicon oxide insulator or a silicon nitride insulator, and the second insulator 132 is a silicon oxide insulator or a silicon nitride insulator.
[0055] Optionally, the width of the second groove 122 is greater than the width of the second groove 122 .
[0056] Because the second groove 122 has a relatively deep depth, during the processing of the second groove 122, due to the large depth-to-width ratio, the second groove 122 is not easy to process. In the embodiment of the present application, the width of the second groove 122 is set to be relatively large. In this way, during the processing of the second groove 122, the depth-to-width ratio of the second groove 122 can be reduced, thereby reducing the processing difficulty of the second groove 122.
[0057] In one possible implementation of the present application, Figure 7 As shown, the base body 110 includes a substrate 111 and a body region 112 disposed on the substrate 111 , and a first groove 121 and a second groove 122 are disposed on one side of the body region 112 and extend into the substrate 111 .
[0058] Among them, the substrate 111 serves as a carrier plate, and a body region 112 is formed on the substrate 111. Specifically, when the substrate 111 is a silicon substrate 111, silicon material can be deposited on the substrate 111 to form a silicon thin film as extraction. The deposited silicon thin film has a good crystal structure and film quality and serves as a working layer.
[0059] In addition, in order to facilitate the connection between the cell region and the deep trench region, a body region 112 contact region may be provided between the first groove 121 and the second groove 122, and a contact hole may be formed, such as Figure 6 In addition, Figure 7 As shown, the top surface of the trench isolation structure 100 is provided with Figure 6 The dielectric layer or passivation layer is shown.
[0060] The present application also discloses a semiconductor device, including the trench isolation structure 100. The semiconductor device includes the same structure and beneficial effects as the trench isolation structure 100 in the aforementioned embodiment. The structure and beneficial effects of the trench isolation structure 100 have been described in detail in the aforementioned embodiment, and will not be repeated here.
[0061] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A trench isolation structure, characterized in that: The invention comprises a substrate, which comprises at least a first groove and a second groove, wherein the depth of the first groove is greater than the depth of the second groove, a first insulator is arranged at the bottom of the first groove, and a second insulator is arranged at the bottom of the second groove, the upper surfaces of the first insulator and the second insulator are equidistant from the upper surface of the substrate, and the side walls of the first groove and the second groove are also provided with a dielectric layer.
2. The trench isolation structure according to claim 1, wherein: An isolation material is deposited and etched in the first groove and the second groove, so that the isolation material forms a first isolation body in the first groove and a second isolation body in the second groove.
3. The trench isolation structure according to claim 2, characterized in that: The deposition of the isolation material in the first groove and the deposition of the isolation material in the second groove are both carried out by high-density plasma deposition.
4. The trench isolation structure according to claim 1, wherein: Gate connections are provided between the dielectric layer and the first insulator, and between the dielectric layer and the second insulator.
5. The trench isolation structure according to claim 4, characterized in that: The gate connection is polysilicon.
6. The trench isolation structure according to claim 1, wherein: The dielectric layer is a gate oxide layer, and the material of the gate oxide layer is silicon oxide.
7. The trench isolation structure according to claim 1, wherein: The first insulator is a silicon oxide insulator or a silicon nitride insulator, and the second insulator is a silicon oxide insulator or a silicon nitride insulator.
8. The trench isolation structure according to claim 1, wherein: The width of the second groove is greater than the width of the second groove.
9. The trench isolation structure according to claim 1, wherein: The base body includes a substrate and a body region disposed on the substrate, and the first groove and the second groove are disposed on one side of the body region and extend into the substrate.
10. A semiconductor device, characterized in that: The invention comprises the trench isolation structure as claimed in any one of claims 1 to 9.