Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device comprises a semiconductor substrate and a lateral double-diffused metal oxide semiconductor transistor. The lateral double-diffused metal oxide semiconductor transistor comprises a drift region, and a source region, a gate region and a drain region which are sequentially arranged along the horizontal direction; the lateral double-diffused metal oxide semiconductor transistor further comprises a body region; the gate region comprises a gate oxide layer and a gate conductor which are located in the drift region trench, and the gate oxide layer surrounds the gate conductor, so that the gate conductor is insulated from the source region, the drain region, the body region and the drift region respectively; the gate oxide layer comprises a first oxidation structure located between the gate conductor and the drain region; along the arrangement direction of the gate region and the drain region, the width of the first oxidation structure at the first depth is a first width, and the width of the first oxidation structure at the second depth is a second width; the first depth is larger than the second depth and the first width is smaller than the second width. By adopting the technical scheme, the on-resistance can be reduced while the withstand voltage value is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a semiconductor device. Background Art

[0002] Lateral double diffused metal oxide semiconductor field effect transistors are widely used in the field of integrated circuits due to their advantages in gain, linearity, switching performance, heat dissipation performance, etc.

[0003] The on-resistance and breakdown voltage of LDMOS transistors are two main parameters, and there is a mutually restrictive relationship between the two. If the withstand voltage is increased, the on-resistance will increase at the same time, which is not conducive to the flow of current. If the on-resistance is reduced, it will be not conducive to the withstand voltage of the semiconductor device, and the semiconductor device is easy to burn out. Utility Model Content

[0004] The utility model provides a semiconductor device, which is used to improve the withstand voltage value of a lateral double diffused metal oxide semiconductor transistor and reduce the on-resistance.

[0005] According to the utility model, a semiconductor device is provided, comprising: a semiconductor substrate, and a lateral double diffused metal oxide semiconductor transistor located on one side of the semiconductor substrate;

[0006] The lateral double diffused metal oxide semiconductor transistor includes a drift region, and a source region, a gate region and a drain region which are located above the drift region and are arranged in sequence along a horizontal direction;

[0007] The lateral double diffused metal oxide semiconductor transistor further includes a body region; the body region is located in the drift region and is adjacent to the source region;

[0008] The gate region includes a gate oxide layer and a gate conductor located in the drift region trench, wherein the gate oxide layer surrounds the gate conductor so that the gate conductor is insulated from the source region, the drain region, the body region, and the drift region respectively;

[0009] The gate oxide layer includes a first oxide structure located between the gate conductor and the drain region; along the arrangement direction of the gate region and the drain region, the width of the first oxide structure at a first depth is a first width, and the width of the first oxide structure at a second depth is a second width; the first depth is greater than the second depth, and the first width is less than the second width.

[0010] Optionally, the first oxidation structure includes a slope surface;

[0011] At the first depth, the distance between the slope surface and the drain region is a first distance; at the second depth, the distance between the slope surface and the drain region is a second distance;

[0012] The first distance is greater than the second distance.

[0013] Optionally, along the arrangement direction of the gate region and the drain region, the maximum width of the first oxide structure is greater than or equal to the maximum width of the gate conductor along the arrangement direction of the gate region and the drain region.

[0014] Optionally, the lateral double diffused metal oxide semiconductor transistor further includes a field plate gate;

[0015] The field plate gate is located above the first oxide structure.

[0016] Optionally, the gate oxide layer further includes a second oxide structure located below the gate conductor;

[0017] Along the arrangement direction of the gate region and the drain region, the minimum width of the first oxide structure is greater than or equal to the maximum width of the second oxide structure along the vertical direction.

[0018] Optionally, along the vertical direction, the maximum depth of the first oxide structure is smaller than the maximum depth of the gate conductor.

[0019] Optionally, the maximum depth of the first oxide structure is greater than or equal to the maximum depth of the drain region.

[0020] Optionally, the body region includes a heavily doped body region and a lightly doped body region;

[0021] The body-doped region and the source region are arranged in a horizontal direction, and the body-doped region is located on a side of the source region away from the gate region; the body-lightly doped region is located below the source region and above the drift region;

[0022] The body region also includes a heavily doped extension region; the heavily doped extension region is located below the heavily doped region and above the drift region, and the heavily doped region is in contact and connected with the heavily doped region and the lightly doped region, respectively.

[0023] Optionally, the lateral double diffused metal oxide semiconductor transistor includes a first transistor and a second transistor; the first transistor and the second transistor are arranged opposite to each other;

[0024] The heavily doped region of the first transistor is reused as the heavily doped region of the second transistor;

[0025] The heavily doped extension region of the first transistor is reused as the heavily doped extension region of the second transistor.

[0026] The technical solution of the utility model increases the width of the first oxide structure locally, and at a second depth with a shallower depth, the second width of the first oxide structure is larger, and at a first depth with a deeper depth, the first width of the first oxide structure is smaller, so that the distance between the gate conductor and the drain region can be increased while reducing the resistance to current flow, which is beneficial to reducing the on-resistance of the lateral double diffused metal oxide semiconductor transistor while improving its withstand voltage value.

[0027] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 It is a structural schematic diagram of a semiconductor device provided by an embodiment of the utility model;

[0030] Figure 2 It is a structural schematic diagram of another semiconductor device provided by an embodiment of the utility model;

[0031] Figure 3 It is a structural schematic diagram of another semiconductor device provided by an embodiment of the utility model;

[0032] Figure 4 It is a flowchart of a method for preparing a semiconductor device provided by an embodiment of the utility model;

[0033] Figure 5 It is a structural schematic diagram of a preparation process of a first oxidation structure provided by an embodiment of the utility model;

[0034] Figure 6 It is a structural schematic diagram of a manufacturing process of a lateral double diffused metal oxide semiconductor transistor provided by an embodiment of the utility model;

[0035] Figure 7 It is a flowchart of another method for preparing a semiconductor device provided by an embodiment of the utility model;

[0036] Figure 8 This is a structural schematic diagram of a preparation process of another first oxidation structure provided by an embodiment of the utility model;

[0037] In the figure:

[0038] 01-semiconductor substrate, 02-lateral double diffused metal oxide semiconductor transistor, 10-drift region, 20-source region, 30-gate region, 31-gate oxide layer, 301-first oxide structure, 302-second oxide structure, 303-third oxide structure, 32-gate conductor, 40-drain region, 50-body region, 51-heavily doped region, 52-lightly doped body region, 53-heavily doped extension region, 60-field plate gate, 71-first oxide layer, 72-second oxide layer, 73-third oxide layer, 81-first silicon nitride layer, 82-second silicon nitride layer, SP-slope surface, h01-first trench, h02-second trench. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] Figure 1 is a schematic diagram of a semiconductor device provided by an embodiment of the utility model, with reference to Figure 1The semiconductor device includes a semiconductor substrate 01, and a lateral double diffused metal oxide semiconductor transistor 02 located on one side of the semiconductor substrate 01; the lateral double diffused metal oxide semiconductor transistor 02 includes a drift region 10, and a source region 20, a gate region 30 and a drain region 40 located above the drift region 10 and arranged in sequence in a horizontal direction; the lateral double diffused metal oxide semiconductor transistor 02 also includes a body region 50; the body region 50 is located in the drift region 10 and is adjacent to the source region 20; the gate region 30 includes a gate oxide layer 31 and a gate conductor located in a groove of the drift region 10 The gate oxide layer 31 surrounds the gate conductor 32 so that the gate conductor 32 is insulated from the source region 20, the drain region 40, the body region 50, and the drift region 10 respectively; the gate oxide layer 31 includes a first oxide structure 301 located between the gate conductor 32 and the drain region 40; along the arrangement direction of the gate region 30 and the drain region 40, the width of the first oxide structure 301 at the first depth D1 is a first width T1, and the width of the first oxide structure 301 at the second depth D2 is a second width T2; the first depth D1 is greater than the second depth D2, and the first width T1 is less than the second width T2.

[0042] The above of the drift region 10 refers to the direction away from the side of the semiconductor substrate 01 in the vertical direction, the vertical direction refers to the direction perpendicular to the plane where the semiconductor substrate 01 is located; the horizontal direction refers to the direction parallel to the plane where the semiconductor substrate 01 is located. The depth refers to the distance extending from the surface of the semiconductor device to the semiconductor substrate 01 in the vertical direction; the width refers to the distance of a certain structure or region in a certain direction (which can be the horizontal direction or the vertical direction).

[0043] Specifically, the lateral double diffused metal oxide semiconductor transistor 02 further includes a source S02, a gate S03 and a drain D02 located on the surface of the semiconductor device, wherein the source S02 is located on the surface of the source region 20, the gate G02 is located on the surface of the gate region 30, and the drain D02 is located on the surface of the drain region 40. When a positive voltage or a negative voltage is applied between the gate G02 and the source S02, charges can be generated between the gate G02 and the source S02, and minority carriers can be gathered. If a positive voltage or a negative voltage is also applied between the drain D02 and the source S02, a minority carrier channel can be formed in the body region 50 and conduct current. When the absolute value of the voltage value between the gate G02 and the source S02 is greater than the absolute value of the threshold voltage, and a corresponding voltage is also applied between the drain D02 and the source S02, the current can flow from the drain region 40 to the source region 20 or from the source region 20 to the drain region 40 in the horizontal direction through the drift region 10.

[0044] It should be noted that the figure only exemplarily shows that the source S02 is located on the surface of the source region 20 and also on the surface of the body region 50. In other optional embodiments, the source S02 can be replaced by two independent electrodes located on the surface of the source region 20 and the surface of the body region 50 respectively.

[0045] Continue to refer Figure 1 The gate region 20 includes a gate oxide layer 31 and a gate conductor 32 located in the groove of the drift region 10. The gate conductor 32 is arranged between the source region 20 and the drain region 40 along the horizontal direction. The gate oxide layer 31 and the gate conductor 32 form a vertical gate structure, which is beneficial to increase the withstand voltage of the lateral double diffused metal oxide semiconductor transistor 02, so that its breakdown voltage is larger and not easily damaged. Among them, along the vertical direction, the maximum depth of the groove where the gate oxide layer 31 and the gate conductor 32 are located can be set according to actual needs, and the embodiment of the utility model does not limit this.

[0046] The gate oxide layer 31 can insulate the gate conductor 32 from other regions in the semiconductor device, wherein the thickness of the gate oxide layer 31 (i.e., the distance of the gate oxide layer 31 that isolates the gate conductor 32 from other regions in the semiconductor device) will also affect the characteristics of the lateral double diffused metal oxide semiconductor transistor 02. The first oxide structure 301 of the gate oxide layer 31 is located between the gate conductor 32 and the drain region 40, and along the arrangement direction of the gate region 30 and the drain region 40, the width of the first oxide structure 301 is the distance of the gate oxide layer 31 that isolates the gate conductor 32 from the drain region 40. Along the arrangement direction of the gate region 30 and the drain region 40, the width of the first oxide structure 301 is positively correlated with the gate-drain breakdown voltage of the lateral double diffused metal oxide semiconductor transistor 02. The wider the width of the first oxide structure 301 is along the arrangement direction of the gate region 30 and the drain region 40, the greater the gate-drain breakdown voltage of the lateral double diffused metal oxide semiconductor transistor 02 is, but the on-resistance will also increase at the same time. By locally increasing the width of the first oxide structure 301 along the arrangement direction of the gate region 30 and the drain region 40, that is, along the arrangement direction of the gate region 30 and the drain region 40 with the increase of depth, the width of the first oxide structure 301 gradually decreases, which can reduce the resistance to the current flow between the drain region 40 and the source region 20, thereby increasing the breakdown voltage while reducing the on-resistance, which is beneficial to taking into account both the withstand voltage value and the on-resistance of the lateral double diffused metal oxide semiconductor transistor 02.

[0047] For example, the lateral double diffused metal oxide semiconductor transistor 02 is an NMOS transistor. The semiconductor substrate 01 can be a P-type substrate P-sub, the drift region 10 can be an N-type drift region N-drift, the source region 20 and the drain region 40 can both include an N-type heavily doped region N+, and the body region 50 can include a P-type heavily doped region P+ and a P-type lightly doped region PB. When a positive voltage is applied between the drain D02 and the source S02, and the voltage between the gate G02 and the source S02 is greater than the threshold voltage, an N-type channel is formed between the drain region 40 and the source region 20 and is turned on, and the current flows from the drain region 40 to the source region 20.

[0048] It can be understood that the lateral double diffused metal oxide semiconductor transistor can also be a PMOS transistor. In this case, the semiconductor substrate can be an N-type substrate, the drift region can be a P-type drift region, the source region and the drain region can both include a P-type heavily doped region, and the body region can include an N-type heavily doped region and an N-type lightly doped region. When a positive voltage is applied between the source and the drain, and the voltage between the gate and the source is less than the threshold voltage, a P-type channel is formed between the source and the drain and is turned on, and the current flows from the source region to the drain region.

[0049] In the embodiment of the utility model, by locally increasing the width of the first oxide structure, and at a second depth with a shallower depth, the second width of the first oxide structure is larger, and at a first depth with a deeper depth, the first width of the first oxide structure is smaller, the distance between the gate conductor and the drain region can be increased while reducing the resistance to current flow, which is beneficial to reducing the on-resistance of the lateral double diffused metal oxide semiconductor transistor while improving its withstand voltage value.

[0050] Optional, continue to refer to Figure 1 The first oxide structure 301 includes a slope surface SP; at a first depth D1, the distance between the slope surface SP and the drain region 40 is a first distance L1; at a second depth D2, the distance between the slope surface SP and the drain region 40 is a second distance L2; the first distance L1 is greater than the second distance L2.

[0051] Specifically, as the depth increases, the width of the first oxide structure 301 gradually decreases along the arrangement direction of the gate region 30 and the drain region 40. At the same time, as the depth increases, the first oxide structure 301 gradually moves away from the drain region 40. When a channel is formed between the source region 20 and the drain region 40, the transmission path of the carriers in the channel can be shortened, which is beneficial to reducing the on-resistance and improving the performance of the semiconductor device, so as to avoid the first oxide structure 301 being close to the drain region 40. The lower side has a large corner, which hinders the flow of current, increases the on-resistance, is not conducive to withstand voltage and current flow, and burns the device; the width of the slope surface SP along the arrangement direction of the gate region 30 and the drain region 40 and / or the depth along the vertical direction can be adjusted according to actual needs, so as to flexibly adjust and optimize the breakdown voltage and on-resistance. In addition, the slope surface SP of the first oxide structure 301 is also beneficial to uniformize the electric field strength near the drain region 40, avoid the formation of electric field spikes near the drain region 40, and affect the withstand voltage value of the lateral double diffused metal oxide semiconductor transistor 02.

[0052] Optional, Figure 2 is a schematic diagram of the structure of another semiconductor device provided by the embodiment of the utility model, referring to Figure 2, along the arrangement direction of the gate region 30 and the drain region 40, the maximum width T301 of the first oxide structure 301 is greater than or equal to the maximum width T32 of the gate conductor 32 along the arrangement direction of the gate region 30 and the drain region 40. By setting the maximum width T301 of the first oxide structure 301 to be wider, it is beneficial to increase the distance between the gate conductor 32 and the drain region 40, thereby increasing the withstand voltage value of the transistor.

[0053] On the basis of the above embodiment, the lateral double diffused metal oxide semiconductor transistor 02 further includes a field plate gate 60 ; the field plate gate 60 is located above the first oxide structure 301 .

[0054] Specifically, a large number of electric field lines may gather below the first oxide structure 301 and near the edge of the drain region 40 close to the gate conductor 32, forming a high electric field peak. When the voltage difference between the gate conductor 32 and the drain region 40 increases, the electric field will increase rapidly. The high electric field in the local area is likely to cause the device to avalanche breakdown and fail. By setting the field plate grid 60, the strong electric field near the gate conductor 32 can be reduced, the breakdown voltage can be increased, and the performance of the semiconductor device can be improved. Among them, the potential of the field plate grid 60 can be set according to actual needs. For example, a fixed potential can be provided to the field plate grid 60 to connect the source region 20, the gate conductor 32 or the drain region 40. The embodiment of the utility model is not limited to this.

[0055] In an optional embodiment, the potential of the field plate gate 60 may be kept consistent with the potential of the source region 20 .

[0056] Optional, continue to refer to Figure 2 The gate oxide layer 31 further includes a second oxide structure 302 located below the gate conductor 32; along the arrangement direction of the gate region 30 and the drain region 40, the minimum width T301' of the first oxide structure 301 is greater than or equal to the maximum width T302 of the second oxide structure 302 along the vertical direction. By setting the minimum width T301' of the first oxide structure 301 to be greater than or equal to the maximum width T302 of the second oxide structure 302, it is beneficial to increase the maximum width T301 of the first oxide structure 301, thereby increasing the withstand voltage value of the transistor.

[0057] Optional, continue to refer to Figure 2 The gate oxide layer 31 further includes a third oxide structure 303 located between the gate conductor 32 and the source region 20; along the arrangement direction of the gate region 30 and the source region 20, the maximum width T303 of the third oxide structure 303 is less than or equal to the maximum width T302 of the second oxide structure 302 along the vertical direction. In this way, the threshold voltage and on-resistance of the transistor are reduced.

[0058] Optional, continue to refer to Figure 2, along the vertical direction, the maximum depth D301 of the first oxide structure 301 is less than the maximum depth D32 of the gate conductor 32 .

[0059] Exemplarily, only a portion of the gate oxide layer 31 on the side of the gate conductor 32 close to the drain region 40 is the first oxide structure 301, and is locally thickened. In the gate oxide layer 31 on the side of the gate conductor 32 close to the drain region 40, a portion with a depth of D301-D32 is not thickened, and a portion with a depth of 0-D301 is locally thickened, and as the depth decreases, the width gradually increases, which is beneficial to improve the withstand voltage value of the lateral double diffused metal oxide semiconductor transistor while reducing its on-resistance.

[0060] Optional, continue to refer to Figure 2 The maximum depth D301 of the first oxide structure 31 is greater than or equal to the maximum depth D40 of the drain region 40, that is, along the arrangement direction of the gate region 30 and the drain region 40, the depth (maximum depth D301) of the position where the minimum width of the first oxide structure 31 is located is greater than or equal to the maximum depth D40 of the drain region 40. In this way, the gate oxide layer 31 between the gate conductor 32 and the drain region 40 (the portion with a depth of 0-D40) is the first oxide structure 31, which can effectively improve the withstand voltage value of the lateral double diffused metal oxide semiconductor transistor.

[0061] Optional, continue to refer to Figure 2 The body region 50 includes a heavily doped region 51 and a lightly doped region 52; the heavily doped region 51 and the source region 20 are arranged in a horizontal direction, and the heavily doped region 51 is located on the side of the source region 20 away from the gate region; the lightly doped region 52 is located below the source region 20 and above the drift region 10; the body region 50 also includes a heavily doped extension region 53; the heavily doped extension region 53 is located below the heavily doped region 51 and above the drift region 10, and the heavily doped region 53 is in contact and connected with the heavily doped region 51 and the lightly doped region 52 respectively.

[0062] Exemplarily, taking the lateral double diffused metal oxide semiconductor transistor 02 as an NMOS transistor as an example, the heavy doped region 51 includes a P-type heavily doped region P+, the body lightly doped region 52 includes a P-type lightly doped region PB, and the heavily doped extension region 53 includes a P-type heavily doped region Extra-P+. The heavily doped extension region 53 can be used as an extension region of the heavy doped region 51, which is equivalent to the heavy doped region 51. By setting the heavily doped extension region 53, it is beneficial to increase the contact area between the heavy doped region 51 and the body lightly doped region 52, and increase the depth of the heavy doped region 51 (i.e., reduce the height of the heavy doped region 51), so that the contact surface position between the heavy doped region 51 and the body lightly doped region 52 is lower.

[0063] In this way, the contact resistance between the heavy doped region 51 and the lightly doped region 52 can be reduced. When the semiconductor device is subjected to radiation, such as space radiation, which causes a large number of electrons and holes to be generated in the lightly doped region 52, the holes in the lightly doped region 52 can be quickly led out of the device from the heavy doped region 51, thereby preventing the holes in the lightly doped region 52 from being transmitted to the source region 20. The parasitic NPN formed by the source region 20, the lightly doped region 52 and the drift region 10 has a large base current, and the parasitic NPN is turned on. The parasitic NPN generates a large current, forming a latching effect and damaging the device. Among them, when the lateral double diffused metal oxide semiconductor transistor 02 is an NMOS transistor, electrons will flow to the high potential drain region 40, that is, to the collector of the parasitic NPN formed by the source region 20, the lightly doped region 52 and the drift region 10, and will not turn on the parasitic NPN to form a large current.

[0064] Optional, Figure 3 is a schematic diagram of the structure of another semiconductor device provided by the embodiment of the utility model, referring to Figure 3 The lateral double diffused metal oxide semiconductor transistor 02 includes a first transistor and a second transistor; the first transistor and the second transistor are arranged relatively to each other; the heavily doped region 51 of the first transistor is reused as the heavily doped region 51 of the second transistor; the heavily doped extension region 53 of the first transistor is reused as the heavily doped extension region 53 of the second transistor.

[0065] Illustratively, along the horizontal direction (from left to right or from right to left in the figure), the drain region 40, gate region 30, source region 20, and heavily doped region 51 of the first transistor, and the heavily doped region 51, source region 20, gate region 30, and drain region 40 of the second transistor are arranged in sequence, and part of the body region 50 adjacent to the first transistor and the second transistor is reused, which can reduce the size of the lateral double diffused metal oxide semiconductor transistor 02 in the horizontal direction, which is beneficial to the integration of semiconductor devices.

[0066] Based on the same utility model concept, the utility model embodiment also provides a method for preparing a semiconductor device. Figure 4 It is a flowchart of a method for preparing a semiconductor device provided by an embodiment of the utility model. Figure 5 is a structural schematic diagram of a preparation process of a first oxidation structure provided by an embodiment of the utility model, Figure 6 is a schematic diagram of a structure of a manufacturing process of a lateral double diffused metal oxide semiconductor transistor provided by an embodiment of the utility model, with reference to Figure 4-Figure 6 , the preparation method comprises:

[0067] S1001, providing a semiconductor substrate, and performing ion implantation and diffusion on the semiconductor substrate to form a drift region of a lateral double diffused metal oxide semiconductor transistor.

[0068] The semiconductor substrate 01 includes but is not limited to a silicon substrate.

[0069] Exemplary, reference Figure 5 Taking the lateral double diffused metal oxide semiconductor transistor 02 as an NMOS transistor as an example, the semiconductor substrate 01 may be a P-type substrate P-sub, and the drift region 10 may be an N-type drift region N-drift.

[0070] S1002 , etching on the surface of the drift region to form a first groove.

[0071] Exemplary, reference Figure 5 , a mask layer (not shown in the figure) can be formed on the surface of the drift region 10, and the mask layer can be patterned to expose the area on the surface of the drift region 10 where the first groove h01 needs to be formed, and the exposed surface of the drift region 10 can be etched to form the first groove h01. The embodiment of the utility model does not limit the process of forming the first groove h01, and the depth of the first groove h01 can be set according to actual needs, and the embodiment of the utility model does not limit it.

[0072] S1003 , using a local oxidation process to locally oxidize the sidewall of a partial area of ​​the first trench, so that the sidewall of the partial area of ​​the first trench forms a slope.

[0073] Exemplary, reference Figure 5 Before forming the slope, a silicon nitride layer (not shown in the figure) may be formed near the sidewall of a portion of the first trench to act as a local hard mask. The silicon nitride covers the area where oxidation should not occur, and the oxide grows only on the bare silicon. Since silicon and silicon nitride have different thermal expansion coefficients, a thin oxide layer (not shown in the figure) may be deposited between silicon and silicon nitride to prevent strain caused by temperature changes.

[0074] A local oxidation process is adopted to take advantage of the different oxidation rates of silicon and silicon nitride. When the bare silicon is oxidized, the thin oxide layer causes lateral diffusion of the oxide under the silicon nitride, thereby causing the oxide at the edge of the nitride mask to grow. The extended portion is somewhat like the shape of a bird's beak, also known as the bird's beak effect. The bird's beak effect of the local oxidation process can be used to form a slope on the sidewall of a partial area of ​​the first trench h01.

[0075] S1004 , after forming the slope, performing oxidation deposition on the first trench, filling the first trench with an oxidation material, and the oxidation material forms a first oxidation structure.

[0076] Specifically, refer to Figure 5The oxide material in the first trench H01 forms a first oxide structure 301. As the depth increases, the width of the first oxide structure 301 gradually decreases along the horizontal direction. In an optional embodiment, the semiconductor substrate 01 includes a silicon substrate, and the oxide material includes silicon dioxide.

[0077] S1005, using photolithography and etching processes, forming a second trench on the side wall of the trench away from the slope side, and exposing the side wall of the first oxide structure.

[0078] Exemplary, reference Figure 6 A mask layer (not shown in the figure) may be formed on the surface first, and the mask layer may be patterned to expose the surface area where the second trench h02 is to be formed, and the exposed surface may be etched to form the second trench h02. The second trench h02 is located on the side of the first oxide structure 301 away from the slope.

[0079] S1006, forming an oxide layer on the inner wall of the second trench, the oxide layer and the first oxide structure forming a gate oxide layer.

[0080] Exemplary, reference Figure 6 The gate oxide layer 31 includes a first oxide structure 301 , a second oxide structure 302 located on the inner wall of the bottom of the second trench h02 , and a third oxide structure 303 located on the inner wall of the second trench h02 away from the first oxide structure 301 .

[0081] S1007, forming a gate conductor in the oxide layer, and then forming a source region, a drain region, and a body region of a lateral double diffused metal oxide semiconductor transistor.

[0082] In the embodiment of the utility model, after forming the first trench, a slope is formed on the sidewall of a part of the first trench, so that the first oxide structure formed in the first trench can be locally thickened, and the width of the first oxide structure is larger at a shallower depth, and the width of the first oxide structure is smaller at a deeper depth. This can increase the distance between the gate conductor and the drain region while reducing the resistance to current flow, which is beneficial to reducing the on-resistance of the lateral double diffused metal oxide semiconductor transistor while improving its withstand voltage.

[0083] In an optional implementation, before the local oxidation process is used to locally oxidize the sidewall of a portion of the first trench so that the sidewall of the portion of the first trench forms a slope, the process further includes: isotropically etching the sidewall.

[0084] Specifically, by isotropically etching the sidewall of a portion of the first trench before performing a local oxidation process to form the slope, the sidewall can be made to form a certain slope first, and then the local oxidation process is performed, which is conducive to regulating the slope.

[0085] In another optional embodiment, after a local oxidation process is used to locally oxidize the sidewalls of a portion of the first trench so that the sidewalls of the portion of the first trench form a slope, it includes: growing a wet oxygen sacrificial oxide layer and removing it to obtain a smooth slope and eliminate the chamfer formed during the local oxidation process.

[0086] Optional, Figure 7 It is a flowchart of another method for preparing a semiconductor device provided by an embodiment of the utility model. Figure 8 This is a schematic diagram of the preparation process of another first oxidation structure provided by the embodiment of the utility model, referring to Figure 6-Figure 8 , the preparation method comprises:

[0087] S2001, providing a semiconductor substrate, and performing ion implantation and diffusion on the semiconductor substrate to form a drift region of a lateral double diffused metal oxide semiconductor transistor.

[0088] S2002, forming a first oxide layer and a first silicon nitride layer in sequence on the surface of the drift region, and forming a first trench in the drift region by using photolithography and etching processes.

[0089] Exemplary, reference Figure 8 Before forming the first trench h01, a first oxide layer 71 may be formed on the surface by thermal oxidation, and then a first silicon nitride layer 81 may be formed on the surface of the first oxide layer 71 by chemical vapor deposition. The first silicon nitride layer 81 may be used as a stop layer in the chemical mechanical polishing process when the oxide material outside the first trench h01 is subsequently removed, and the first oxide layer 71 may alleviate the stress damage to the semiconductor substrate 01 and the drift region 10 caused by the formation of the first silicon nitride layer 81.

[0090] In an optional implementation, the semiconductor substrate 01 includes a silicon substrate, and the first oxide layer 71 includes silicon dioxide.

[0091] S2003, after forming the first trench, sequentially forming a second oxide layer and a second silicon nitride layer.

[0092] Exemplarily, after forming the first trench h01, the entire second oxide layer 72 and the second silicon nitride layer 82 are formed successively, so that the inner wall surface of the first trench h01 is sequentially covered with the second oxide layer 72 and the second silicon nitride layer 82. The second silicon nitride layer 82 can act as a local hard mask in the subsequent local oxidation process, and the second oxide layer 72 can prevent strain caused by temperature changes.

[0093] In an optional implementation, after forming the second silicon nitride layer 82 , a third oxide layer 73 may be formed to planarize the surface, which is beneficial for subsequent processing.

[0094] S2004, using photolithography and etching processes to remove the first oxide layer, the first silicon nitride layer, the second oxide layer, and the second silicon nitride layer in a preset area to expose the sidewall of a partial area of ​​the first trench.

[0095] The preset area refers to a position above the area where a slope needs to be formed.

[0096] Specifically, the second oxide layer 72 and the second silicon nitride layer 82 in a preset area are removed to expose the area where the slope needs to be formed, so that the position can be processed to form the slope in a subsequent process.

[0097] S2005 , using a local oxidation process to locally oxidize the sidewall of a partial area of ​​the first trench, so that the sidewall of the partial area of ​​the first trench forms a slope.

[0098] S2006, after forming the slope, removing the second silicon nitride layer, and performing oxidation deposition on the first trench.

[0099] Specifically, after the slope is formed, the second silicon nitride layer 82 used as a mask in the first trench h01 and the second silicon nitride layer 82 outside the first trench h01 are removed. If the oxide material subsequently filled in the first trench h01 is the same as the material of the second oxide layer 72, the second oxide layer 72 does not need to be removed in this step; if the oxide material subsequently filled in the first trench h01 is different from the material of the second oxide layer 72, the second oxide layer 72 needs to be removed in this step.

[0100] S2007, after the first trench is fully filled with the oxide material, a chemical mechanical polishing process is used to remove the oxide material outside the first trench, and then the first silicon nitride layer is removed, and the oxide material inside the first trench constitutes a first oxide structure.

[0101] For example, a chemical mechanical polishing process may be used to remove the oxide material on the surface of the first silicon nitride layer 81 , and then hydrofluoric acid may be used to remove the oxide material on the surface of the first oxide layer 71 , and finally the first silicon nitride layer 81 may be removed.

[0102] In an optional implementation, after removing the first silicon nitride layer, the first oxide layer outside the first trench may be removed by photolithography and etching, and only the oxide material in the first trench is retained to form a first oxide structure.

[0103] S2008, using photolithography and etching processes, forming a second trench on the side wall of the trench away from the slope side, and exposing the side wall of the first oxide structure.

[0104] S2009, forming an oxide layer on the inner wall of the second trench, the oxide layer and the first oxide structure forming a gate oxide layer.

[0105] S2010, forming a gate conductor in the oxide layer, and then forming a source region, a drain region, and a body region of a lateral double diffused metal oxide semiconductor transistor.

[0106] In the above two preparation method embodiments, it is also necessary to add that after the device is prepared by the above preparation method, in order to ensure the normal use of the semiconductor device, it is necessary to connect it to the outside, that is, it is necessary to connect the metal electrode, such as Figure 1 The source S02, gate G02, and drain D02 are shown, so it is necessary to add the following steps after S1007 or S2010: perform a back-end process to form a plurality of contact holes, and connect each electrode of the device with the corresponding metal layer through the contact holes.

[0107] The method for preparing a semiconductor device provided in the embodiment of the utility model is used to prepare the semiconductor device provided in any embodiment of the utility model, and has the corresponding technical features and beneficial effects of the semiconductor device. For the contents not fully described in the embodiment of the method for preparing a semiconductor device, refer to the above description of the semiconductor device, and will not be repeated here. Similarly, the semiconductor device in the embodiment of the utility model also has the functional modules and beneficial effects that can execute the method for preparing a semiconductor device provided in the embodiment of the utility model. For the contents not fully described in the embodiment of the semiconductor device, refer to the above description of the method for preparing a semiconductor device, and will not be repeated here.

[0108] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate, and a lateral double diffused metal oxide semiconductor transistor located on one side of the semiconductor substrate; The lateral double diffused metal oxide semiconductor transistor includes a drift region, and a source region, a gate region and a drain region which are located above the drift region and are arranged in sequence along a horizontal direction; The lateral double diffused metal oxide semiconductor transistor further includes a body region; the body region is located in the drift region and is adjacent to the source region; The gate region includes a gate oxide layer and a gate conductor located in the drift region trench, wherein the gate oxide layer surrounds the gate conductor so that the gate conductor is insulated from the source region, the drain region, the body region, and the drift region respectively; The gate oxide layer includes a first oxide structure located between the gate conductor and the drain region; along the arrangement direction of the gate region and the drain region, the width of the first oxide structure at a first depth is a first width, and the width of the first oxide structure at a second depth is a second width; the first depth is greater than the second depth, and the first width is less than the second width.

2. The semiconductor device according to claim 1, wherein: The first oxidation structure includes a slope surface; At the first depth, the distance between the slope surface and the drain region is a first distance; at the second depth, the distance between the slope surface and the drain region is a second distance; The first distance is greater than the second distance.

3. The semiconductor device according to claim 1, wherein: Along the arrangement direction of the gate region and the drain region, the maximum width of the first oxide structure is greater than or equal to the maximum width of the gate conductor along the arrangement direction of the gate region and the drain region.

4. The semiconductor device according to claim 3, characterized in that The lateral double diffused metal oxide semiconductor transistor also includes a field plate gate; The field plate gate is located above the first oxide structure.

5. The semiconductor device according to claim 1, wherein: The gate oxide layer further includes a second oxide structure located below the gate conductor; Along the arrangement direction of the gate region and the drain region, the minimum width of the first oxide structure is greater than or equal to the maximum width of the second oxide structure along the vertical direction.

6. The semiconductor device according to claim 1, wherein: Along the vertical direction, the maximum depth of the first oxide structure is smaller than the maximum depth of the gate conductor.

7. The semiconductor device according to claim 1, wherein: The maximum depth of the first oxide structure is greater than or equal to the maximum depth of the drain region.

8. The semiconductor device according to claim 1, wherein: The body region includes a heavily doped region and a lightly doped region; The body-doped region and the source region are arranged in a horizontal direction, and the body-doped region is located on a side of the source region away from the gate region; the body-lightly doped region is located below the source region and above the drift region; The body region also includes a heavily doped extension region; the heavily doped extension region is located below the heavily doped region and above the drift region, and the heavily doped region is in contact and connected with the heavily doped region and the lightly doped region, respectively.

9. The semiconductor device according to claim 8, characterized in that The lateral double diffused metal oxide semiconductor transistor includes a first transistor and a second transistor; the first transistor and the second transistor are arranged opposite to each other; The heavily doped region of the first transistor is reused as the heavily doped region of the second transistor; The heavily doped extension region of the first transistor is reused as the heavily doped extension region of the second transistor.

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