Collection electron protection ring layout structure for eliminating antenna effect
By adding an inverted P-type injection epitaxial layer to the integrated circuit layout structure, the PSD/N well/DNW/NBL diode is formed, which solves the problems of large area occupation caused by the antenna effect and great impact on the circuit structure, and effectively eliminates the antenna effect and improves the stability and reliability of the integrated circuit.
Patent Information
- Application Number
- CN202421698215.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-07-18
AI Technical Summary
When the prior art eliminates the antenna effect in integrated circuits, it faces problems such as large area occupation, large impact on the circuit structure, and still exists in the risk of antenna effect.
By adding an inverted P-type injection epitaxial layer to the layout structure, a PSD/N well/DNW/NBL diode is formed to achieve the function of eliminating the antenna effect.
It effectively solves the problems of large area occupation and great impact on the circuit structure, while avoiding the risk of antenna effect and improving the stability and reliability of integrated circuits.
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Figure CN222885084U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electrical components, in particular to a collection electron protection ring layout structure for eliminating antenna effects. Background Art
[0002] The exposed conductor will accumulate charge during the dry etching process, and when enough charge is accumulated, it will damage the gate dielectric. This plasma-induced damage failure is called the antenna effect. During the layout design process, designers need to perform specific antenna effect checks on the layout to check whether the gate of the MOS transistor is connected to a large area of conductor.
[0003] There are usually two ways to eliminate the antenna effect:
[0004] 1. Add metal jumper.
[0005] 2. Add a diode to discharge the charge.
[0006] Designers usually solve the antenna effect by jumping metal wires to the upper layer. However, this method may not be suitable for digital circuits with relatively complex metal connections. Therefore, a diode is needed to connect the conductor with accumulated charge to the substrate. When the voltage on the conductor reaches the conduction condition of the diode or reaches the breakdown voltage of the diode, the diode conducts / breaks down, so that the accumulated charge is quickly discharged.
[0007] Figure 1 It is a PSD / N-well diode. Figure 2 for Figure 1 The cross-sectional view of the P-type implanted epitaxial layer and the N-well form a PN junction diode, which is placed outside the guard ring. When the voltage of the b1 node is higher than the N-well potential, the diode is forward biased. When the voltage of the b1 node is lower than the substrate potential, the PSD epitaxial layer undergoes avalanche breakdown before the thick oxygen is damaged.
[0008] However, adding PSD / N-well diodes directly on conductors to eliminate the antenna effect has the following drawbacks:
[0009] 1. Adding this device to the routing channel will occupy a large area. Although the overall device size can be reduced to minimize the occupied area. However, when a large number of antenna effects appear, the PSD / N-well diode will affect the metal wiring and hierarchical layout. For example, the periphery of the junction cannot be surrounded by metal, and the N-well in the junction needs to be placed adjacent to the N-well of the same potential.
[0010] 2. This PSD / N-well diode placed near the gate may have an impact on the circuit structure. When a large number of PSD / N-well diodes appear in a densely wired layout structure, it is impossible to quantify the impact of this structure on the actual circuit.
[0011] 3. When the PSD / N-well diode is placed far away from the gate oxide layer that needs to be protected, the conductor connecting the diode and the gate oxide layer accumulates charge, and there may still be a risk of antenna effect.
[0012] Figure 3a , 3b The different effects of charge accumulation on the gate conductor when the bleeder diode is placed closer and farther away are shown.
[0013] Designers usually add guard rings between sensitive circuit modules to absorb noise and minority carriers. According to design rules, this layout structure with a large junction depth will occupy more area.
[0014] Therefore, a layout structure is needed that can improve area efficiency while eliminating the antenna effect. Summary of the invention
[0015] The utility model aims to solve the problem of antenna effect in the layout structure and provides a layout structure for collecting electrons to eliminate the antenna effect. An inverted P-type injection epitaxial layer is added to the layout structure to form a PSD / N well / DNW / NBL diode while collecting the electron protection layout structure, thereby achieving the function of eliminating the antenna effect.
[0016] The utility model provides a collection electron protection ring layout structure for eliminating antenna effect, comprising a metal layer to be eliminated antenna effect, a P-type epitaxial layer, an N well, a deep N well, an NBL buried layer and a substrate connected in sequence from top to bottom;
[0017] The metal layer to be eliminated for the antenna effect is the signal line passing through the guard ring, and the N-well, deep N-well and NBL buried layer share the same point;
[0018] The P-type epitaxial layer, the N-well, the deep N-well, and the NBL buried layer form a PN junction diode.
[0019] The electronic collection protection ring layout structure for eliminating antenna effect described in the utility model, as a preferred method, also includes metal signal lines connected to a power supply on the left and right sides of the metal layer to be eliminated antenna effect and an N-type epitaxial layer connected below the metal signal line, and an N-well connected below and outside the P-type epitaxial layer and the two N-type epitaxial layers.
[0020] The electronic collection protection ring layout structure for eliminating antenna effect described in the utility model is preferably configured such that the deep N-well is located below the P-type epitaxial layer and two N-type epitaxial layers.
[0021] The electronic collection protection ring layout structure for eliminating antenna effect described in the utility model is preferably configured such that the length of the deep N-well is greater than the sum of the lengths of the P-type epitaxial layer and the two N-type epitaxial layers.
[0022] The utility model discloses a collection electron protection ring layout structure for eliminating antenna effect. As a preferred embodiment, the NBL buried layer is located below the P-type epitaxial layer and the two N-type epitaxial layers.
[0023] In the electron collection protection ring layout structure for eliminating antenna effect described in the utility model, as a preferred embodiment, the length of the NBL buried layer is greater than the length of the P-type epitaxial layer.
[0024] The electronic collection protection ring layout structure for eliminating antenna effect described in the utility model is, as a preferred embodiment, a metal layer to be eliminated of the antenna effect and two metal signal lines are located in the same metal layer.
[0025] The electronic collection protection ring layout structure for eliminating antenna effect described in the utility model is, as a preferred embodiment, the number of metal layers to be eliminated for the antenna effect is at least two.
[0026] The utility model discloses a collection electron protection ring layout structure for eliminating antenna effect. As a preferred embodiment, the P-type epitaxial layer, N-well, deep N-well and NBL buried layer are all located inside the protection ring.
[0027] The utility model adds an inverted P-type injection epitaxial layer in the PSD / N well and locates it within the guard ring, and can form a PSD / N well / DNW / NBL diode while collecting the electronic protection layout structure, thereby achieving the function of eliminating the antenna effect.
[0028] The utility model solves the area problem caused by adding PSD / N well diodes; and avoids charge accumulation between the diodes placed far away and the conductors between the gate oxide layer. Inserting the structure in the guard ring close to the gate can effectively protect the gate oxide layer.
[0029] The utility model has the following advantages:
[0030] The utility model combines a commonly used electron collection protection ring with a diode for eliminating antenna effect, thereby improving area efficiency while improving the safety and reliability of the integrated circuit. While improving area efficiency, it effectively eliminates the antenna effect and improves the stability of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A layout of a PSD / N-well diode;
[0032] Figure 2 is a cross-sectional view of a PSD / N-well diode;
[0033] Figure 3aA first cross-sectional schematic diagram of a charge accumulation effect of a PSD / N-well diode at different placement distances;
[0034] Figure 3b A second cross-sectional schematic diagram of the charge accumulation effect of a PSD / N-well diode at different placement distances;
[0035] Figure 4 A schematic diagram of a layout structure of a collection electronic protection ring for eliminating antenna effect;
[0036] Figure 5 An N-type implantation and a P-type implantation epitaxial layer layout are placed in a collection electron protection ring layout structure for eliminating antenna effect;
[0037] Figure 6 A layout of a deep N-well and NBL buried layer for collecting electron guard ring layout structure to eliminate antenna effect;
[0038] Figure 7 The figure is a cross-sectional diagram of each layer of the protection ring for a collection electronic protection ring layout structure that eliminates the antenna effect.
[0039] Reference numerals:
[0040] 1. Metal layer whose antenna effect is to be eliminated; 2. P-type epitaxial layer; 3. N-well; 4. Deep N-well; 5. NBL buried layer; 6. Substrate; 7. Metal layer; 8. N-type epitaxial layer. DETAILED DESCRIPTION
[0041] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.
[0042] Example 1
[0043] like Figures 4 to 7 As shown, a layout structure of an electron collection guard ring for eliminating antenna effect includes: a metal layer 1 to be eliminated antenna effect, a P-type epitaxial layer 2, an N well 3, a deep N well 4, an NBL buried layer 5, and a substrate 6 connected in sequence from top to bottom;
[0044] The metal layer 1 whose antenna effect is to be eliminated is a signal line passing through a guard ring, and the N well 3, the deep N well 4 and the NBL buried layer 5 share the same point;
[0045] The P-type epitaxial layer 2 forms a PN junction diode with the N-well 3, the deep N-well 4, and the NBL buried layer 5;
[0046] The P-type epitaxial layer 2, the N well 3, the deep N well 4, the NBL buried layer 5, and the substrate 6 are all located inside the guard ring.
[0047] Example 2
[0048] like Figures 4 to 7 As shown, a layout structure of an electron collection guard ring for eliminating antenna effect includes a metal layer 1 to be eliminated antenna effect, a P-type epitaxial layer 2, an N well 3, a deep N well 4, an NBL buried layer 5, a substrate 6, a metal signal line 7 connected to a power supply on the left and right sides of the metal layer 1 to be eliminated antenna effect, and an N-type epitaxial layer 8 connected below the metal signal line 7, which are connected in sequence from top to bottom;
[0049] The metal layer 1 whose antenna effect is to be eliminated is a signal line passing through a guard ring, and the N well 3, the deep N well 4 and the NBL buried layer 5 share the same point;
[0050] The P-type epitaxial layer 2 forms a PN junction diode with the N-well 3, the deep N-well 4, and the NBL buried layer 5;
[0051] The N-well 3 is connected below and outside the P-type epitaxial layer 2 and the two N-type epitaxial layers 8;
[0052] The deep N-well 4 is located below the P-type epitaxial layer 2 and the two N-type epitaxial layers 8; the length of the deep N-well 4 is greater than the sum of the lengths of the P-type epitaxial layer 2 and the two N-type epitaxial layers 8;
[0053] The NBL buried layer 5 is located below the P-type epitaxial layer 2 and the two N-type epitaxial layers 8, and the length of the NBL buried layer 5 is greater than the length of the P-type epitaxial layer 2;
[0054] The metal layer 1 whose antenna effect is to be eliminated and the two metal signal lines 7 are located in the same metal layer;
[0055] The number of metal layers to be eliminated of antenna effect is at least two;
[0056] The P-type epitaxial layer 2, the N well 3, the deep N well 4, the NBL buried layer 5, and the substrate 6 are all located inside the guard ring.
[0057] Figure 4 The electron collection guard ring of the inverted P-type implanted epitaxial layer 2 is inserted in Examples 1 and 2, and a1 to a6 and b1 to b6 represent signal lines passing through the metal 2 and the metal 1 through the guard ring, respectively.
[0058] Figure 5 for Figure 4 The N-type implanted epitaxial layer 8 and the P-type implanted epitaxial layer 2 of the layout structure show that an inverted P-type implanted epitaxial layer 2 is inserted at the metal line where the antenna effect needs to be eliminated.
[0059] Figure 6The deep N-well 4 and N-type buried layer 5 of the guard ring are introduced to obtain the deepest junction depth and reduce the N-well resistance. At the same time, because the deep N-well 4 and the N-type buried layer 5 are the same type as the upper N-type implanted epitaxial layer 8, these structures share the same potential. This guard ring structure connected to the highest power supply potential can effectively absorb minority carriers and absorb noise at the same time. It is worth noting that the layers of the guard ring itself have no physical connection with the internal circuit.
[0060] Due to the characteristics of the guard ring, the utility model can take any parameters. When designing the utility model, an active area with a width of 3um is adopted for design.
[0061] Figure 7 The cross-sectional view of each layer of the protection ring shows that below the metal line 1 (node b1) where the antenna effect needs to be eliminated, the P-type epitaxial layer 2 forms a PN junction diode with the inverted N-well 3, deep N-well 4, and NBL buried layer 5 below.
[0062] The use method of embodiments 1 and 2 is as follows: when the voltage of node b1 is higher than the potential of N well 3, the diode is forward biased. When the voltage of node b1 is lower than the potential of substrate 6, the PSD epitaxial layer undergoes avalanche breakdown before the thick oxide is damaged, eliminating the antenna effect.
[0063] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes within the technical scope disclosed by the present invention according to the technical scheme and the utility model concept of the present invention, which should be covered by the protection scope of the present invention.
Claims
1. A collection electron protection ring layout structure for eliminating antenna effect, characterized in that: It comprises a metal layer (1) to be eliminated of antenna effect, a P-type epitaxial layer (2), an N well (3), a deep N well (4), an NBL buried layer (5) and a substrate (6) which are connected in sequence from top to bottom; The metal layer (1) whose antenna effect is to be eliminated is a signal line passing through a guard ring, and the N well (3), the deep N well (4) and the NBL buried layer (5) share the same point; The P-type epitaxial layer (2), the N-well (3), the deep N-well (4), and the NBL buried layer (5) form a PN junction diode.
2. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 1 is characterized in that: It also includes metal signal lines (7) connected to a power source and arranged on the left and right sides of the metal layer (1) whose antenna effect is to be eliminated, and an N-type epitaxial layer (8) connected below the metal signal line (7); the N-well (3) is connected below and outside the P-type epitaxial layer (2) and the two N-type epitaxial layers (8).
3. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 2 is characterized in that: The deep N-well (4) is located below the P-type epitaxial layer (2) and the two N-type epitaxial layers (8).
4. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 3 is characterized in that: The length of the deep N-well (4) is greater than the sum of the lengths of the P-type epitaxial layer (2) and the two N-type epitaxial layers (8).
5. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 2, characterized in that: The NBL buried layer (5) is located below the P-type epitaxial layer (2) and the two N-type epitaxial layers (8).
6. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 5, characterized in that: The length of the NBL buried layer (5) is greater than the length of the P-type epitaxial layer (2).
7. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 2, characterized in that: The metal layer (1) whose antenna effect is to be eliminated and the two metal signal lines (7) are located in the same metal layer.
8. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 1, characterized in that: The number of the metal layers (1) whose antenna effect is to be eliminated is at least two.
9. The electronic collection protection ring layout structure for eliminating antenna effect according to claim 1, characterized in that: The P-type epitaxial layer (2), the N well (3), the deep N well (4) and the NBL buried layer (5) are all located inside the protection ring.