Semiconductor test structure and test method

Abstract

The application provides a semiconductor test structure and a test method, and belongs to the technical field of semiconductors. The test structure comprises two test branches, wherein the first test branch comprises n (n>=1) first test transistors and a first reference transistor, the gate oxide of the first test transistor and the first reference transistor has a first thickness, and the gate electrode of the first test transistor is connected with a corresponding first antenna structure; the second test branch comprises n second test transistors and a second reference transistor, the gate oxide of the second test transistor and the second reference transistor has a second thickness, the second thickness is smaller than the first thickness, and the gate electrode of the second test transistor is connected with a corresponding second antenna structure. The application can automatically judge the damage degree of the antenna effect on the gate oxide by using the threshold voltage deviation of the two test branches, thereby solving the problem that the damage degree of the gate oxide cannot be identified and the problem of missed judgment, and the accuracy and reliability of antenna effect monitoring are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor test structure and test method. Background Technology

[0002] In the back-end processes of deep submicron integrated circuit manufacturing, plasma etching and deposition processes are widely used. However, these processes introduce free charges onto the surface of conductive structures. When these conductive structures with accumulated free charges are directly connected to the gate electrode of a transistor, the free charges will dissipate through the gate oxide of the transistor, potentially causing plasma-induced damage (PID) to the gate oxide. This can severely reduce the reliability and lifespan of the device and even the entire chip. This phenomenon is also known as the antenna effect, and the probability of the antenna effect occurring can be quantified using the antenna ratio, which is equal to the ratio of the area of ​​the conductive structure to the area of ​​the gate electrode.

[0003] To quantify the impact of antenna effects on device reliability and monitor process window shifts, dedicated semiconductor test structures are typically used to sensitively reflect changes in electrical parameters that damage the gate oxide caused by antenna effects. However, the degree of gate oxide damage is not a single mode; there is mild damage corresponding to interface trap states and fatal damage corresponding to tunneling or soft breakdown. Current test structures cannot distinguish the degree of gate oxide damage, which can easily lead to missed detections. Furthermore, they are prone to misjudgments due to minute changes in electrical parameters introduced by non-ideal factors such as process gradients and temperature drift. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a semiconductor test structure and test method to solve the problems of existing test structures being unable to distinguish the degree of gate oxide damage and being prone to missed detection and false detection.

[0005] This application provides a semiconductor testing structure, including: A first test branch includes a first reference transistor and n first test transistors, wherein the gate oxide of both the first test transistors and the first reference transistors has a first thickness, and the gate electrode of the first test transistors is connected to a corresponding first antenna structure; and, The second test branch includes a second reference transistor and n second test transistors. The gate oxide of both the second test transistor and the second reference transistor has a second thickness, which is less than the first thickness. The gate electrode of the second test transistor is connected to the corresponding second antenna structure, and n≥1.

[0006] In some embodiments, the second thickness is less than 1 / 2 of the first thickness.

[0007] In some embodiments, the first thickness is 20 angstroms to 40 angstroms; and / or, the second thickness is 10 angstroms to 20 angstroms.

[0008] In some embodiments, n first test transistors and n first reference transistors are arranged along a first predetermined direction, with adjacent first test transistors and adjacent first test transistors and first reference transistors sharing a source region; n second test transistors and n second reference transistors are arranged along the first predetermined direction, with adjacent second test transistors and adjacent second test transistors and second reference transistors sharing a source region; and / or, n first test transistors and n second test transistors are arranged in n columns along a second predetermined direction, and the gate electrodes of the first test transistors and the second test transistors in each column are integral structures.

[0009] In some embodiments, the first test branch and the second test branch have a symmetrical layout structure.

[0010] In some embodiments, both the first antenna structure and the second antenna structure include a conductive layer and / or a conductive via, and the first antenna structure and the second antenna structure have the same structure and size.

[0011] An embodiment of this application also provides a testing method utilizing the aforementioned semiconductor test structure, comprising: Obtain the average threshold voltage deviation between each of the first test transistors and the first reference transistor on the first test branch; Obtain the average threshold voltage deviation between each of the second test transistors and the second reference transistor on the second test branch; and, The degree of damage to the gate oxide caused by the antenna effect is determined based on the average threshold voltage deviation between the first test branch and the second test branch.

[0012] In some embodiments, determining the degree of gate oxide damage based on the average threshold voltage deviation between the first test branch and the second test branch includes: The ratio of the average threshold voltage deviation of the second test branch to the average threshold voltage deviation of the first test branch is used as the damage coefficient; and, When the damage coefficient is greater than or equal to 0.8 and less than or equal to 1.2, the damage to the gate oxide is determined to be interface trap damage; when the damage coefficient is greater than 1.2, the damage to the gate oxide is determined to be tunneling / soft breakdown damage; when the damage coefficient is less than 0.8, the gate oxide is determined to be without damage.

[0013] In some embodiments, after determining the degree of gate oxide damage based on the average threshold voltage deviation between the first test branch and the second test branch, the method further includes: The source of gate oxide damage is determined based on the polarity of the average threshold voltage deviation between the first test branch and the second test branch. When the average threshold voltage deviations of the first test branch and the second test branch are both negative, it is determined that negative charges have accumulated in the first antenna structure and the second antenna structure, and the source of gate oxide damage is the deposition process during the fabrication of the first antenna structure and the second antenna structure; when the average threshold voltage deviations of the first test branch and the second test branch are both positive, it is determined that positive charges have accumulated in the first antenna structure and the second antenna structure, and the source of gate oxide damage is the etching process during the fabrication of the first antenna structure and the second antenna structure.

[0014] In some embodiments, obtaining the average threshold voltage deviation between each of the first test transistors and the first reference transistor on the first test branch includes: Obtain the threshold voltage of each of the first test transistors and the first reference transistor on the first test branch; The threshold voltage of each of the first test transistors is subtracted from the threshold voltage of the first reference transistor, and the average of the differences is taken as the average threshold voltage deviation of the first test branch. And / or, obtaining the average threshold voltage deviation between each of the second test transistors and the second reference transistor on the second test branch includes: Obtain the threshold voltage of each of the second test transistors and the second reference transistor on the second test branch; The threshold voltage of each of the second test transistors is subtracted from the threshold voltage of the second reference transistor, and the average of the differences is taken as the average threshold voltage deviation of the second test branch.

[0015] This application provides a semiconductor test structure and test method. By configuring test transistors and reference transistors with different gate oxide thicknesses in two test branches and connecting each test transistor to a corresponding antenna structure, the degree of damage to the gate oxide caused by the antenna effect is distinguished by utilizing the different sensitivity of different gate oxide thicknesses to breakdown damage. This solves the problems of being unable to identify the degree of gate oxide damage, missed detection, and false detection, and improves the accuracy and reliability of antenna effect monitoring. Attached Figure Description

[0016] Figure 1 The layout of the semiconductor test structure provided in the embodiments of this application.

[0017] Figure 2 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the AA direction.

[0018] Figure 3 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the BB direction.

[0019] Figure 4 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the CC direction.

[0020] Figure 5 A flowchart of a semiconductor testing method provided in an embodiment of this application.

[0021] The attached figures are labeled as follows: T1 - First test transistor; T2 - Second test transistor; R1 - First reference transistor; R2 - Second reference transistor; M1 - First antenna structure; M2 - Second antenna structure; 100 - Substrate; 101 - Gate oxide; 200 - Gate electrode; d1 - First thickness; d2 - Second thickness. Detailed Implementation

[0022] To assess the damage to gate oxide caused by the antenna effect, differential pair-based test structures are commonly used in related technologies. Specifically, a test transistor coupled with an antenna structure and a reference transistor without an antenna are configured to form a differential detection branch. The degree of damage is quantified by measuring the threshold voltage drift caused by the free charge introduced by the antenna structure. The basic working principle is that, because the test transistor is coupled with the antenna structure, the antenna structure collects charge in the plasma environment and directs the charge to the transistor's gate electrode, causing interface trap damage or tunneling / soft breakdown damage within the gate oxide, thus shifting the threshold voltage. The reference transistor, being uncoupled from the antenna, is unaffected by this. Therefore, the threshold voltage deviation between the test transistor and the reference transistor reflects the degree of damage to the gate oxide caused by the antenna effect.

[0023] However, when this test structure is used for online monitoring of advanced deep submicron processes, it cannot accurately distinguish the degree of gate oxide damage. This is because the gate oxide thickness of the test transistor and the reference transistor is the same in the design, while in actual processes, antenna effects can cause two very different forms of degradation: interface trap damage and tunneling / soft breakdown damage. Both types of damage affect the threshold voltage by drift, but interface trap damage is considered mild and usually tolerable, while tunneling / soft breakdown damage is considered fatal and usually unacceptable. For example, if interface trap damage or tunneling / soft breakdown damage occurs in the gate oxide after via deposition or metal etching, the threshold voltage drift detected by this test structure may be on the same order of magnitude, or even lower than the noise caused by process fluctuations. This could lead to fatal damage being misjudged as mild damage or completely missed, resulting in the risk of yield loss not being detected in a timely manner.

[0024] The problem arises because standard-thickness gate oxide lacks sufficient differentiation between its sensitivity to tunneling / soft breakdown damage and its sensitivity to interface trap damage. Since interface trap damage is primarily caused by charge injection into the gate oxide-silicon interface, the resulting threshold voltage drift is less dependent on gate oxide thickness. In contrast, tunneling / soft breakdown damage involves defect generation and leakage path formation within the gate oxide layer. As the gate oxide thickness decreases, the tunneling probability and damage severity increase exponentially, and a single gate oxide thickness scheme cannot utilize this physical difference to separate the two damage levels.

[0025] Based on this, this application proposes a different technical approach. Its core concept is to simultaneously integrate two test branches with different gate oxide thicknesses within a semiconductor test structure. The test branch with the larger gate oxide thickness retains the response to interface trap damage, while the test branch with the smaller gate oxide thickness utilizes its exponentially enhanced sensitivity to tunneling / soft breakdown damage to respond to tunneling / soft breakdown damage. The degree of gate oxide damage is automatically identified by comparing the threshold voltage deviation between the two test branches, thus solving the problem of misjudgment and missed judgment caused by the inability of a single gate oxide thickness to distinguish the degree of damage. This approach maintains common-mode rejection capability while also distinguishing the degree of damage.

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] This application provides a semiconductor test structure that can be integrated into the wafer dicing channel or distributed as an independent test key in the gaps between chip regions for online monitoring of the damage to gate oxide caused by the antenna effect induced by plasma in the back-end process. Figure 1 A layout of a semiconductor test structure provided in one embodiment of this application, such as... Figure 1 As shown, the semiconductor test structure includes a first test branch and a second test branch. The first test branch includes a first reference transistor R1 and n first test transistors T1, and the second test branch includes a second reference transistor R2 and n second test transistors T2, where n≥1. Figure 1 In this configuration, n=1, meaning the first test branch includes a first reference transistor R1 and one first test transistor T1, and the second test branch includes a second reference transistor R2 and one second test transistor T2, but this is not a limitation. In some embodiments, n can also be greater than 1, meaning the first test branch can include more than two first test transistors T1, and the second test branch can also include more than two second test transistors T2, but the number of first test transistors T1 in the first test branch is the same as the number of second test transistors T2 in the second test branch. By setting multiple test transistors in the first and second test branches and performing subsequent averaging, redundancy is provided for the monitoring of antenna effects, which can effectively suppress random process fluctuations and single-transistor measurement noise, and reduce the interference of local process fluctuations (such as line edge roughness and random doping fluctuations) caused by the continuous shrinkage of transistor feature size on the test results.

[0028] Figure 2 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the AA direction. Figure 3 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the BB direction. Figure 4 This is a schematic cross-sectional view of the semiconductor test structure provided in an embodiment of this application along the CC direction. (In conjunction with...) Figures 2-4 As shown, the first test branch and the second test branch are both located on a substrate 100. That is, the first reference transistor R1, the first test transistor T1, the second reference transistor R2 and the second test transistor T2 are all fabricated on the same substrate 100. The substrate 100 can be an intrinsic silicon substrate, a p-type doped silicon substrate, an n-type doped silicon substrate, a silicon-on-insulator (SOI) substrate or a composite substrate with an epitaxial layer.

[0029] In some embodiments, the first test transistor T1, the first reference transistor R1, the second test transistor T2, and the second reference transistor R2 can all be insulated-gate field-effect transistors (IGFETs), each including a source region S and a drain region D formed in the substrate 100, and a gate structure formed on the substrate 100 and located between the respective source region S and drain region D. The gate structure may include a gate oxide 101 and a gate electrode 200 located on the gate oxide 101. The gate oxide 101 of the first test transistor T1 and the first reference transistor R1 has the same thickness, and both have a first thickness d1; the gate oxide 101 of the second test transistor T2 and the second reference transistor R2 also has the same thickness, and both have a second thickness d2, which is less than the first thickness d1. That is, the gate oxide 101 thickness of the second test transistor T2 and the second reference transistor R2 is less than the gate oxide 101 thickness of the first test transistor T1 and the first reference transistor R1.

[0030] Furthermore, the gate electrode 200 of the first test transistor T1 is connected to the corresponding first antenna structure M1. The first antenna structure M1 is a large-area conductive structure that is directly electrically connected to the gate electrode 200 of the first test transistor T1. During the chip manufacturing process, these conductive structures act as antennas to collect free charges in the plasma environment and conduct these charges to the gate oxide 101 of the first test transistor T1 connected to it, thereby simulating the free charges that the transistors in a real working chip should withstand. The gate electrode 200 of the first reference transistor R1 is not connected to any antenna structure for collecting free charges, so that it collects almost no charges during the fabrication process. By comparing the electrical parameters (such as threshold voltage) of the first test transistor T1 and the first reference transistor R1, the common-mode drift caused by other non-antenna effect process factors (such as thermal stress, process gradient, etc.) can be removed, and the changes in electrical parameters caused by the antenna effect can be accurately extracted. Similarly, the gate electrode 200 of the second test transistor T2 is connected to the corresponding second antenna structure M2. The second antenna structure M2 is a large-area conductive structure that is directly electrically connected to the gate electrode 200 of the second test transistor T2. During chip manufacturing, these conductive structures act as antennas to collect ionized charges in the plasma environment and conduct these charges to the gate oxide 101 of the connected second test transistor T2, thereby simulating the ionized charges that the transistors in a real working chip should withstand. The gate electrode 200 of the second reference transistor R2 is not connected to any antenna structure for collecting ionized charges, so that it collects almost no charges during the fabrication process. By comparing the electrical parameters (such as threshold voltage) of the second test transistor T2 and the second reference transistor R2, the common-mode drift caused by other non-antenna effect process factors (such as thermal stress, process gradient, etc.) can be removed, and the changes in electrical parameters caused by the antenna effect can be accurately extracted.

[0031] Understandably, as the primary bearer of antenna effect damage, the degree of damage to gate oxide 101 is closely related to the electric field strength, current density, and physical thickness of the gate oxide 101 itself. For mild interface trap damage, charge carriers generated by high-energy charges will create traps in the gate oxide 101 or at the interface between the gate oxide 101 and the substrate 100. As traps accumulate, the threshold voltage of the transistor (the test transistor in this application) will drift. For fatal tunneling / soft breakdown damage, when the electric field formed by the charge accumulated on the gate oxide 101 is strong enough, charge carriers will tunnel through the gate oxide 101, forming permanent conductive channels or oxygen vacancies inside the gate oxide 101. This will also cause the threshold voltage of the transistor (the test transistor in this application) to drift. However, the thinner the gate oxide 101, the lower the electric field threshold required for tunneling. Therefore, when the gate oxide 101 thickness of a transistor is thinner, its sensitivity to tunneling / soft breakdown damage is higher, and the transistor's sensitivity to tunneling / soft breakdown damage increases exponentially with the reduction in gate oxide 101 thickness, while interface trap damage is relatively less dependent on the gate oxide 101 thickness. Based on this difference in physical mechanism, the gate oxide 101 thickness of the transistors in the first test branch and the second test branch is set to different thicknesses. The first test branch can be understood as a reference branch, and the second test branch can be understood as a sensitive branch. The threshold voltage deviation between the first test transistor T1 and the first reference transistor R1 in the first test branch and the threshold voltage deviation between the second test transistor T2 and the second reference transistor R2 in the second test branch are measured and compared. This allows the damage level information to be decoupled from a single threshold voltage deviation data, which will be explained in detail below.

[0032] In some embodiments, the second thickness d2 is less than half the first thickness d1. That is, the gate oxide 101 thickness of the second reference transistor R2 and the second test transistor T2 is less than half the gate oxide 101 thickness of the first reference transistor R1 and the first test transistor T1. This makes the gate oxide 101 of the second test transistor T2 much more sensitive to tunneling / soft breakdown damage than the gate oxide 101 of the first test transistor T1, thereby improving the accuracy and reliability of gate oxide 101 damage assessment. This numerical limitation is not arbitrarily chosen, but is based on the characteristic that the sensitivity of ultra-thin gate oxide 101 to tunneling / soft breakdown damage increases exponentially. When the second thickness d2 is less than half the first thickness d1, it can be ensured that there is a significant difference between the threshold voltage deviation of the second test branch and the threshold voltage deviation of the first test branch when tunneling / soft breakdown damage occurs, thereby greatly improving the signal-to-noise ratio and determinism of damage assessment.

[0033] In a specific embodiment, the first thickness d1 can be 20 angstroms to 40 angstroms, such as 22 angstroms, 24 angstroms, 26 angstroms, 28 angstroms, 30 angstroms, 32 angstroms, 34 angstroms, 36 angstroms, 38 angstroms, etc. This means that the first test transistor T1 and the first reference transistor R1 adopt the gate oxide thickness that conforms to the deep submicron or nanometer standard logic device or I / O device. The gate oxide performance within this thickness range is stable, the process is mature, and it can exhibit a stable response to interface trap damage under certain plasma stress, thus forming a reliable detection baseline.

[0034] In a specific embodiment, the second thickness d2 can be 10 angstroms to 20 angstroms, such as 11 angstroms, 12.5 angstroms, 13 angstroms, 14 angstroms, 15 angstroms, 16 angstroms, 17 angstroms, 18 angstroms, 19 angstroms, etc. This means that the second test transistor T2 and the second reference transistor R2 adopt ultra-thin gate oxide, and their thickness is close to or equal to the gate oxide thickness of the core logic device under the same process platform. The direct tunneling current of the gate oxide in this thickness range will become dominant, making it extremely sensitive to charge accumulation and dielectric damage in the gate oxide, which can greatly improve the accuracy of detection.

[0035] Please continue to refer to this. Figure 1 n first test transistors T1 and n first reference transistors R1 can be arranged along a first predetermined direction. Adjacent first test transistors T1 (existing when n>1) share a drain region, and adjacent first test transistors T1 and first reference transistors R1 share a source region. Similarly, n second test transistors T2 and n second reference transistors R2 are also arranged along the first predetermined direction. Adjacent second test transistors T2 (existing when n>1) share a drain region, and adjacent second test transistors T2 and second reference transistors R2 share a source region. Sharing a source-drain region is a common technique in layout design to minimize area and eliminate proximity effects. In this test structure, it means that the doped regions of any two adjacent transistors in the first test branch are merged into a single region on the layout. For example, the drain region of the first test transistor T1 also serves as the drain region of an adjacent first test transistor T1; the source region of the first test transistor T1 also serves as the source region of an adjacent first reference transistor R1. This close arrangement of shared active regions ensures that the transistors in each test branch are in almost identical thermal and stress environments, thus making any drift in the threshold voltage more accurately point to antenna effects rather than location-dependent process variations.

[0036] In some embodiments, n first test transistors T1 and n second test transistors T2 are arranged in n columns along a second predetermined direction, and the gate electrodes 200 of the first test transistors T1 and the second test transistors T2 in each column are integral structures. This means that on the layout, the lines of the gate electrodes 200 of the two transistors in each column are connected together and extend continuously (this is a physical direct connection, not a circuit connection). The integral gate electrode 200 eliminates the system mismatch at the microscopic level of gate length and line width caused by proximity effects, micro-load effects, etc. in the polysilicon photolithography and etching process, ensuring that the transistors between the two test branches along the second predetermined direction receive maximum process sharing, which can further avoid the impact of process fluctuations and suppress the mismatch problem caused by process gradients.

[0037] In some embodiments, the first predetermined direction can be understood as a row direction in the layout, and the second predetermined direction can be a column direction orthogonal to it. Of course, in other embodiments, the first predetermined direction and the second predetermined direction can be set perpendicularly according to the layout plan.

[0038] Please continue reading. Figure 1 In some embodiments, the first and second test branches have a symmetrical layout structure, meaning they are mirror-symmetrical in layout shape, area, placement, and surrounding environment. This implies that when the chip experiences a temperature gradient, the two test branches lie on the same isotherm; when there is uneven stress distribution, the two test branches experience the same mechanical stress; and when there is illumination or electromagnetic interference, they experience the same external noise. These common-mode interferences act symmetrically on the two test branches, avoiding the generation of spurious differential signals and effectively canceling out all spatially dependent environmental noise and process deviations. This ensures that the final test results only reflect the different responses to the antenna effect due to the different gate oxide 101 thickness.

[0039] Furthermore, to ensure that the only variable is the thickness of the gate oxide 101, the first antenna structure M1 and the second antenna structure M2 have identical structures and dimensions. This means that at the layout design level, the first antenna structure M1 and the second antenna structure M2 have exactly the same geometry, area, perimeter, number of layers, and constituent materials. This ensures that when exposed to the same plasma environment, the total charge collected by the first antenna structure M1 and the second antenna structure M2 (proportional to their exposed area) is consistent, avoiding the introduction of a contamination variable that would make the final detection results unreliable in determining the degree of damage. For example, the first antenna structure M1 and the second antenna structure M2 can both include a single metal layer of the same material. In this case, the area of ​​the metal layer of the first antenna structure M1 and the second antenna structure M2 needs to be equal. Of course, the first antenna structure M1 and the second antenna structure M2 are not limited to containing only a single metal layer; they can include conductive layers (such as single or multiple metal layers / polycrystalline silicon layers, etc.) and / or conductive vias (tungsten plugs or copper pillars, etc., connecting different conductive layers).

[0040] Based on this, this application also provides a test method using the semiconductor test structure of any of the foregoing embodiments. The semiconductor test method can determine the degree of damage to the gate oxide caused by the antenna effect during the semiconductor manufacturing process through electrical measurement and data analysis. Figure 5 A flowchart of the semiconductor testing method provided in the embodiments of this application is shown below. Figure 5 As shown, the semiconductor testing method includes: Step S100: Obtain the average threshold voltage deviation between each first test transistor and the first reference transistor on the first test branch; Step S200: Obtain the average threshold voltage deviation between each second test transistor and the second reference transistor on the second test branch; and, Step S300: Determine the degree of damage to the gate oxide caused by the antenna effect based on the average threshold voltage deviation between the first test branch and the second test branch.

[0041] Specifically, steps S100 and S200 are executed first. Using a semiconductor parameter analyzer, probe station, and other testing equipment, the first test transistor T1, the first reference transistor R1, the second test transistor T2, and the second reference transistor R2 are tested respectively to obtain the threshold voltages of the first test transistor T1, the first reference transistor R1, the second test transistor T2, and the second reference transistor R2, denoted as Vth_T1, Vth_R1, Vth_T2, and Vth_R2, respectively. When testing the threshold voltage of each transistor, the substrate 100 and the source S of the corresponding transistor are grounded, a small constant voltage is applied to the drain D, and a scanning voltage is applied to the gate electrode 200. The change of drain current with gate voltage is measured, i.e., the transfer characteristic curve. The threshold voltage of each transistor can be extracted using the fixed current method or the maximum transconductance method based on the transfer characteristic curve of each transistor.

[0042] In some embodiments, if n is greater than 1, that is, the first test branch contains more than 2 first test transistors T1 and the second test branch contains more than 2 second test transistors T2, then the threshold voltage of each first test transistor T1 in the first test branch, i.e., n Vth_T1, and the threshold voltage of each second test transistor T2 in the second test branch, i.e., n Vth_T2, can be measured.

[0043] Next, the threshold voltages Vth_T1 of the n first test transistors T1 are subtracted from the threshold voltage Vth_R1 of the first reference transistor R1, resulting in n difference values. These n differences represent the threshold voltage deviations of the first test transistors T1 caused by the antenna effect and local process variations. The average of these n differences is then taken to obtain the average threshold voltage deviation ΔV1 of the first test branch. Similarly, the threshold voltages Vth_T2 of the n second test transistors T2 are subtracted from the threshold voltage Vth_R2 of the second reference transistor R2, resulting in n difference values. These n differences represent the threshold voltage deviations of the second test transistors T2 caused by the antenna effect and local process variations. The average of these n differences is then taken to obtain the average threshold voltage deviation ΔV2 of the second test branch.

[0044] This processing sequence can be summarized as "differential first, then averaging." Its physical essence lies in treating the reference transistor as an intrinsic common-mode noise detector. The test transistors and reference transistors in each test branch are adjacent on the layout; they are adjacent or even share a source region in a first predetermined direction. Therefore, the threshold shifts caused by global or local large-scale process fluctuations such as substrate 100 temperature drift, photolithography focal plane shift, and annealing temperature differences on a pair of devices with the same nominal value are in the same direction and approximately equal in magnitude. Through the "differential" operation, this type of common-mode drift is precisely eliminated at the level of each pair of test and reference transistors. The subsequent "averaging" operation is performed on these differential signals, which have already had common-mode noise eliminated and are purely caused by antenna parasitic effects, aiming to suppress noise caused by subtle random mismatches between test transistors. Compared to averaging the threshold voltages of all test transistors in each test branch and then subtracting them from the threshold voltage of the reference transistor, or subtracting the threshold voltage of only one test transistor from the threshold voltage of the reference transistor, the "differential first, average later" method maximizes the information enrichment capability of redundant test transistors and significantly improves the extraction accuracy and stability of weak PID damage signals.

[0045] Of course, if n=1, that is, the first test branch contains only one first test transistor T1 and the second test branch contains only one second test transistor T2, then the threshold voltage deviation of the first test branch can be obtained by subtracting the threshold voltage Vth_T1 of the first test transistor T1 from the threshold voltage Vth_R1 of the first reference transistor R1, without having to calculate the average threshold voltage deviation of the first test branch; similarly, the threshold voltage deviation of the second test branch can be obtained by subtracting the threshold voltage Vth_T2 of the second test transistor T2 from the threshold voltage Vth_R2 of the second reference transistor R2, without having to calculate the average threshold voltage deviation of the second test branch.

[0046] Further, step S300 is executed to determine the damage degree of the gate oxide 101 based on the average threshold voltage deviations ΔV1 and ΔV2 between the first test branch and the second test branch. Specifically, the ratio of the average threshold voltage deviation ΔV2 of the second test branch to the average threshold voltage deviation ΔV1 of the first test branch is used as the damage coefficient K, where K = ΔV2 / ΔV1.

[0047] The damage factor K is a dimensionless quantity. Physically, it represents the sensitivity factor of an ultrathin gate oxide 101 (gate oxide 101 with a second thickness d2) relative to a standard gate oxide 101 (gate oxide 101 with a first thickness d1) under the same antenna effect. When the external plasma environment causes only slight damage to the interface between the gate oxide 101 and the substrate 100, interface states are introduced into the bandgap, thereby changing the threshold voltage of the transistor. The interface state density is not sensitive to the thickness of the gate oxide 101 itself. Whether the gate oxide 101 has a first thickness d1 or a second thickness d2, as long as an equal amount of interface state density is introduced, the threshold voltage drift of the corresponding first test transistor T1 and the second test transistor T2 will be approximately equivalent. Therefore, if interface trap damage occurs, the average threshold voltage deviations ΔV2 and ΔV1 of the first and second test branches will be very close, and their ratio K will naturally fluctuate around 1.

[0048] When excessive charge accumulates, causing more severe damage to the gate oxide 101 of the second thickness d2 than that of the first thickness d1, or directly inducing tunneling within the gate oxide 101 of the second thickness d2, the threshold voltage drift of the second test transistor T2 will far exceed that of the first test transistor T1. This is because the dependence of tunneling / soft breakdown damage on the thickness of the gate oxide 101 is exponential. Therefore, if tunneling / soft breakdown damage occurs, the average threshold voltage deviations ΔV2 and ΔV1 between the first and second test branches will be large, and their ratio K will also be large. This indicates that the damage is no longer a simple interface trap, but has progressed to a stage where the inherent properties of the gate oxide 101 itself have changed, i.e., tunneling / soft breakdown damage.

[0049] If the K value is small, the average threshold voltage deviation ΔV2 of the first test branch is even much smaller than the average threshold voltage deviation ΔV1 of the first test branch. This usually means that the antenna effect itself is extremely weak and the total amount of charge collected is insufficient to cause substantial damage. A small ratio of K indicates that the antenna effect has not had a significant impact on the gate oxide 101.

[0050] Based on this, when the damage coefficient K is greater than or equal to 0.8 and less than or equal to 1.2 (0.8≤K≤1.2), the damage to the gate oxide 101 is determined to be interface trap damage. At this time, the charge only causes damage at the gate oxide 101 interface, with no risk of breakdown. This is a relatively mild damage that usually does not affect the device's lifespan. When the damage coefficient K is greater than 1.2 (K>1.2), the damage to the gate oxide 101 is determined to be tunneling / soft breakdown damage. At this time, the threshold voltage drift of the transistor in the second test branch is much greater than that of the transistor in the first test branch. Oxygen vacancies and tunneling paths are generated inside the surface gate oxide 101, resulting in pre-breakdown fatal damage. When the damage coefficient is less than 0.8 (K<0.8), the gate oxide 101 is determined to have no significant damage. The threshold voltage drift of the test transistor and the reference transistor originates from factors such as temperature and process fluctuations.

[0051] It should be noted that the thresholds of 0.8 and 1.2 mentioned above are empirical values, which can be adjusted slightly according to specific process and product reliability requirements to further improve the confidence level and applicability of the judgment.

[0052] In addition, after determining the degree of damage to the gate oxide 101 based on the average threshold voltage deviations ΔV1 and ΔV2 between the first test branch and the second test branch, the polarity of the average threshold voltage deviations ΔV1 and ΔV2 between the first test branch and the second test branch can be used to determine the source of damage to the gate oxide 101, thereby tracing the source of damage.

[0053] Specifically, when the average threshold voltage deviations ΔV1 and ΔV2 between the first test branch and the second test branch are both negative, it can be determined that negative charges have accumulated in the first antenna structure M1 and the second antenna structure M2, and the source of the gate oxide 101 damage is the deposition process (such as plasma-enhanced chemical vapor deposition process for filling via structures) during the fabrication of the first antenna structure M1 and the second antenna structure M2; when the average threshold voltage deviations ΔV1 and ΔV2 between the first test branch and the second test branch are both positive, it can be determined that positive charges have accumulated in the first antenna structure M1 and the second antenna structure M2, and the source of the gate oxide 101 damage is the etching process (such as plasma etching process for patterned conductive layers) during the fabrication of the first antenna structure M1 and the second antenna structure M2.

[0054] Understandably, for conventional NMOS transistors, the presence of a fixed negative charge in the gate oxide 101 or at its interface with the substrate 100 will cause the threshold voltage to drift in the positive direction. However, in this application, the polarity determination is based on the antenna structure having already captured charges of a specific polarity. For example, in the deposition process, electrons in the plasma have a much higher mobility than ions, making it easier for them to accumulate negative charges on the outermost conductor surface. This results in the antenna structure carrying a relatively negative potential, which in turn subjectes the connected gate electrode 200 to a negative stress. For the NMOS transistor, this will cause a negative drift in its threshold voltage, i.e., a negative deviation. Therefore, the negative deviation is related to the deposition process. In contrast, in metal or dielectric etching processes, the plasma contains a large number of positive energy ions. High-energy ion bombardment causes the conductor surface to lose electrons and accumulate positive charges, resulting in the antenna structure carrying a relatively positive potential. For the NMOS transistor, this manifests as a positive threshold voltage deviation. Therefore, by determining the positive or negative polarity of the threshold voltage deviation, the suspected process causing the antenna effect can be quickly identified as either an etching or deposition process, thus tracing the source of the damage.

[0055] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0056] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0057] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0058] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor testing structure, characterized in that, include: The first test branch includes a first reference transistor and n first test transistors. The gate oxide of the first test transistor and the first reference transistor both have a first thickness. The gate electrode of the first test transistor is connected to a corresponding first antenna structure. as well as, The second test branch includes a second reference transistor and n second test transistors. The gate oxide of both the second test transistor and the second reference transistor has a second thickness, which is less than the first thickness. The gate electrode of the second test transistor is connected to the corresponding second antenna structure, and n≥1.

2. The semiconductor test structure according to claim 1, characterized in that, The second thickness is less than 1 / 2 of the first thickness.

3. The semiconductor test structure according to claim 2, characterized in that, The first thickness is 20 angstroms to 40 angstroms; and / or, the second thickness is 10 angstroms to 20 angstroms.

4. The semiconductor test structure according to any one of claims 1 to 3, characterized in that, n first test transistors and the first reference transistor are arranged along a first predetermined direction, with adjacent first test transistors sharing a drain region and adjacent first test transistors and the first reference transistors sharing a source region; n second test transistors and the second reference transistors are arranged along the first predetermined direction, with adjacent second test transistors sharing a drain region and adjacent second test transistors and the second reference transistors sharing a source region. And / or, n first test transistors and n second test transistors are arranged in n columns along a second predetermined direction, and the gate electrodes of the first test transistors and the second test transistors in each column are integral structures.

5. The semiconductor test structure according to claim 4, characterized in that, The first test branch and the second test branch have a symmetrical layout structure.

6. The semiconductor test structure according to any one of claims 1 to 3, characterized in that, Both the first antenna structure and the second antenna structure include a conductive layer and / or conductive vias, and the first antenna structure and the second antenna structure have the same structure and dimensions.

7. A testing method utilizing the semiconductor test structure as described in any one of claims 1 to 6, characterized in that, include: Obtain the average threshold voltage deviation between each of the first test transistors and the first reference transistor on the first test branch; Obtain the average threshold voltage deviation between each of the second test transistors and the second reference transistor on the second test branch; as well as, The degree of damage to the gate oxide caused by the antenna effect is determined based on the average threshold voltage deviation between the first test branch and the second test branch.

8. The semiconductor testing method according to claim 7, characterized in that, The determination of the gate oxide damage degree based on the average threshold voltage deviation between the first test branch and the second test branch includes: The ratio of the average threshold voltage deviation of the second test branch to the average threshold voltage deviation of the first test branch is used as the damage coefficient; and, When the damage coefficient is greater than or equal to 0.8 and less than or equal to 1.2, the damage to the gate oxide is determined to be interface trap damage; when the damage coefficient is greater than 1.2, the damage to the gate oxide is determined to be tunneling / soft breakdown damage; when the damage coefficient is less than 0.8, the gate oxide is determined to be without damage.

9. The semiconductor testing method according to claim 7, characterized in that, After determining the degree of gate oxide damage based on the average threshold voltage deviation between the first test branch and the second test branch, the method further includes: The source of gate oxide damage is determined based on the polarity of the average threshold voltage deviation between the first test branch and the second test branch. When the average threshold voltage deviations of the first test branch and the second test branch are both negative, it is determined that negative charges have accumulated in the first antenna structure and the second antenna structure, and the source of gate oxide damage is the deposition process during the fabrication of the first antenna structure and the second antenna structure; when the average threshold voltage deviations of the first test branch and the second test branch are both positive, it is determined that positive charges have accumulated in the first antenna structure and the second antenna structure, and the source of gate oxide damage is the etching process during the fabrication of the first antenna structure and the second antenna structure.

10. The semiconductor testing method according to claim 7, characterized in that, The step of obtaining the average threshold voltage deviation between each of the first test transistors and the first reference transistor on the first test branch includes: Obtain the threshold voltage of each of the first test transistors and the first reference transistor on the first test branch; The threshold voltage of each of the first test transistors is subtracted from the threshold voltage of the first reference transistor, and the average of the differences is taken as the average threshold voltage deviation of the first test branch. And / or, obtaining the average threshold voltage deviation between each of the second test transistors and the second reference transistor on the second test branch includes: Obtain the threshold voltage of each of the second test transistors and the second reference transistor on the second test branch; The threshold voltage of each of the second test transistors is subtracted from the threshold voltage of the second reference transistor, and the average of the differences is taken as the average threshold voltage deviation of the second test branch.

Images