Method for improving physical design antenna effect of unit driving

Abstract

The application discloses a method for improving antenna effect of unit driving solution of physical design, comprising the following steps: querying antenna effect rules and antenna ratio of a process node; numbering all buffers (BUF) in the process node in sequence, calculating the area of the gate oxide layer, and then calculating the area ratio of the gate oxide layer of the buffer (BUF); selecting a process node violating the antenna effect as a path, and calculating a multiple relationship N; based on the calculated multiple relationship N, analyzing the buffer (BUF) in the path violating the antenna effect, and selecting a buffer (BUF) needing to be replaced; replacing the buffer (BUF) needing to be replaced with a corresponding buffer (BUF); and performing antenna effect rule checking to confirm whether the antenna violation is repaired. The application can complete the antenna effect checking and modification of the node at one time, greatly compresses the time consumed when checking the antenna effect of an integrated circuit, and makes the whole circuit design process more efficient.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the driving of cell units to solve the antenna effect in physical design. Background Technology

[0002] In ultra-deep submicron integrated circuit fabrication, a plasma-based ion etching process is commonly used. This technology meets the requirements of continuously decreasing mask etching resolution as dimensions shrink. However, during etching, free charges are generated. When etching conductive metals or polysilicon, the exposed conductor surface collects these free charges, and the amount of accumulated charge is proportional to the area of ​​the conductor exposed to the plasma beam. If the conductor with accumulated charge is directly connected to the device's gate, a tunneling current will form in the thin oxide layer under the polysilicon gate, discharging the charge. When the accumulated charge exceeds a certain amount, this current will damage the gate oxide layer, severely reducing the reliability and lifespan of the device and even the entire chip. During chip manufacturing, exposed metal lines or polysilicon conductors act like antennas, collecting charges, such as charged particles generated by plasma etching, leading to an increase in potential. The longer the antenna, the more charge it collects, and the higher the voltage. This high voltage can potentially break down the thin gate oxide layer, causing circuit failure; this phenomenon is called the antenna effect.

[0003] Antenna effect rules and antenna ratios are provided by wafer manufacturers. They are generally defined as the ratio of the area of ​​the metal layer constituting the antenna to the area of ​​the adjacent gate oxide layer. The antenna ratio measures the probability that a chip will exhibit antenna effects. Common methods for preventing antenna effects on the layout include jumper wiring and adding antenna devices. When the highest metal layer exhibits antenna effects, jumping down cannot solve the problem, thus the jumper wiring method is ineffective. Adding antenna devices requires significant modifications, and it can only raise the threshold to a certain extent, not guarantee a complete solution to the antenna effect. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a method for solving the antenna effect in physical design using a booster unit drive that features a short design cycle and high optimization efficiency.

[0005] The technical solution of this invention to solve the above problems is: a method for improving unit driving to solve the physical design antenna effect, comprising the following steps:

[0006] Step S1: Based on different process nodes, query the antenna effect rules and antenna ratio R of the relevant process nodes;

[0007] Step S2: In the relevant process node project, calculate the area of ​​the gate oxide layer of all buffer BUFs in each process node, and number all buffer BUFs in each process node in order of small to large area. Then calculate the area ratio of the gate oxide layers of two buffer BUFs with a set interval number.

[0008] Step S3: Perform antenna effect rule checks in the design rule checking tool calibre. In the placement and routing tool Innovus, first select a process node that violates the antenna effect as a path, then calculate the metal layer side area S1 that violates the antenna effect. Based on the actual antenna ratio R of the path, obtain the minimum gate oxide area S2 to eliminate the antenna effect. Then, take the area of ​​the buffer BUF gate oxide layer that generates the antenna effect in the path as S3. Finally, calculate the multiple relationship N between S2 and S3.

[0009] Step S4: Based on the calculated multiple relationship N, analyze the buffer BUF in the path that violates the antenna effect and select the buffer BUF that needs to be replaced;

[0010] Step S5: In the placement and routing tool Innovus, replace the buffer BUF that needs to be replaced with the corresponding buffer BUF;

[0011] Step S6: Perform antenna effect rule checks in the design rule checking tool calibre. If the tool's report does not show any antenna effect violations for this path, then the antenna violation is determined to be repaired; otherwise, it is not repaired.

[0012] The above-mentioned method for addressing the physical design antenna effect using a booster unit, specifically step S2, involves the following steps:

[0013] (2-1) Calculate the area of ​​the gate oxide layer of all buffer BUFs in the process node, and use A1, A2, ... A1 in ascending order of area. m This means that m = 1, 2, ..., M;

[0014] (2-2) Number all buffers (BUFs) in the process node in ascending order of area: BUF_X1, BUF_X2, ..., BUF_X m m = 1, 2, ..., M, where M is the total number of buffers;

[0015] (2-3) Let the set interval number sequence be P, P = 1, 2...M-1, then the buffer BUF_X Q+P With buffer BUF_X Q The set of area ratios n = A Q+P / A Q Q = 1, 2, ..., M-1 and P + Q ≤ M, the number of elements ni in the area ratio set n is M(M-1) / 2.

[0016] In the above-mentioned method for solving the physical design antenna effect by boosting unit, the formula for calculating the side area S1 of the metal layer in step S3 is: S1=2*(W+L)*H, where S1 is the side area of ​​the metal layer, W is the width of the metal layer, L is the length of the metal layer, and H is the thickness of the metal layer.

[0017] In the above-mentioned method for solving the antenna effect in physical design driven by the boosting unit, the formula for calculating the minimum gate oxide area S2 for eliminating the antenna effect in step S3 is: S2 = S1 / R.

[0018] In the above-mentioned method for addressing antenna effects in physical design using a booster unit, step S4 first sets the buffer BUF that generates antenna effects in the path that violates the antenna effect as BUF_X. j For j = 1, 2, ..., M, the area of ​​the corresponding gate oxide layer is A. j Then, select A sequentially from the set of area ratios n. j+1 A j+2 …, A M With A j The area ratios are calculated, and then all the obtained area ratios are compared with the multiplier N. When the first area ratio is greater than N, the buffer corresponding to this area ratio is the replacement BUF_X. j buffer.

[0019] The above-mentioned method for addressing the antenna effect in physical design using the boosting unit can simultaneously modify several nodes according to steps S2 to S6 when multiple process nodes violate the antenna effect rules.

[0020] The beneficial effects of this invention are as follows:

[0021] 1. This invention calculates the area of ​​the gate oxide layer of all buffer BUFs in each process node, and numbers all buffer BUFs in each process node in ascending order of area. Then, it calculates the area ratio of the gate oxide layers of two buffer BUFs with a set interval number. This can prevent the operation of repeatedly repairing the antenna due to selecting a buffer unit that is too small, thus increasing unnecessary workload, and can also prevent the area from being wasted due to selecting a buffer unit that is too large.

[0022] 2. When many nodes (such as the data bus) violate the antenna effect, several nodes can be modified simultaneously. The method of improving the unit drive can be directly considered to fix the antenna effect, which can ensure that the antenna effect problem is completely solved.

[0023] 3. The method of improving unit-driven solution to antenna effect in physical design of the present invention can satisfy the antenna effect rules after the modified layout. The antenna effect check and modification of the node can be completed in one go, which greatly reduces the time spent checking the antenna effect of integrated circuits, so as to make the entire circuit design process more efficient. It has the advantages of visual inspection and convenient editing operation.

[0024] 4. The present invention improves the method of solving the antenna effect of physical design by enhancing the unit drive and repairs the antenna effect without changing the winding. This will also repair the antenna effect of the cumulative metal layer type. Attached Figure Description

[0025] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0026] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] like Figure 1 As shown, a method for improving unit driving to solve the antenna effect in physical design includes the following steps:

[0028] Step S1: Based on different process nodes, query the antenna effect rules and antenna ratio R of the relevant process nodes.

[0029] The purpose of querying the antenna effect rules and antenna ratio R of the relevant process node is to understand the antenna effect calculation method and the actual antenna ratio of that process node, so as to calculate the required gate oxide area and accurately eliminate the antenna effect.

[0030] This example uses a 180nm process node. The antenna ratio R in the process library is 400. Cadence's Encounter tool is used to extract parasitic parameters from the layout. The metal side area is calculated based on the perimeter information of the interconnects, i.e., S1 = 2*(W+L)*H, where S1 is the metal layer side area; W is the metal layer width, which is 0.44; L is the metal layer length, which is 744.104538; and H is the metal layer thickness, which is 1.19. According to the formula, the metal layer side area that violates the antenna effect is calculated to be 1772.016.

[0031] Step S2: In the relevant process node projects, calculate the area of ​​the gate oxide layer of all buffer BUFs in each process node, and number all buffer BUFs in each process node in ascending order of area. Then, calculate the area ratio of the gate oxide layers of two buffer BUFs with a set interval number. This operation can prevent the repeated antenna repair operation due to selecting too small a driving unit, which increases unnecessary workload, and can also prevent the area waste due to selecting too large a driving unit.

[0032] The specific steps are as follows:

[0033] (2-1) Calculate the area of ​​the gate oxide layer of all buffer BUFs in the process node, and use A1, A2, ... A1 in ascending order of area. m This means that m = 1, 2, ..., M;

[0034] (2-2) Number all buffers (BUFs) in the process node in ascending order of area: BUF_X1, BUF_X2, ..., BUF_X m m = 1, 2, ..., M, where M is the total number of buffers;

[0035] (2-3) Let the set interval number sequence be P, P = 1, 2...M-1, then the buffer BUF_X Q+P With buffer BUF_X Q The set of area ratios n = A Q+P / A Q Q = 1, 2, ..., M-1 and P + Q ≤ M, the number of elements ni in the area ratio set n is M(M-1) / 2.

[0036] In this example, the gate oxide area of ​​the corresponding buffers is calculated. There are four buffers used: BUF_X1 has a gate oxide area of ​​2.204 (denoted as A1), BUF_X2 has a gate oxide area of ​​4.408 (denoted as A2), BUF_X3 has a gate oxide area of ​​6.612 (denoted as A3), and BUF_X4 has a gate oxide area of ​​8.816 (denoted as A4). Then, the area ratio of the gate oxide layers of the two buffers with the set interval number is calculated. If P=1, then n1=A2 / A1=2.00, n2=A3 / A2=1.50, and n3=A4 / A3=1.33; if P=2, then n4=A3 / A1=3.00 and n5=A4 / A2=2.00. By analogy, n6=A4 / A1=4.00.

[0037] Step S3: Perform antenna effect rule checks in the design rule checking tool calibre. In the placement and routing tool Innovus, first select a process node that violates the antenna effect as a path, then calculate the metal layer side area S1 that violates the antenna effect. Based on the actual antenna ratio R of the path, obtain the minimum gate oxide area S2 to eliminate the antenna effect. Then, take the area of ​​the buffer BUF gate oxide layer that generates the antenna effect in the path as S3. Finally, calculate the multiple relationship N between S2 and S3.

[0038] In this example, the side area of the metal layer S1 = 1772.016, S2 = S1 / R = 4.430265. Since the unit generating the antenna effect is BUF_X1 and its gate oxide layer area is 2.204, that is, S3 = 2.204. Then, it is calculated that N = S2 / S3 = 2.01010209.

[0039] Step S4: Based on the calculated multiple relationship N, analyze the buffer BUF in the path violating the antenna effect and select the buffer BUF to be replaced.

[0040] First, set the buffer BUF generating the antenna effect in the path violating the antenna effect as BUF_X j , j = 1, 2,... M, and the area of the corresponding gate oxide layer is A j , then sequentially select A j+1 , A j+2 …, A M from the area ratio set n, and then compare all the obtained area ratios with the multiple relationship N. When the first area ratio is greater than N, the buffer corresponding to this area ratio is the buffer replacing BUF_X j . j Buffer.

[0041] Based on the calculation results of this example, it is analyzed that n1 = 2.00, N = 2.01010209, n1 < N, n4 = 3.00, N = 2.01010209, N < n4. That is, by selecting BUF_X3 to replace BUF_X1, the antenna effect can be eliminated.

[0042] Step S5: In the layout and routing tool innovus, replace the buffer BUF to be replaced with the corresponding buffer BUF. That is, use the command ecoChangCell - inst{*DOUT

[15] *} - cell BUF_X3, where - inst is the name of the unit with the antenna effect, and - cell is the name of the unit type after replacement.

[0043] Step S6: Perform antenna effect rule checking in the design rule checking tool calibre. If there is no violation of the antenna effect for this path in the report generated by the tool, it is determined that the antenna violation is repaired; otherwise, it is not repaired.

[0044] When multiple process nodes violate the antenna effect rule, select several nodes simultaneously and modify them according to steps S2 to S6.

Claims

1. A method for improving unit driving to solve the antenna effect in physical design, characterized in that, Includes the following steps: Step S1: Based on different process nodes, query the antenna effect rules and antenna ratio R of the relevant process nodes; Step S2: In the relevant process node project, calculate the area of ​​the gate oxide layer of all buffer BUFs in each process node, and number all buffer BUFs in each process node in ascending order of area. Then calculate the area ratio of the gate oxide layers of two buffer BUFs with a set interval number. Step S3: Perform antenna effect rule checks in the design rule checking tool calibre. In the placement and routing tool Innovus, first select a process node that violates the antenna effect as a path, then calculate the metal layer side area S1 that violates the antenna effect. Based on the actual antenna ratio R of the path, obtain the minimum gate oxide area S2 to eliminate the antenna effect. Then, take the area of ​​the buffer BUF gate oxide layer that generates the antenna effect in the path as S3. Finally, calculate the multiple relationship N between S2 and S3. Step S4: Based on the calculated multiple relationship N, analyze the buffer BUF in the path that violates the antenna effect and select the buffer BUF that needs to be replaced; Step S5: In the placement and routing tool Innovus, replace the buffer BUF that needs to be replaced with the corresponding buffer BUF; Step S6: Perform antenna effect rule checks in the design rule checking tool calibre. If the tool's report does not show any antenna effect violations for this path, then the antenna violation is determined to be repaired; otherwise, it is not repaired.

2. The method for solving the physical design antenna effect by driving the lifting unit according to claim 1, characterized in that, The specific process of step S2 is as follows: (2-1) Calculate the area of all buffer BUF gate oxide layers in the process node, and use A1, A2, … A m denotes, m = 1, 2, … M; (2-2) All the buffers in the process node are numbered in ascending order of area, BUF_X1, BUF_X2, …BUF_X m , m = 1, 2, …M, M is the total number of buffers; (2-3) Let the set of interval numbers be P, P = 1, 2, …, M-1, then the buffer BUF_X Q+P The area ratio set n = A Q / A Q+P of the buffer BUF_X Q , Q = 1, 2, …, M-1 and P+Q≤M, the number of elements ni in the area ratio set n is M(M-1) / 2.

3. The method for solving the physical design antenna effect by driving the lifting unit according to claim 2, characterized in that, In step S3, the formula for calculating the side area S1 of the metal layer is: S1=2*(W+L)*H, where S1 is the side area of ​​the metal layer, W is the width of the metal layer, L is the length of the metal layer, and H is the thickness of the metal layer.

4. The method for solving the physical design antenna effect by driving the lifting unit according to claim 3, characterized in that, In step S3, the formula for calculating the minimum gate oxide area S2 to eliminate the antenna effect is: S2 = S1 / R.

5. The method for solving the physical design antenna effect by driving the lifting unit according to claim 3, characterized in that, In step S4, the buffer BUF that generates the antenna effect in the path that violates the antenna effect is first set to BUF_X. j For j = 1, 2, ..., M, the area of ​​the corresponding gate oxide layer is A. j Then, select A sequentially from the set of area ratios n. j+1 A j+2 …, A M With A j The area ratios are calculated, and then all the obtained area ratios are compared with the multiplier N. When the first area ratio is greater than N, the buffer corresponding to this area ratio is the replacement BUF_X. j buffer.

6. The method for solving the physical design antenna effect by driving the lifting unit according to claim 3, characterized in that, When multiple process nodes violate the antenna effect rules, select several nodes and modify them simultaneously according to steps S2 to S6.

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