Protection diode identification, wire winding method, and test chip design method and system

Abstract

The application provides a protection diode identification method, comprising: obtaining a layout, identifying a source-drain doped region; identifying an active region connection line in contact with the source-drain doped region and not in contact with an active region other than the source-drain doped region and not in contact with a gate connection line, i.e. a pin of a protection diode; and identifying the protection diode by identifying the pin of the protection diode. The application can automatically and quickly provide an optional protection diode to avoid an antenna effect. The application also provides a winding method, which obtains the pin of the protection diode by the protection diode identification method, and automatically connects to a gate of a transistor to protect the gate. The test chip design method of the application can automatically and quickly add the protection diode to a transistor type target object by using the winding method, and further improves the design efficiency. The test chip design method, system and test chip have corresponding advantages.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a method for identifying protection diodes, a method for winding transistors to add protection diodes, and corresponding test chips and their design methods and systems. Background Technology

[0002] In chip manufacturing, each metal layer or mask is fabricated and stacked layer by layer. Exposed metal lines or conductors such as polysilicon act like antennas, collecting ionized charges and causing the potential to rise. Ion implantation and etching during manufacturing generate a large amount of this ionized charge; the longer the antenna, the more charge it collects, and the higher the voltage. If this conductor happens to be connected only to the gate of a MOSFET, a FN tunneling current will form in the thin oxide layer under the polysilicon gate to discharge the charge. If a large amount of charge accumulates, the high voltage and large current will damage the gate oxide layer. This can range from minor damage affecting the threshold voltage Vt to severe breakdown causing circuit failure. This phenomenon is generally called the Process Antenna Effect (PAE), also known as plasma-induced gate oxide damage (PID). Especially with advancements in manufacturing processes, gate sizes are shrinking and the number of metal layers is increasing, making the antenna effect more likely. Common protective measures to avoid damage from the antenna effect include jumper wiring. Jumper wiring typically addresses the antenna effect by changing the layers of the metal wiring; however, it also introduces vias. Since vias have high resistance, they directly affect chip timing and crosstalk issues.

[0003] In test chips based on actual products, after the devices under test (DUTs) have been wired, there are still many environmental components—devices without leads—inside the test chip. For transistor-type DUTs, a protection diode is needed to prevent the gate from being damaged by electrostatic discharge (ESD). Therefore, quickly and accurately identifying devices that can act as protection diodes from among the numerous environmental components would provide an effective and feasible solution to the antenna effect problem of transistor-type DUTs.

[0004] Therefore, there is a great need to study a method for identifying protection diodes, a method for adding protection diodes to transistors, and a corresponding test chip design method. This method should be able to quickly and accurately identify devices that can be used as protection diodes, utilize environmental devices without connection leads in the chip to act as protection diodes, solve the antenna effect of transistor-type devices under test, and further promote the in-depth development and widespread application of semiconductor design and manufacturing technology. Summary of the Invention

[0005] This invention aims to solve all or part of the problems of the prior art. One aspect of this invention provides a method for identifying protection diodes, applicable to identifying devices that can function as protection diodes. Another aspect of this invention provides a novel wire-winding method for automatically adding protection diodes to the gate. Based on the protection diode identification method of this invention, as well as a test chip design method, system, and test chip, the wire-winding method of this invention is employed.

[0006] The present invention provides a method for identifying protection diodes, comprising: acquiring a layout and identifying source / drain doped regions; identifying active region connection lines that are in contact with the source / drain doped regions (NSD or PSD) but not in contact with active regions (AA) other than the source / drain doped regions (NSD or PSD) and not in contact with gate connection lines, i.e., the pins of the protection diode; and identifying the protection diode by identifying the pins of the protection diode. By identifying active region connection lines that are in contact with the source / drain doped regions (NSD or PSD) but not in contact with active regions (AA) other than the source / drain doped regions (NSD or PSD) and gate connection lines, the present invention can automatically, quickly and accurately acquire active region connection lines that meet the above conditions in the layout, which can be used as pins of the protection diode. By identifying the pins, the present invention can identify devices that can be used as protection diodes. The method is simple, the results are intuitive, and the identification efficiency is high. It can utilize environmental devices without connection leads in the chip to act as protection diodes, avoiding the waste of unnecessary resources on metal wiring without antenna effect, and does not increase the chip area when using protection diodes.

[0007] In general, the layout includes: an active region layer, a doped layer, an N-well layer, an active region connection layer, a gate connection layer, and a polysilicon layer; wherein, the graphic of the active region layer defines the active region; the graphic of the doped layer defines the doped region; the graphic of the N-well layer defines the N-well region; the graphic of the active region connection layer defines active region connection lines for connecting the active regions; and the graphic of the gate connection layer defines gate connection lines for connecting the gate.

[0008] The steps for identifying the pins of the protection diode include: Step 1. Obtaining the source and drain doped regions in the layout; Step 2. Identifying the active region connection lines that contact the source and drain doped regions, and recording them as target connection lines; Step 3. Among all the target connection lines, excluding those that contact the gate connection line or those that contact active regions other than the source and drain doped regions, the remaining target connection lines are the pins of the protection diode. Automatic identification through graphical processing allows for the automatic and rapid addition of protection diodes, improving efficiency.

[0009] The doped regions include N-type doped regions (SDN) and P-type doped regions (SDP).

[0010] When the protection diode is an N-type protection diode, the source / drain doped region refers to the N-type source / drain doped region (NSD); the identification method of the N-type source / drain doped region includes: obtaining the overlapping part of the active region (AA) and the N-type doped region (SDN), denoted as NAA; obtaining the part of the NAA that does not overlap with the N-well region (NW), which is the N-type source / drain doped region.

[0011] When the protection diode is a P-type protection diode, the source / drain doped region refers to the P-type source / drain doped region (PSD); the identification method of the P-type source / drain doped region includes: obtaining the overlapping part of the active region (AA) and the P-type doped region (SDP), denoted as PAA; obtaining the part of the PAA that overlaps with the N-well region (NW), which is the P-type source / drain doped region.

[0012] In some implementations, when the protection diode is an N-type protection diode, the identified pin is the negative terminal of the N-type protection diode.

[0013] In other implementations, when the protection diode is a P-type protection diode, the identified pin is the positive terminal of the P-type protection diode.

[0014] By targeting different protection diodes, it is possible to identify whether the positive or negative terminal is connected to the gate of the protected transistor according to specific needs. This is more conducive to identifying the protection diodes required for the antenna effect characteristics of different types of transistors in practical applications, thereby further improving the effectiveness of the identification results and the protection effect.

[0015] Another aspect of the present invention provides a transistor wire-winding method for adding a protection diode, comprising: identifying the pins of a protection diode using a protection diode identification method according to one aspect of the present invention, thereby obtaining a protection diode; and simultaneously wire-winding the transistor while connecting the protection diode to the gate of the transistor. By connecting the identified protection diode to the gate while wire-winding the transistor, the antenna effect of the transistor-type device under test is effectively avoided, thereby ensuring that the chip is less prone to failure and improving product yield.

[0016] The transistor winding method for adding a protection diode further includes: determining the transistor type before winding the transistor, and identifying the protection diode accordingly; when the transistor is an NMOS, an N-type protection diode is used; when the transistor is a PMOS, a P-type protection diode is used. Determining and utilizing appropriate protection diodes for different types of transistors provides flexible support solutions for specific situations in practical applications, enabling manufacturers to more effectively utilize protection diodes to avoid antenna effects and optimize existing processes.

[0017] Another aspect of this invention provides a test chip design method, comprising the following steps: Step S1: Input a product chip layout, and obtain objects and their information in the product chip layout based on graphical interpretation; wherein, the product chip layout includes a front-end layer and a back-end layer; Step S2: Create a back-end layer for the test chip, including: arranging several pads on the product chip; selecting several objects as target objects based on the objects and their information obtained in Step S1; capturing the pins of the target objects; assigning pads to the pins of the target objects, and connecting the pins of the target objects to the assigned pads by routing wires; wherein, the routing method includes using the transistor routing method with added protection diodes described in this invention to connect the pins to the assigned pads by routing wires; Step S3: Merge and connect the front-end layer of the product chip layout and the back-end layer of the test chip created in Step S2 to obtain the layout of the test chip. Designing test chips to better meet testing applications in real physical environments is highly beneficial for significantly improving the quality of product chips. In particular, for transistor-type targets, the above-mentioned transistor winding method with added protection diodes can automatically and quickly add protection diodes, improving design efficiency and further refining the design scheme for test chips when the target is transistor-type, which is highly conducive to promoting the further development and application of test chips.

[0018] In step S2, when the target object is a transistor, before connecting the pins of the protection diode to the gate of the target object, it is first determined whether the pins of the protection diode overlap with the pattern in the product chip layout. The pattern refers to the via (V0) and the gate connection line connecting the target object. The via (V0) is used to connect the active area connection line to its adjacent layer connection line or to connect the gate connection line to its adjacent layer connection line. If there is overlap, the via (V0) in the product chip layout is used when connecting the pins of the protection diode to the gate of the target object. By making this pre-judgment, it is possible to reasonably increase the number of vias while making the most of existing vias, avoiding unnecessary increases in vias that could lead to excessive resistance. This helps to minimize potential timing and crosstalk problems in the test chip.

[0019] In step S1, the graphical interpretation includes: using preset feature patterns, matching and identifying corresponding objects based on the feature patterns, and using quantification to characterize object information; the objects include devices and hotspot patterns, where hotspot patterns are structural patterns prone to process defects. By graphically interpreting the layout of a product chip, objects can be automatically and quickly identified and the target objects can be captured based on different testing requirements by matching preset feature patterns.

[0020] In step S1, the object information refers to the feature information that can affect the performance of the object, including information about the object's feature graphics and the environmental information between the object's feature graphics and its surrounding graphics.

[0021] An object database is also established to store the objects and object information obtained in step S1; the object information includes: the object's name, location coordinates, and quantitative characteristic information.

[0022] In step S2, arranging several pads on the product chip includes: on the test chip, arranging multiple pad groups in a staggered manner with two pad groups spaced apart in a first direction to form several pad sequences along the first direction; on both sides of the pad sequence, determining selectable areas of the pads in the pad sequence for connecting the pads to the test object pins in their selectable areas to form test paths; wherein, the pad group is a pad array; the first direction refers to the row direction or column direction of the pad array in the pad group.

[0023] The step of selecting several objects as target objects includes: selecting only objects within the selectable area.

[0024] The pins of the target object include: the terminals of the target object, and a plurality of connecting lines leading out from the terminals; the plurality of connecting lines leading out from the terminals include connecting lines with the same path as the connecting lines in the product chip layout and / or newly created connecting lines.

[0025] In step S2, assigning the pad to the pin includes: selecting the pad closest to the pin from a number of pads that conform to the principle of rotatable linearity for assignment.

[0026] In step S2, assigning the pads to the pins includes: designating two pad groups that are arranged alternately and intermittently as the first pad group and the second pad group, designating the optional area on one side of the pad sequence as the odd-numbered area and the optional area on the other side as the even-numbered area, wherein the odd-numbered area is the optional area of ​​the first pad group and the even-numbered area is the optional area of ​​the second pad group; assigning the pins of the target object located in the odd-numbered area of ​​the pad sequence to the pads of the first pad group in the pad sequence, and assigning the pins of the target object located in the even-numbered area of ​​the pad sequence to the pads of the second pad group in the pad sequence.

[0027] Several winding rules are preset; in step S2, the winding is performed by selecting the corresponding winding rule according to different pins.

[0028] After step S3, the layout of the test chip obtained in step S3 is verified. If the verification is successful, the design of the test chip is completed.

[0029] The present invention also provides a test chip design system, including a storage device; the storage device stores a plurality of instructions, which are adapted to be loaded by a processor and executed by the test chip design method of the present invention.

[0030] This invention also provides a test chip, designed using the test chip design method of this invention. While keeping the front-end and middle-end process layers (i.e., the front-end layer FEOL) of the product chip unchanged, the layout of the test chip can be obtained by modifying the interconnect layer and back-end process layer (i.e., creating a new back-end layer BEOL). The test chip designed in this way is suitable for testing the product chip in a real physical environment. The test chip with a test structure that has the same physical environment as the devices or hotspot patterns in the product chip can significantly optimize test accuracy.

[0031] Compared with the prior art, the main beneficial effects of the present invention are:

[0032] 1. The present invention provides a method for identifying protection diodes, which can automatically and quickly identify protection diodes. To avoid the antenna effect, it provides environmental devices without connection leads in the chip as optional protection diodes. This method is simple, feasible, and can easily and quickly identify protection diodes accurately. It is easy to implement and solves the shortcomings of adding protection diodes to the gate in the prior art to avoid the antenna effect in practice. This method enables practical and efficient implementation, thereby effectively achieving the goal of avoiding the antenna effect. It provides a feasible and more widely applicable solution for optimizing chip manufacturing processes, which is highly beneficial to improving product yield and thus promoting the further development of semiconductor manufacturing technology.

[0033] 2. A winding method of the present invention, wherein the identification method of the present invention connects the protection diode to the gate of the transistor while winding the transistor, can automatically connect to the gate of the transistor, thereby protecting the transistor and even the circuit from the influence of the antenna effect.

[0034] 3. The test chip design method of this invention provides a scheme for designing test chips, thereby better supporting the needs of testing applications in real physical environments and greatly contributing to a significant improvement in the quality level of product chips. Especially for transistor-type targets, the aforementioned transistor winding method for adding protection diodes allows for the automatic and rapid addition of protection diodes, improving the design efficiency of the test chip. Using the winding method of this invention, the pins of the target object are directly connected to the pads, which allows the test chip to cover more test items and conditions while avoiding the impact of antenna effects on the quality and test results of the test chip. This further ensures that the designed test chip is less prone to failure during use and has positive implications for further optimization of the test chip.

[0035] 4. The test chip design system and test chip provided by this invention have corresponding advantages, and provide a positive and effective solution for promoting the further development of actual test technology and the continuous optimization of product manufacturing quality. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the process of identifying the protection diode according to Embodiment 1 of the present invention.

[0037] Figure 2 This is a schematic diagram of the initial layout of Embodiment 1 of the present invention.

[0038] Figure 3 This is a schematic diagram of the NAA in Embodiment 1 of the present invention.

[0039] Figure 4 This is a schematic diagram of the N-type source / drain doped region in Embodiment 1 of the present invention.

[0040] Figure 5 This is a schematic diagram of the target connection line in Embodiment 1 of the present invention.

[0041] Figure 6 This is a schematic diagram of M0A_NSD_valid in Embodiment 1 of the present invention.

[0042] Figure 7 This is a schematic diagram of M0A_NSD_exclude in Embodiment 1 of the present invention.

[0043] Figure 8 This is a schematic diagram of the test chip design method according to Embodiment 2 of the present invention.

[0044] Figure 9 This is a schematic diagram of the arrangement of pads on the original product chip in Embodiment 2 of the present invention.

[0045] Figure 10 This is a schematic representation of the MOSFET object information stored in the object database of Embodiment 2 of the present invention.

[0046] Figure 11 This is a schematic diagram of the object parameters of the MOSFET in Embodiment 2 of the present invention.

[0047] Figure 12 This is a schematic diagram of the staggered placement of two pad groups in Embodiment 3 of the present invention.

[0048] Figure 13 This is a schematic diagram showing the relationship between the pad group and the optional area in Embodiment 3 of the present invention.

[0049] Figure 14 This is a schematic representation of the target MOSFET information during the screening process in Embodiment 3 of the present invention.

[0050] Figure 15 This is a schematic diagram of the target MOSFET pin acquisition process in Embodiment 3 of the present invention.

[0051] Figure 16 This is a schematic diagram of the process of assigning pads to pins in Embodiment 3 of the present invention. Detailed Implementation

[0052] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Example 1

[0054] In Embodiment 1 of this invention, the identification of an N-type protection diode is used as an example for illustration. This embodiment is intended to facilitate understanding of the invention by those skilled in the art, but it does not limit the invention in any way. Figure 1 As shown, the example method for identifying the protection diode specifically includes: Step 1: Obtain the layout and identify the source and drain doped regions. Step 2: Identify the pins of the protection diode to identify it.

[0055] The layout obtained in step one of this embodiment is as follows: Figure 2 As shown, the structure includes an active region layer, a doped layer, an N-well layer, an active region connection layer, a gate connection layer, and a polysilicon layer. The active region layer is graphically defined as the active region, denoted as AA; the doped layer is graphically defined as the doped region, including N-type doped regions (SDN) and P-type doped regions (SDP); the N-well layer is graphically defined as the N-well region, denoted as NW; the active region connection layer is graphically defined as the active region connection line, denoted as MOA in this embodiment, used to connect the active regions; the gate connection layer is graphically defined as the gate connection line, denoted as MOP in this embodiment, used to connect the gate; and the polysilicon layer is graphically defined as polysilicon, denoted as PO.

[0056] In this embodiment, in conjunction with reference Figure 1 The second step may include the following sub-steps:

[0057] Step (1): As Figure 3 As shown, the overlapping portion of the active region AA and the N-type doped region SDN is obtained and denoted as NAA; Figure 4 As shown, the portion of the NAA that does not overlap with the N-well region NW is the N-type source / drain doped region, which is identified as NSD in the figure.

[0058] This example illustrates the identification of an N-type protection diode. In this example, step (1) above obtains the N-type source / drain doped region. In other embodiments for the identification of a P-type protection diode, step (1) will obtain the P-type source / drain doped region (PSD, not shown). NSD and PSD can be collectively referred to as source / drain doped regions. It should be noted that in the identification of PSD, the overlapping portion of the active region AA and the P-type doped region SDP is obtained, denoted as PAA. The portion of PAA that overlaps with the N-well region NW is obtained, which is the P-type source / drain doped region. This is different from the step of obtaining the N-type source / drain doped region. The implementation should be adjusted according to the actual situation, and the specific situation is not limited here.

[0059] Step (2): Identify the active area connection line M0A that is in contact with NSD, and denote it as M0A_NSD, such as Figure 5 As shown.

[0060] Step (3): As Figure 6 As shown, those identified as MOA_NSDs that are in contact with the gate connection line MOP are excluded, and the remaining MOA_NSDs are recorded as MOA_NSD_valid. MOA_NSD_valids that are in contact with other types of active regions AA besides N-type source / drain doped regions NSD are identified and recorded as MOA_NSD_exclude. (Refer to...) Figure 7 As shown. The remaining part after excluding M0A_NSD_exclude in M0A_NSD_valid, i.e., the negative terminal of the required N-type protection diode, is as follows. Figure 7 The N-diode negative electrode in the middle.

[0061] The specific sequence of the second step mentioned above is only an example and does not limit the timing in other specific operational situations.

[0062] In CMOS, the anode of an NDIODE (N-type diode) is a P-type substrate, and the cathode is an N-type doped active region. Because the reverse breakdown voltage of the diode is lower than the gate oxide breakdown voltage, electrostatic discharge preferentially flows through the diode during reverse breakdown. When connecting this N-type diode as a protection diode, the cathode needs to be connected to the gate of the transistor being protected to protect the transistor gate. Therefore, in this embodiment, the identified pin of the protection diode is the cathode. Conversely, for a PDIODE (P-type diode), the anode needs to be connected to the gate of the transistor being protected; therefore, in some other embodiments for identifying P-type protection diodes, the identified pin is the anode.

[0063] This embodiment describes in detail the specific steps for identifying the pins of the protection diode for ease of understanding, but does not impose any limitations on it.

[0064] In this embodiment, based on the aforementioned method for identifying the protection diode, a transistor winding method for adding a protection diode is also provided. The pins of the protection diode are identified using the aforementioned method, thus obtaining the protection diode. The protection diode is connected to the gate of the transistor while the transistor is being wound. The example transistor winding method for adding a protection diode further includes: determining the transistor type before winding the transistor, and identifying the protection diode accordingly based on the transistor type; different types of transistors require different types of protection diodes, such as NMOS requiring an N-type protection diode and PMOS requiring a P-type protection diode.

[0065] Example 2

[0066] This embodiment illustrates a test chip design method, and the test chip design process is as follows: Figure 8 As shown, the process includes: Step S1: Inputting the product chip layout and obtaining the objects and their information in the product chip layout based on graphical interpretation; wherein, the product chip layout includes a front-end layer and a back-end layer; Step S2: Creating the back-end layer of the test chip, including: arranging several pads on the product chip; selecting several objects as target objects based on the objects and their information obtained in Step S1; capturing the pins of the target objects; assigning pads to the pins of the target objects and routing wires to connect the pins of the target objects to the assigned pads; Step S3: Merging and connecting the front-end layer of the product chip layout and the back-end layer of the test chip created in Step S2 to obtain the layout of the test chip. When the transistor is the target object, the routing method in the example can adopt the transistor routing method with added protection diodes in Embodiment 1, and the routing wires connect the pins to the assigned pads.

[0067] It is worth noting that in step S2 of this embodiment, when the target object is a transistor, the above-described transistor winding method for adding a protection diode is used. In the specific implementation of connecting the pins to the assigned pads, when connecting the protection diode pins to the gate of the target object, it is first determined whether the protection diode pins overlap with the following patterns in the product chip layout: a connection hole V0 and a gate connection line M0P connecting the target object. The connection hole V0 is used to connect the active area connection line to its adjacent layer connection line M1 or the gate connection line to its adjacent layer connection line M1. If the determination result is yes, then when connecting the protection diode pins to the gate of the target object, the connection hole V0 in the product chip layout is used; if not, a connection hole V0 is added to the protection diode pins, and a winding layer is automatically connected to the gate of the target object. At this point, the addition of the protection diode to the gate is complete. By reasonably increasing the connection hole V0 and using the original connection hole V0 as much as possible, the risk of timing or crosstalk problems in the designed test chip is reasonably avoided.

[0068] In step S1 of this embodiment, the graphical interpretation includes: using preset feature patterns, identifying corresponding objects based on feature pattern matching, and using quantization to characterize the corresponding object information; the objects include devices and hotspot patterns. Hotspot patterns are structural patterns prone to process defects (such as photolithography defects), and examples include interconnect structures, active areas (AA), and single diffusion breaks (SDB). Example devices may include MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), diodes, BJTs (Bipolar Junction Transistors), resistors, capacitors, inductors, and SRAM (Static Random Access Memory). In this embodiment, the situation after arranging pads on the original product chip is as follows... Figure 9 As shown.

[0069] In step S1 of the example, object information refers to feature information that can affect object performance, including information about the object's feature graphics and environmental information between the object's feature graphics and its surrounding graphics. Environmental information includes, for example, relative distance information. In this embodiment, an object database is also established to store the objects and object information obtained in step S1. Figure 10 The object information shown includes: the object's name, location coordinates, and characteristic information of various quantitative representations.

[0070] Below is a specific example of how to identify and obtain object information using MOSFETs as an example. Based on the MOSFET type, two preset feature patterns are used to identify MOSFETs: N-type MOSFET: The N-type gate (ngate) has edges that contact the N-type source and drain (NSD) on both sides, and a P-type body (ptap) is present in the non-NWELL region. P-type MOSFET: The P-type gate (pgate) has edges that contact the P-type source and drain (PSD) on both sides, and an N-type body (ntap) is present in the NWELL region. Examples of the MOSFET device-related pattern definitions for the above feature patterns are as follows. N-type active region: ndiff = ((AA and NIMP) not PIMP) not NWELL; P-type active region: pdiff = ((AA and PIMP) not NIMP) and NWELL; N-type gate: ngate = (POLY not EG) and ndiff; P-type gate: pgate = (POLY not EG) and pdiff; N-type source and drain: NSD = ndiff not POLY; P-type source and drain: PSD = pdiff not POLY; N-type body: ntap = ((AA and NIMP) not PIMP) and NWELL; P-type body: ptap = ((AA and PIMP) not NIMP) not NWELL. The basic graphic definitions involved in the above-mentioned feature patterns are exemplified below: POLY—polysilicon layer; POLYCUT—polysilicon removal layer; EG—edge gate marker layer; AA—active layer; NIMP—N-type implantation layer; PIMP—P-type implantation layer; NWELL—N-well layer; PSUB—P-substrate; IOMK—thick device marker layer. In this embodiment, the defined MOSFET's intrinsic characteristic parameters and surrounding environmental parameters can be referenced. Figure 11 Examples include L, W, DPL11, DPL12, SA, SB, PEEU, etc., and the specific cases are not limited here.

[0071] Example 3

[0072] This embodiment provides a detailed example of some specific practices in step S2. In this embodiment, arranging several pads on the product chip includes: setting up pad groups, where each pad group is a pad array; the preset interval values ​​for adjacent pads in the pad group in the row and column directions are denoted as pitchX and pitchY, respectively; arranging several pad groups on the product chip, with the pads of adjacent pad groups arranged in an alternating manner in the row or column direction. The preset values ​​for the design dimensions of the pads in the row and column directions are denoted as sizeX and sizeY, respectively. Specifically... Figure 12 As shown, the pad group is a 48×2 pad array, with pads from every two pad groups arranged interleaved in the Y direction. Approximately 232 pad groups can be placed within the chip area (approximately 9mm×9mm), for a total of 22,272 pads. There are four repeating rows for the pad groups in the Y direction and fifty-eight repeating columns in the X direction. The row and column directions can be X and Y, or Y and X, respectively. Figure 12 This is for illustrative purposes only and does not limit the specific arrangement of rows and columns.

[0073] In step S2 of this embodiment, selecting several objects as target objects includes filtering only from objects within the selectable region. The selectable region is the area on both sides of the pad sequence where the pads of two adjacent pad groups are arranged with alternating spacing, that is, the area on both sides of each column of pad sequence arranged along the Y direction in the example. The selectable region can be referenced. Figure 13 DeviceArea, Figure 13 The pad group in the middle represents the pad group.

[0074] The example uses preset filtering rules for the filtering process. Step S2 further includes selecting applicable filtering rules for different objects to obtain target objects. The example sets the priority order of the selected filtering rules according to the actual application requirements of the test chip, and then applies the filtering rules in order of priority to filter out several suitable objects as target objects. The example has over 30 preset filtering rules covering MOSFETs, BJTs, DIODEs, resistors, capacitors, SRAMs, hotspots, etc. The following example uses a MOSFET filtering rule: for various types of MOSFETs in the DEVICETYPE, target devices that meet the requirements are selected according to the minimum and maximum values ​​of the basic parameters W and L. The example's filtering rules are interested in these selected target devices, covering the extreme values ​​(minimum and maximum values) of the W and L ranges of various MOSFETs in the product chip, used for monitoring the ProcessWindow. The parameters of the selected target devices can be found in Table 1 below.

[0075] Table 1. Parameters of the Selected Target Device

[0076]

[0077] In the general operation of this embodiment, three sample devices are randomly selected from the candidate devices that meet the screening rules and are of sufficient quantity. If the number of candidate devices that meet the screening rules is less than three, all of them are selected first. The screening rules select a total of the following: Figure 14 The twenty target devices shown.

[0078] In step S2 of this embodiment, the pins of the target object include: terminals of the target object, and several connecting lines leading out from the terminals. For example... Figure 15 As shown, the example automatically identifies and captures the four terminals of the MOSFET: gate, source, drain, and body. Metal leads for these four terminals are then created, and processing is performed to conform to design rules, optimizing the pin routing directions to ensure the four pins exit from four different directions, making subsequent wiring steps easier. Because the actual location of the body is relatively far, [the following steps are not explicitly stated]. Figure 9 Only the automatic identification and capture results of the gate, source, and drain are shown, and only the back-end layer is retained. In some cases, the connection lines brought out from the terminals include connection lines with the same path as the connection lines in the original product chip layout and / or newly created connection lines. It is preferable to use connection lines with the same path as the connection lines in the original product chip layout, but this is not a limitation.

[0079] In this embodiment, assigning pads to the pins of a target object includes: designating two pad groups arranged in an alternating pattern as the first pad group and the second pad group; designating the optional area on one side of the pad sequence as the odd-numbered area and the optional area on the other side as the even-numbered area. The odd-numbered area is the optional area of ​​the first pad group, and the even-numbered area is the optional area of ​​the second pad group. Pins of the target object located in the odd-numbered area of ​​the pad sequence are assigned to the pads of the first pad group in that pad sequence, and pins of the target object located in the even-numbered area of ​​the pad sequence are assigned to the pads of the second pad group in that pad sequence. For the optional areas, refer to... Figure 12 and Figure 13 , Figure 12 Two pad groups, Pad Group I and Pad Group II, are arranged alternately in the Y direction. The optional area on the left side of the pad sequence arranged along the Y direction is designated as the Left Optional Area of ​​Pad Group I, and the optional area on the right side of the pad sequence is designated as the Right Optional Area of ​​Pad Group II. During allocation, pads belonging to Pad Group I are matched with pins of target objects within the Left Optional Area of ​​Pad Group I of their respective pad sequences, and pads belonging to Pad Group II are matched with pins of target objects within the Right Optional Area of ​​Pad Group II of their respective pad sequences.

[0080] In step S2 of this embodiment, assigning pads to pins includes selecting the pad closest to the pin from a number of pads that conform to the principle of linearity. That is, when assigning pads to the pins of the target object, the following are followed: 1) Assigning according to the principle of proximity and linearity, where linearity includes that the pad can be wound around the pin, and that all pins are wound around as a whole; 2) Assigning pins of the target object only to the pads within their selectable area.

[0081] In this embodiment, several winding rules are preset. In step S2, the winding is performed by selecting the corresponding winding rule according to different pins. When winding the pins of the target object to the assigned pads, the corresponding winding rule is automatically selected for automatic winding based on different pins (such as general pins, pins sensitive to voltage drop caused by current, etc.).

[0082] In this embodiment, for Figure 15The system automatically winds the four pins of the target MOSFET device: gate, source, drain, and body. The body pin will share the bottom pad with other similar devices, while the remaining three pins will be assigned pads based on flexibility and proximity. Figure 16 The pad assignments are as follows: Gate G is assigned to PAD_92; Drain D is assigned to PAD_94; Source S is assigned to PAD_96; Body B is assigned to PAD_2 (shared bottom pad); the MOSFET is located within the selectable area corresponding to the pad groups of PAD_92, PAD_94, and PAD_96. During wiring, Gate G and Body B use single wiring, while Drain D and Source S use large-area mesh wiring to reduce IR drop.

[0083] In this embodiment, step S2 further includes deleting the back-end layer (conductive interconnect layer) of the product chip. After step S3, the test chip is verified, for example, by verifying compliance with design rules using DRC and ensuring the back-end wiring connections meet requirements using LVS. If the verification is successful, the design of the test chip is complete, resulting in a high-precision built-in test chip for monitoring the yield and performance of the product chip. The test chip provided in this embodiment selects approximately 6200 target objects within the product chip area, and directly connects the measurement pins of the target objects to adjacent pads. This improves area utilization and, through direct pin connection to pads, covers more test items and conditions.

[0084] This embodiment also provides a test chip design system, including a storage device. The storage device stores multiple instructions adapted for loading and execution by a processor using the test chip design method of this embodiment.

[0085] This embodiment also provides a test chip, which is designed using the test chip design method of this embodiment.

[0086] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

Claims

1. A method for identifying protection diodes, characterized in that: include: Obtain the layout and identify the source and drain doped regions; The active region connection line that is in contact with the source / drain doped region but not in contact with the active region other than the source / drain doped region and not in contact with the gate connection line is identified, i.e., the pin of the protection diode; the protection diode is identified by identifying the pin of the protection diode. The source / drain doped regions include N-type source / drain doped regions and P-type source / drain doped regions.

2. The method for identifying protection diodes according to claim 1, characterized in that: The layout includes: an active region layer, a doped layer, an N-well layer, an active region connection layer, a gate connection layer, and a polysilicon layer; wherein, the graphic of the active region layer defines the active region; the graphic of the doped layer defines the doped region; the graphic of the N-well layer defines the N-well region; the graphic of the active region connection layer defines active region connection lines for connecting the active regions; and the graphic of the gate connection layer defines gate connection lines for connecting the gate.

3. The method for identifying protection diodes according to claim 1, characterized in that: The steps for identifying the pins of the protection diode include: Step 1. Obtain the source and drain doped regions in the layout; Step 2. Identify the active region connection lines that are in contact with the source / drain doped regions, and denote them as target connection lines; Step 3. Among all the target connection lines, exclude those that are in contact with the gate connection line or the active region other than the source / drain doped region. The remaining target connection lines are the pins of the protection diode.

4. The method for identifying a protection diode according to any one of claims 1 to 3, characterized in that: When the protection diode is an N-type protection diode, the source / drain doped region refers to the N-type source / drain doped region; The identification method of the N-type source / drain doped region includes: obtaining the overlapping part of the active region and the N-type doped region, denoted as NAA; obtaining the part of the NAA that does not overlap with the N-well region, which is the N-type source / drain doped region.

5. The method for identifying a protection diode according to any one of claims 1 to 3, characterized in that: When the protection diode is a P-type protection diode, the source / drain doped region refers to the P-type source / drain doped region; The identification method of the P-type source / drain doped region includes: obtaining the overlapping part of the active region and the P-type doped region, denoted as PAA; obtaining the part of the PAA that overlaps with the N-well region, which is the P-type source / drain doped region.

6. The method for identifying a protection diode according to claim 4, characterized in that: When the protection diode is an N-type protection diode, the identified pin is the negative terminal of the N-type protection diode.

7. The method for identifying a protection diode according to claim 5, characterized in that: When the protection diode is a P-type protection diode, the identified pin is the positive terminal of the P-type protection diode.

8. A method for winding a transistor with a protective diode, characterized in that: include: The pins of the protection diode are identified by the identification method described in any one of claims 1-7, thereby obtaining the protection diode; The protection diode is connected to the gate of the transistor while the transistor is being wound.

9. The transistor winding method with added protection diode according to claim 8, characterized in that: Before winding the transistor, the transistor type is determined, and the corresponding protection diode is identified based on the transistor type; when the transistor is an NMOS, an N-type protection diode is used; when the transistor is a PMOS, a P-type protection diode is used.

10. A test chip design method, characterized in that: Includes the following steps: Step S1: Input the product chip layout and obtain the objects and their information in the product chip layout based on graphical interpretation; wherein, the product chip layout includes a front-end layer and a back-end layer; Step S2: Create a back-end layer for the test chip, including: arranging several pads on the product chip; selecting several objects as target objects based on the objects and object information obtained in step S1; capturing the pins of the target objects; assigning pads to the pins of the target objects, and connecting the pins of the target objects to the assigned pads by wire routing; wherein the wire routing method includes the transistor wire routing method with added protection diodes as described in any one of claims 8-9; Step S3: Merge and connect the front layer of the product chip layout and the back layer of the test chip created in step S2 to obtain the layout of the test chip.

11. The test chip design method according to claim 10, characterized in that: In step S2, when the target object is a transistor, when connecting the pin of the protection diode to the gate of the target object, it is first determined whether the pin of the protection diode overlaps with the pattern in the product chip layout. The pattern refers to the connecting hole and the gate connection line connecting the target object; wherein, the connecting hole is used to connect the active region connection line to its adjacent layer connection line or to connect the gate connection line to its adjacent layer connection line; If there is overlap, the connection hole in the product chip layout is used when connecting the pin of the protection diode to the gate of the target object.

12. The test chip design method according to claim 10, characterized in that: In step S1, the graphical interpretation includes: using preset feature patterns, matching and identifying corresponding objects based on the feature patterns, and using quantitative representation to characterize object information; the objects include devices and hotspot patterns, where hotspot patterns are structural patterns that are prone to process defects.

13. The test chip design method according to claim 10, characterized in that: In step S1, the object information refers to the feature information that can affect the performance of the object, including information about the object's feature graphics and the environmental information between the object's feature graphics and its surrounding graphics.

14. The test chip design method according to any one of claims 10-13, characterized in that: An object database is also established to store the objects and object information obtained in step S1; the object information includes: the object's name, location coordinates, and quantitative characteristic information.

15. The test chip design method according to claim 10, characterized in that: In step S2, arranging several pads on the product chip includes: on the test chip, arranging multiple pad groups in a staggered manner with two pad groups spaced apart in a first direction to form several pad sequences along the first direction; on both sides of the pad sequence, determining selectable areas of the pads in the pad sequence for connecting the pads to the test object pins in their selectable areas to form test paths; wherein, the pad group is a pad array; the first direction refers to the row direction or column direction of the pad array in the pad group.

16. The test chip design method according to claim 15, characterized in that: The step of selecting several objects as target objects includes: selecting only objects within the selectable area.

17. The test chip design method according to claim 10, characterized in that: Several filtering rules are preset; in step S2, filtering out several objects as target objects also includes selecting applicable filtering rules for different objects to filter and obtain target objects.

18. The test chip design method according to claim 10, characterized in that: The pins of the target object include: the terminals of the target object, and a plurality of connecting lines leading out from the terminals; the plurality of connecting lines leading out from the terminals include connecting lines with the same path as the connecting lines in the product chip layout and / or newly created connecting lines.

19. The test chip design method according to claim 10, characterized in that: In step S2, assigning the pad to the pin includes: selecting the pad closest to the pin from a number of pads that conform to the principle of rotatable linearity for assignment.

20. The test chip design method according to claim 10, characterized in that: In step S2, assigning the pads to the pins includes: designating two pad groups that are arranged alternately and intermittently as the first pad group and the second pad group, designating the optional area on one side of the pad sequence as the odd-numbered area and the optional area on the other side as the even-numbered area, wherein the odd-numbered area is the optional area of ​​the first pad group and the even-numbered area is the optional area of ​​the second pad group; assigning the pins of the target object located in the odd-numbered area of ​​the pad sequence to the pads of the first pad group in the pad sequence, and assigning the pins of the target object located in the even-numbered area of ​​the pad sequence to the pads of the second pad group in the pad sequence.

21. The test chip design method according to claim 10, characterized in that: Several winding rules are preset; in step S2, the winding is performed by selecting the corresponding winding rule according to different pins.

22. The test chip design method according to claim 10, characterized in that: After step S3, the layout of the test chip obtained in step S3 is verified. If the verification is successful, the design of the test chip is completed.

23. A test chip design system, characterized in that: Includes a storage device; the storage device stores multiple instructions adapted for loading and execution by a processor of the test chip design method according to any one of claims 10-22.

24. A test chip, characterized in that: The test chip was designed using the test chip design method described in any one of claims 10-22.

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