Determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design

Abstract

A method for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design is provided. The 3DIC design includes at least two electrically connected circuit components. A first circuit component of the circuit components includes at least one first sub-circuit. A second circuit component of the circuit components includes at least one interposer and / or at least one second sub-circuit. The respective sub-circuit includes one or more metal layers and at least one gate. The respective interposer includes at least one metal layer. The method includes providing the 3DIC design and determining at least one geometric property of at least one representative metal layer of the respective circuit component using the 3DIC design. The respective geometric property of the at least one representative metal layer is representative of the respective circuit component with respect to an antenna effect of the respective circuit component. The method includes determining a stacked arrangement of the representative metal layers representing the respective circuit components, determining a stacked antenna effect value of the stacked arrangement using the geometric properties of the representative metal layers, and outputting that the integrated circuit design has a process deficiency if the stacked antenna effect value exceeds a preconfigurable threshold

Description

DETERMINING A PROCESS DEFICIENCY RELATING TO AN ANTENNA EFFECT OF A THREE-DIMENSIONAL INTEGRATED CIRCUIT (3DIC) DESIGNTECHNICAL FIELD

[0001] The present disclosure is directed, in general, to electronic design automation (EDA) and, more specifically, to the determination of a process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design. Such electronic design automation systems and process deficiency systems are collectively referred to herein as product systems.BACKGROUND ART

[0002] The development of electronic devices with electronic circuits typically involves many steps known as a design flow. This design flow typically starts with a specification for a new electronic device to be implemented with an electronic circuit, such as an integrated circuit (IC). The specification of the electronic device may be transformed into an electronic device design, such as anetlist, for example, by a schematic capture tool or by synthesizing a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic device. The netlist may be specified in an Electronic Design Interchange Format (EDIF) or the like, which may describe nets or connectivity between various components or parts in the electronic device design.

[0003] The design flow may continue by verifying functionality of the electronic device design, for example, by simulating, emulating, or prototyping the electronic device design and verifying that the results of the simulation or emulation correspond with an expected output from the electronic device design. The functionality may also be verified by formally verifying with one or more solvers or statically checking the electronic device design for various attributes that may be problematic during operation of the electronic device built utilizing the electronic device design.

[0004] Once the electronic device design has been functionally verified, the design flow may utilize the logical design to generate a layout design for the electronic device. This procedure may be implemented in different ways, but typically, through the use of a layout tool, which may place and interconnect various components or parts into a representation of an electronic circuit. For example, the layout tool implemented in a computing system may present a graphical view of the electronic circuit and allow a designer to utilize the layout tool to place parts from a library onto the electronic circuit in the graphical view.

[0005] The layout of the electronic circuit may then physically be verified (e.g. to address functional yield challenges in IC designs or process deficiency that may occur during themanufacture of IC designs). Such a physical verification helps to provide accurate circuit behavior with precise device parameters, while being manufacturable with a desired quality and manufacture yield. In some respects, the present patent disclosure primarily focusses on the physical verification of an electronic circuit layout (e.g., the identification of a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design).

[0006] Currently, there exist product systems and solutions that support determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design. Such product systems may benefit from improvements.SUMMARY OF INVENTION

[0007] Variously disclosed embodiments include methods and computer systems that may be used to facilitate determining a process deficiency relating to an antenna effect of a three- dimensional integrated circuit design.

[0008] According to a first aspect of the invention, a computer-implemented method for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design is provided. The integrated circuit design may include at least two electrically connected circuit components. A first circuit component of the circuit components may include at least one first sub-circuit. A second circuit component of the circuit components may include at least one interposer and / or at least one second sub-circuit. The respective sub-circuit may include one or more metal layers and at least one gate. The respective interposer may include at least one metal layer. The suggested method may include: providing the integrated circuit design; determining at least one geometric property of at least one representative metal layer of the respective circuit component using the integrated circuit design, where the respective geometric property of the at least one representative metal layer is representative of the respective circuit component with respect to an antenna effect of the respective circuit component; determining a stacked arrangement of the representative metal layers representing the respective circuit components; determining a stacked antenna effect value of the stacked arrangement using the geometric properties of the representative metal layers; and outputting that the integrated circuit design has a process deficiency if the stacked antenna effect value exceeds a preconfigurable threshold.

[0009] According to a second aspect of the invention, a computer system may be arranged and configured to execute the steps of this computer-implemented method according to the first aspect.

[0010] According to a third aspect, a computer program product may include computer program code that, when executed by the computer system according to the second aspect,causes the computer system to carry out the method according to the first aspect.

[0011] According to a fourth aspect, a computer-readable medium may include the computer program product according to the third aspect. By way of example, the described computer- readable medium may be non-transitoiy and may further be a software component on a storage device.

[0012] The foregoing has outlined rather broadly the technical features of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiments disclosed as a basis for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design or for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0013] Also, before undertaking the detailed description below, it should be understood that various definitions for certain words and phrases are provided throughout this patent document and those of ordinary' skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0014] Embodiments will be described below in greater detail.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1-3 depict a functional block diagram of example systems that facilitate determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system, respectively.

[0016] Figures 4-5 depict different aspects of various example methodologies that facilitate determining a process deficiency’ relating to an antenna effect of a three-dimensional integrated circuit design in a product system, respectively.

[0017] Figures 6-8 depict further aspects relating to further example methodologies that facilitate determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system, respectively.

[0018] Figures 9-11 depict a flow diagram of an example methodology that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system, respectively.

[0019] Figure 12 depicts a block diagram of a data processing system in which an embodiment may be implemented.DETAILED DESCRIPTION

[0020] Various technologies that pertain to systems and methods for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system will now be described with reference to the drawings, where like reference numerals represent like elements throughout. The drawings discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged apparatus. It is to be understood that functionality that is described as being carried out by certain system elements may be performed by multiple elements. Similarly, for example, an element may be configured to perform functionality that is described as being carried out by multiple elements. The numerous innovative teachings of the present patent document will be described with reference to exemplary non-limiting embodiments.

[0021] With reference to Figure 1, a functional block diagram of a first example computer system or data processing system 100 that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100 is depicted. The processing system 100 may include an integrated circuit (IC) verification (ICV) system 118 that may, in some examples, include at least one processor 102 that is configured to execute at least one application software component 106 from a memory 104 accessed by the processor 102. The application software component 106 may be configured (e.g., programmed) to cause the processor 102 to cany7out various acts and functions described herein. For example, the described application software component 106 may include and / or correspond to one or more components of an application for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120, where the application software component 106 may, for example, be configured to generate and store product data in a data store 108 such as a database.

[0022] By way of example, the ICV system 118 may be cloud-based, internet-based, and / or be operated by a provider providing support for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120. In some examples, the user may be located close to the ICV system 118 or remote to the ICV system 1 18 (e.g., anywhere else; using a mobile device for connecting to the ICV system 118; via the internet), where themobile device may include an input device 110 and a display device 112. In some examples, the ICV system 118 may be installed and run on a user’s device, such as a computer, laptop, pad, on-premises computing facility, or the like.

[0023] It should be appreciated that determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 may be a challenging and timeconsuming process that may require highly skilled engineers with many years of training. For example, advanced knowledge in electronics, physics, and other scientific domains may be required. Further, in some examples, tools available for two-dimensional integrated circuit design may fail or not be able to reliably determine a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120. Hence, determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 may be a long and not efficient process.

[0024] To enable the enhanced determination of a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 1 12 (e g., a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 through the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, scroll bars usable by a user to provide inputs through the input device 110 that cause determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120. By way of example, the GUI 114 may include an ICV user interface (UI) 116 provided to a user.

[0025] In an example embodiment, a process deficiency relating to an antenna effect of a three- dimensional integrated circuit design 120 (e g., an integrated circuit design) may be determined, where the integrated circuit design 120 may include at least two electrically connected circuit components 124, 128. A first circuit component 124 of the circuit components 124, 128 may include at least one first sub-circuit. A second circuit component 128 of the circuit components 124, 128 may include at least one interposer and / or at least one second sub-circuit. The respective sub-circuit may include one or more metal layers 130 and at least one gate 132. The respective interposer may include at least one metal layer 130. Herein, the application software component 106 and / or the processor 102 may be configured to provide the integrated circuit design 120.

[0026] A three-dimensional integrated circuit (3DIC) may, for example, be a metal-oxide semiconductor (MOS) integrated circuit (IC) manufactured by stacking as many as 16 or more ICs and interconnecting the ICs vertically using, for example, through-silicon vias (TSVs) or Cu-Cu connections, so that the ICs behave as a single device to achieve performanceimprovements at reduced power and smaller footprint than conventional two-dimensional processes. The 3DIC is one of a number of (e.g., several) 3D integration schemes that exploit the z-direction to achieve electrical performance benefits in microelectronics and nanoelectronics. 3D integrated circuits may be classified by their level of interconnect hierarchy at the global (e.g., package), intermediate (e.g., bond pad), and local (e.g., transistor) level. In general, 3D integration is a broad term that may. for example, include such technologies as: 3D wafer-level packaging (3DWLP); 2.5D and 3D interposer-based integration; 3D stacked ICs (3D-SICs); 3D heterogeneous integration; and 3D systems integration; as well as true monolithic 3D ICs. In some examples, the three-dimensional integrated circuit design 120 may be understood as a three-dimensional integrated circuit layout.

[0027] Further, the antenna effect, more formally plasma induced gate oxide damage, may be understood as an effect that may potentially cause yield and reliability problems during the manufacture of integrated circuits, such as MOS integrated circuits. In some examples, the gate dielectric may be so thin (e.g., a few molecules thick) that a big worry is breakdown of this layer. This may, for example, happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip. In some examples, factories (e g., fabs) may supply antenna rules for two-dimensional ICs, where these antenna rules are to be obeyed to avoid this problem. A violation of such rules is referred to as an antenna violation. The word antenna is something of a misnomer in this context; the problem is really the collection of charge, not the normal meaning of antenna, which is a device for converting electromagnetic fields to / from electrical currents. As already mentioned above, determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 may still be a challenging and time-consuming process.

[0028] The three-dimensional integrated circuit design 120 may, for example, include a first circuit component 124 and a second circuit component 128 that are electrically connected via an electric connection 126. Herein, the respective circuit component 124, 128 may be or include a respective sub-circuit, such as a die. A die, in the context of integrated circuits, may be understood as a small block of semiconducting material on which a given functional circuit is fabricated. Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (such as GaAs) through processes such as photolithography. The wafer is cut (e.g., diced) into many pieces, each containing one copy of the circuit. Each of these pieces is referred to as a die. The second circuit component 128 may. additionally or alternatively to a second sub-circuit, include an interposer that may, for example, be understood as an electrical interface routing between one socket or connection to another. The purpose of an interposer is to spread a connection to a wider pitch or to reroute a connection to adifferent connection.

[0029] The respective sub-circuit may include at least one gate 132 (e.g., of a field-effect transistor (FET), which is a type of transistor that uses an electric field to control the flow of current in a semiconductor). Herein, FETs have three terminals: source, gate 132, and drain. FETs control the flow of an electric current by the application of a voltage to the gate 132, which in turn alters the conductivity between the drain and the source.

[0030] In some examples, the integrated circuit design 120 may involve that the integrated circuit design 120 may be determined by a user or engineer. The integrated circuit design 120 may be provided and stored in the data store 108 of the ICV system 118 (e.g., by the user using the ICV UI 116 and / or the input device 110). In some examples, the integrated circuit design 120 may be received (e.g., via an application programming interface (API)) from another data source 108’. By way of example, the integrated circuit design 120 may include information of a netlist of the integrated circuit design 120, where the netlist may, for example, be understood as a list of interconnects of the integrated circuit design 120 that electrically connect the electric components of the integrated circuit design 120 or the corresponding electronic circuit 122. In some examples, the integrated circuit design 120 or the netlist may further include the electric components or elements 148 of the integrated circuit design 120 or the corresponding integrated circuit 122. Further, the integrated circuit design 120 may include information or computer- aided design (CAD) data on the geometry of the electric components of the integrated circuit design 120 or the corresponding integrated circuit 122 and on the connections of the mentioned electric components or elements.

[0031] By w ay of example, the application software component 106 and / or the processor 102 may further be configured to determine at least one geometric property 134 of at least one representative metal layer 130 of the respective circuit component 124, 128 using the integrated circuit design 120, w here the respective geometric property 134 of the at least one representative metal layer 130 is representative of the respective circuit component 124, 128 with respect to an antenna effect of the respective circuit component 124, 128.

[0032] To determine the at least one geometric property 134 of at least one representative metal layer 130 of the respective circuit component 124, 128, at least one geometric property 134 of the metal layers 130 of the respective sub-circuit may be considered. Examples of such geometric properties 134 that may be meaningful in the context of an antenna effect are provided in more detail below. Herein, in some examples, there may be one or more representative metal layers 130 of the respective sub-circuit and hence of respective circuit component 124, 128. The respective representative metal layer 130 may, for example, represent the respective circuit component 124, 128 with respect to an antenna effect of the respective circuit component 124,128. For example, if the respective circuit component 124, 128 includes a gate 132, the one or more representative metal layers 130 of the respective circuit component 124, 128 may represent both the one or more gates 132 and the metal layers 130 of the respective circuit component 124, 128 with respect to an antenna effect of the respective circuit component 124, 128. In some examples, the first circuit component 124 and the second circuit component 128 may, for example, include a respective sub-circuit including at least one respective gate 132. In further examples, the first circuit component 124 may include a sub-circuit including at least one respective gate 132, and the second circuit component 128 may include an interposer. In either example, at least one geometric property 134 of the gate 132 of the respective circuit component 124, 128 including this gate 132 may be determined.

[0033] By way of example, the at least one geometric property 134 of the one or more representative metal layers 130 represents the respective circuit component 124, 128 with respect to the antenna effect of the respective circuit component 124, 128. In some examples, the contribution of the metal layers 130 that are not representative metal layers 130 or, optionally, the contribution of the respective gate 132 to the antenna effect of the respective circuit component 124, 128 may be included in the at least one geometric property 134 of the one or more representative metal layers 130. For example, for the respective circuit component 124, 128, the at least one geometric property 134 of the one or more representative metal layers 130 may correspond to the total geometric properties 134 of all metal or metal layers connected to one or more gates 132 without being connected to a source / drain implant. Similar considerations may apply to a second circuit component 128 including at least one interposer. In some examples, fewer metal layers 130 and no gates 132 need to be considered for the determination of the at least one geometric property 134 of the one or more representative metal layers 130 representing this second circuit component 128.

[0034] In further examples, the required antenna properties, including the at least one geometric property7134 of at least one representative metal layer 130 of the respective circuit component 124, 128. may be extracted for each circuit component 124, 128 (e.g., each die). For example, since the respective circuit component 124, 128 may be considered to be a two-dimensional integrated circuit, the provided integrated circuit design 120 may be used by available ICV tools, such as the Calibre nmDRC application produced by Siemens Industry Software Inc., of Plano, Texas, USA, to determine the mentioned respective geometric property 134. Other ICV tools may have similar functionalities. The output of the mentioned extraction may, for example, be stored in a mini-OASIS ('‘Open Artwork System Interchange Standard”) file or layout files with the top interconnect layers, the partial layers, or the top metal layers 130 of the respective circuit component 124, 128 annotated with these extracted output properties.

[0035] By way of example, determining the at least one geometric property 134 of the at least one representative metal layer 130 of the respective circuit component 124, 128 may include determining the at least one representative metal layer 130 of the respective circuit component 124, 128.

[0036] In some examples, the application software component 106 and / or the processor 102 may further be configured to determine a stacked arrangement 136 of the representative metal layers 130 representing the respective circuit components 124, 128.

[0037] By way of example, the determined at least one representative metal layer 130 of the respective circuit component 124, 128 may be stacked to obtain the stacked arrangement 136. The stacked arrangement 136 may, for example, be determined by replacing the respective circuit component 124, 128 with the corresponding at least one representative metal layer 130 of the respective circuit component 124, 128. Herein, the representative metal layers 130 of the respective circuit components 124, 128 may be electrically connected to each other via the electric connections 126 just like the respective circuit components 124, 128 of the original integrated circuit design 120 that are electrically connected to each other via corresponding electric connections 126.

[0038] The stacked arrangement 136 may, by way of example, be understood as a simplified integrated circuit design 120 including the representative metal layers 130 of the respective circuit components 124, 128. In some examples, the stacked arrangement 136 may represent the integrated circuit design 120 or the corresponding integrated circuit 122 with respect to the antenna effect of the integrated circuit design 120 or the corresponding integrated circuit 122.

[0039] In further examples, stacking the representative metal lay ers 130 to obtain the stacked arrangement 136 may be done using available ICV tools, such as the Calibre 3DSTACK application produced by Siemens Industry Software Inc., of Plano, Texas, USA. By way of example, the OASIS files including the extracted output properties of the top interconnect layers, the partial layers, or the top metal layers 130 of the respective circuit component 124, 128 annotated with these extracted output properties may be used as an input to the step of determining the stacked arrangement 136.

[0040] For example, the application software component 106 and / or the processor 102 may further be configured to determine a stacked antenna effect value 138 of the stacked arrangement 136 using the geometric properties 134 of the representative metal layers 130.

[0041] To determine the stacked antenna effect value 138, for example, the above-mentioned antenna rules may be used, which may use the determined geometric properties 134 of the representative metal layers 130 of the stacked arrangement 136 as an input. Herein, the antenna rules may include one or more mathematical equations that include the determined geometricproperties 134 of the representative metal layers 130 of the stacked arrangement 136 as variables of the respective equation. In some examples, these antenna rules may be expressed as an allowable ratio of the geometric properties 134 of the representative metal layers 130 to the geometric properties 134 of the gate 132, as will be explained in more detail below. By way of example, there may be one such ratio for each interconnect layer. Further, the antenna rules may, for example, include cumulative rules according to which the sum or partial sum of the ratios over all interconnect layers may set the limit. By way of example, the mentioned ratio may correspond to the stacked antenna effect value 138, and the allowable ratio may correspond to the preconfigurable threshold mentioned above and below.

[0042] In this context, it should be appreciated that, in some examples, antenna rules applicable to two-dimensional ICs may validly be applied to the stacked arrangement 136, although the stacked arrangement 136 represents the three-dimensional integrated circuit design 120 and the three-dimensional integrated circuit 122. The valid application of “2D antenna rules” to the 3DIC design 120 and the 3DIC 122 may, in some examples, be enabled thanks to the described introduction of the representative metal layers 130 and the corresponding geometric properties 134. Accordingly, by way of example, the respective circuit component 124, 128 may be modeled and hence be simplified while capturing the relevant properties of the respective circuit component 124, 128 with respect to the antenna effect of the respective circuit component 124, 128. The suggested method may include the advantage of boiling down the more complex 3DIC design 120 and the 3DIC 122 to the representative metal layers 130 and the corresponding geometric properties 134 to eventually obtain a modeled and simplified stacked arrangement 136: the advantage may, for example, be that the stacked arrangement 136 may capture and reproduce the antenna effect of the 3DIC design 120 while the determination of this antenna effect and the stacked antenna effect value 138 may still be done using available antenna rules. This applicability, for example, of antenna rules for two-dimensional integrated circuits to the stacked arrangement 136 representing the 3DIC design 120 may be valid since the stacked arrangement 136 may still be susceptible and well-described by antenna rules for two- dimensional integrated circuits. These antenna rules may be provided by fabs or users, as mentioned above.

[0043] The suggested method therefore may, in some examples, avoid a full calculation of the complete three-dimensional integrated circuit design 120 to determine potentially problematic antenna effects and related process deficiencies of the integrated circuit design 120. Rather, according to the suggested method, a smart simplification and modeling of the complete three- dimensional integrated circuit design 120 is used to facilitate the determination of potentially problematic antenna effects and related process deficiencies of the integrated circuit design 120.The facilitation may be achieved thanks to stacking the described representative metal layers 130 and their geometric properties 134.

[0044] By way of example, the application software component 106 and / or the processor 102 may further be configured to output that the integrated circuit design 120 has a process deficiency if the stacked antenna effect value 138 exceeds a preconfigurable threshold.

[0045] As mentioned above, the preconfigurable threshold may. for example, be derived from or determined using the above-mentioned antenna rules. For example, the preconfigurable threshold may be provided by a user or by a fab, as mentioned above. If the stacked antenna effect value 138 exceeds the preconfigurable threshold, a problematic antenna effect of the three- dimensional integrated circuit design 120 and hence a process deficiency relating to this antenna effect may be identified. Accordingly, output may be generated (e.g., an output message 140 that may be output to a user or an engineer, such as via the ICV UI 116) and displayed to the user on the display device 112. In further examples, the output and / or the output message 140 may additionally or alternatively be communicated to another device which is communicatively connected with the ICV system 118.

[0046] Once the user or another device has been informed about the identified process deficiency, the integrated circuit design 120 may, for example, be amended to reduce or avoid the antenna effect and hence the process deficiency of the integrated circuit design 120. Then, the amended integrated circuit design 120 may be checked according to the suggested method to verily that the amended integrated circuit design 120 involves no problematic antenna effect and hence does not suffer from a corresponding process deficiency.

[0047] In further examples, the output message 140 may also be output if the integrated circuit design 120 does not have a process deficiency and if the stacked antenna effect value 138 does not exceed a preconfigurable threshold. In these examples, the output message 140 may indicate that the no problematic antenna effect is determined for the analyzed three-dimensional integrated circuit design 120.

[0048] In further examples, the at least one representative metal layer 130 of the respective circuit component 124, 128 includes one or more metal layers 130-1 arranged in the vicinity of the electric connection 126 of the respective circuit component 124, 128 to at least one of the other circuit components 124, 128, and / or the at least one representative metal layer 130 of the respective sub-circuit includes one or more metal layers 130-1 arranged remotely from the respective gate 132.

[0049] In some examples, one representative metal layer 130-1 may be sufficient for adequately modeling the respective circuit component 124, 128 with respect to an antenna effect. This one representative metal layer 130-1 may, for example, be among the metal layers 130-1 ofthe respective circuit component 124, 128 arranged closest to the electric connection 126 that electrically connects the respective circuit component 124, 128 with one or more of the other circuit components 124, 128 of the three-dimensional integrated circuit design 120. In further examples, two or more representative metal layers 130-1, 130-2 may be required in this context. These representative metal layers 130-1, 130-2 may be the metal layers 130-1, 130-2 of the respective circuit component 124, 128 that are arranged closest to the mentioned electric connection 126. By way of example, the mentioned representative metal layer 130-1 or representative metal layers 130-1, 130-2 may be arranged among the metal layers 130-1, 130-2 of the respective circuit component 124, 128 most remotely from the respective gate 132 of the respective circuit component 124, 128.

[0050] By way of example, the explained representative metal layers 130-1, 130-2 may be one or more metal layers 130-1, 130-2 that, during the construction of the respective circuit component 124, 128, may be subject to added electric charge when the metal layers 130-1, 130- 2 are etched. Then, especially if the oxide of the gate 132 is not protected (e.g.. not yet protected) by a diode, the charge on the respective top metal layer 130-1. 130-2 may rise to the level of breaking down the gate oxide to which the respective metal layers 130-1, 130-2 are already electrically connected.

[0051] In some examples, the mentioned metal layers 130-1, 130-2 that are arranged closest to the mentioned electric connection 126 or are arranged most remotely from the respective gate 132 may be known as ‘'top” metal layers 130-1, 130-2 of the respective circuit component 124, 128 (e.g., of the respective die). By way of example, these top metal layers 130-1, 130-2 may have a decisive influence on the overall antenna effect of the respective circuit component 124, 128, which is why. in some examples, these top metal layers 130-1. 130-2 may represent the respective circuit component 124, 128 in the context of determining an antenna effect of the respective circuit component 124, 128 or the three-dimensional integrated circuit design 120.

[0052] By way of example, the mentioned most remote metal layers 130 may be know n as “bottom’' or “lower” metal layers 130 of the respective circuit component 124, 128 (e.g., of the respective die). In this context, the respective circuit component 124. 128 may. for example, include a gate 132 at its bottom side.

[0053] In some examples, the at least one representative metal layer 130 of the respective subcircuit includes one or more metal layers 130 connected to the remaining sub-circuit via a through-silicon via 142.

[0054] Herein, a through-silicon via (TSV) may also be known as a through-chip via and may be understood as a vertical electrical connection (e.g., via) that passes completely through a silicon wafer or die. TSVs are high-performance interconnect techniques used as an alternativeto wire-bond and flip chips to create 3D packages and 3D integrated circuits 122. Compared to alternatives such as package-on-package, the interconnect and device density may be substantially higher, and the length of the connections may become shorter.

[0055] In some examples, the respective representative metal layer 130 connected to the remaining sub-circuit via a TSV 142 may be a back-side metal layer 130. Herein, the TSV 142 may, for example, be used to branch off the die or sub-circuit. The branched-off portion of the respective circuit component 124, 128 includes one or more of the mentioned back-side metal layers 130. These back-side metal layers 130 may also have an important influence on the overall antenna effect of the respective circuit component 124, 128 so that the back-side metal layers 130 may be included in the respective representative metal layer 130 of the respective circuit component 124, 128. In further examples, if there are several back-side metal layers 130, the one or more of these back-side metal layers 130 may be identified to be a respective representative metal layer 130 most remote from the TSV 142.

[0056] By way of example, the respective geometric property 134 of the respective metal layer 130 includes an area, a diameter, and / or a perimeter of a metal surface of the respective metal layer 130. The respective metal surface is arranged in the vicinity of the electric connection 126 of the respective circuit component 124, 128 to at least one of the other circuit components 124, 128, and / or the respective metal surface is arranged remotely from the respective gate 132.

[0057] The above-mentioned antenna rules may. for example, be expressed as an allowable ratio of the metal area to the gate area. In further examples, the diameter or perimeter of the metal surface of the respective metal layer 130 may alternatively or additionally be taken into account for the mentioned ratio. There may be one such ratio for each interconnect or metal layer 130. The area, diameter, or perimeter that may be counted may be or relate to more than one polygon (e.g., may be the total area, diameter, or perimeter of all metal connected to one or more gates 132 without being connected to a source / drain implant). By way of example, the contribution of the bottom metal layers to the antenna effect may be included in the respective geometric property 134 of the respective representative metal layer 130 of the respective circuit component 124, 128 (e.g., by summing up the respective geometric properties 134 of the various metal layers 130 and optionally of the respective gate 132, and by assigning the accumulated geometric properties 134 to the respective representative metal layer 130).

[0058] Accordingly, the respective geometric property 134 may include the area, diameter, or perimeter of the respective metal layer 130 and optionally of the respective gate 132. Herein, the respective metal surface may, for example, be the surface of a metal layer 130 that is arranged towards the top metal layer 130-1 explained above since the respective metal surface may accumulate electric charges during the construction of the of the respective circuit component124, 128 when the metal layers 130 are etched.

[0059] In some examples, the respective geometric property 134 of the respective gate 132 includes an area, a diameter, and / or a perimeter of a gate surface of the respective gate 132 protruding from the integrated circuit design 120.

[0060] Similar to the above explanations with respect to the area, a diameter, and / or a perimeter of a metal surface of the respective metal layer 130. the respective geometric property 134 of the respective gate 132 may include an area, a diameter, and / or a perimeter of a gate surface of the respective gate 132 as input to the above-mentioned antenna rules.

[0061] The relevant gate surface of the respective gate 132 may, for example, protrude from the integrated circuit design 120 or from the integrated circuit 122, which may provide that the relevant gate surface points away from the top metal layer 130-1 explained above. This may be due to the electric charges accumulated during the construction of the of the respective circuit component 124, 128, when the metal layers 130 are etched: the electric charges flow from the metal layers 130 to the electrically connected gate 132 and may damage the gate oxide arranged at the explained gate surface pointing away from the top metal layer 130-1 of the respective circuit component 124, 128.

[0062] In further examples, the stacked arrangement 136 excludes gates 132 or other metal layers 130 of the respective circuit component 124, 128. The other metal layers 130 are arranged remotely from the electric connection 126 of the respective circuit component 124, 128 to at least one of the other circuit components 124, 128, and / or the other metal layers 130 are arranged in the vicinity of the respective gate 132.

[0063] According to the above-mentioned modeling of the three-dimensional integrated circuit design 120, for example, only a fraction of the metal layers 130 of the respective circuit component 124, 128 may be identified to be a respective representative metal layer 130 that may then be stacked to obtain the stacked arrangement 136. In some examples, neglecting these bottom or lower metal layers 130 may be justified because of their comparably small contribution to an antenna effect of the respective circuit component 124, 128. In further examples, the contribution of the bottom metal layers to the antenna effect may be included in the respective geometric property 134 of the respective representative metal layer 130 of the respective circuit component 124, 128 (e.g., by summing up the respective geometric properties 134 of the various metal layers 130 and by assigning the accumulated geometric properties 134 to the respective representative metal layer 130).

[0064] By way of example, the application software component 106 and / or the processor 102 may further be configured to: determine a circuit component antenna effect value 138 of the respective circuit component 124, 128 using the respective geometric property 134 of the at leastone representative metal layer 130 of the respective circuit component 124. 128; and output that the respective circuit component 124, 128 of the integrated circuit design 120 has a process deficiency if the respective circuit component antenna effect value 138 exceeds the preconfigurable threshold.

[0065] To determine a circuit component antenna effect value 138 of the respective circuit component 124, 128, the explained antenna rules may be applied accordingly on the level of the respective individual circuit component 124, 128.

[0066] In some examples, the application software component 106 and / or the processor 102 may further be configured to output an indication 150 of the at least one representative metal layer 130 that is at least partially causing the stacked antenna effect value 138 to exceed the preconfigurable threshold.

[0067] By way of example, the determined stacked antenna effect value 138 or the respective geometric property of the respective representative metal layer 130 may be used to determine which respective representative metal layer 130 may be the cause or at least one of the main causes of the problematic antenna effect of the three-dimensional integrated circuit design 120 or the corresponding three-dimensional integrated circuit 122. The problematic antenna effect may, for example, predominantly be caused by one of the representative metal layers 130 that may, in some examples, be indicated by a considerable contribution to the stacked antenna effect value 138 by the concerned representative metal layer 130 (e.g., through a considerable contribution to the one or more of the ratios mentioned above in the context of the antenna rules).

[0068] In further examples, the antenna effect value 138 may be determined directly or individually for the respective representative metal layer 130 (e.g., independently from the stacked antenna effect value 138 of the three-dimensional integrated circuit design 120). The determination of the mentioned antenna effect value 138 may, for example, be done using the mentioned ratios of the antenna rules, where in some examples, only individual respective representative metal layer 130 may be considered.

[0069] Once the concerned respective representative metal layer 130 has been identified, a corresponding indication 150 may be output, for example, comparably to the above-mentioned output message 140. Hence, the indication 150 may, for example, be output to a user or an engineer (e.g., via the ICV UI 116 that may be displayed to the user on the display device 112). In further examples, the indication 150 may additionally or alternatively be communicated to another device that is communicatively connected with the ICV system 118.

[0070] Outputting the indication 150 relating to the concerned respective representative metal layer 130 may, in some examples, contribute to reduce or avoid the antenna effect and hence the process deficiency of the integrated circuit design 120. In some examples, the user may focus onthe concerned respective representative metal layer 130 to create an amended integrated circuit design 120 that may be checked according to the suggested procedure to verify that the amended integrated circuit design 120 involves no problematic antenna effect and hence does not suffer from a corresponding process deficiency.

[0071] By way of example, the application software component 106 and / or the processor 102 may further be configured to: determine a respective net 146* of electrically connected elements 148 in the respective circuit component 124, 128 including the at least one representative metal layer 130 that is at least partially causing the stacked antenna effect value 138 to exceed the preconfigurable threshold; and output an indication 150 of the determined, respective net 146* of electrically connected elements 148, and / or output an indication 150 of the respective gate 132* that is included in the determined, respective net 146*.

[0072] As mentioned above, the respective representative metal layer 130 that at least partially causes the stacked antenna effect value 138 to exceed the preconfigurable threshold may be determined. In some examples, using the knowledge of the concerned respective representative metal layer 130, the net 146* of electrically connected elements 148 in the respective circuit component 124, 128 and relating to the concerned respective representative metal layer 130 may be determined. This may, by way of example, be achieved by integrating back the concerned respective representative metal layer 130 in the original, respective circuit component 124. 128 (e.g., the original die). In some examples, the mentioned antenna rules may be used to identify the concerned respective net 146* that is arranged on one or more metal layers 130 that may be represented by the concerned respective representative metal layer 130.

[0073] Herein, in some examples, the mentioned elements 148 may include active components that may be understood to rely on a source of energy and usually may inject power into a circuit. Active components may include amplifying components such as transistors, diodes, thyristors, field-programmable gate arrays (FPGAs), or opto-electronic components, such as opto-isolators, opto-couplers, photo-couplers, or optical switches. In further examples, the mentioned elements 148 may include passive components that may not be able to introduce net energy into a circuit. Passive components may, for example, include two-terminal components such as resistors, capacitors, inductors, and transformers.

[0074] In further examples, the one or more gates 132* that are or are included in the concerned respective net 146* may be determined. The determined antenna effect and process deficiency may, in some examples, damage the gate oxide of the concerned respective gate 132*. If the concerned respective net 146* includes two or more gates 132, the mentioned antenna rules may, for example, be used to identify the respective concerned respective net 146* that may, for example, include the gate 132* with the most unfavorable geometric properties 134and / or the gate 132* that is electrically connected to the top metal layers 130-1 with the most unfavorable geometric properties 134. Unfavorable geometric properties 134 refer to the antenna rules and the antenna effect.

[0075] Once the concerned respective net 146* and / or the concerned respective gate 132* have been identified, a corresponding indication 150 may be output (e.g., comparably to the above- mentioned output message 140). Hence, the indication 150 may, for example, be output to a user or an engineer (e.g., via the ICV UI 116 that may be displayed to the user on the display device 112). In further examples, the indication 150 may additionally or alternatively be communicated to another device that is communicatively connected with the ICV system 118.

[0076] Outputting the indication 150 relating to the concerned respective net 146* and / or the concerned respective gate 132* may, in some examples, contribute to reduce or avoid the antenna effect and hence the process deficiency of the integrated circuit design 120. In some examples, the user may focus on the concerned respective net 146* and / or the concerned respective gate 132 to create an amended integrated circuit design 120 that may be checked according to the suggested procedure to verify that the amended integrated circuit design 120 involves no problematic antenna effect and hence does not suffer from a corresponding process deficiency.

[0077] In some examples, a corresponding procedure may be applied if the at least one representative metal layer 130 that is at least partially causing the circuit component antenna effect value 138 exceeds the preconfigurable threshold.

[0078] In further examples, if the stacked antenna effect value 138 does not exceed the preconfigurable threshold, the application software component 106 and / or the processor 102 may further be configured to transmit the three-dimensional integrated circuit design 120 to an integrated circuit manufacturing machine 160.

[0079] In some examples, the transmission of the electronic circuit design 120 to an integrated circuit manufacturing machine 160 and, optionally, the manufacture of the one or more three- dimensional integrated circuit 122 by the integrated circuit manufacturing machine 160 may only be done or triggered if the stacked antenna effect value 138 does not exceed the preconfigurable threshold(e.g., since no problematic process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design has been determined). In some examples, the three-dimensional integrated circuit 122 may be included by a larger integrated circuit 162.

[0080] It should be appreciated that the described the application software component 106 and / or the processor 102 may carry out an analogous method of determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120.Also, the explained examples may be combined to obtain a more detailed method of determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120. Further, a computer-readable medium 170 that may include a computer program product 172 is shown in Figure 1. The computer program product 172 may be encoded with executable instructions that, when executed, cause the computer system 100 or and / or the ICV system 118 to carry out the described method.

[0081] Among the advantages of the suggested method is that using the representative metal layers 130 and, in some examples, partial layers of a 3DIC design 120, a 3DIC antenna check may, for example, be done with reduced memory usage while achieving a good performance. Further, the suggested method may be suitable for many if not all packaging types to check the antenna effect of 3DIC. In some examples, the property extraction from each die may be handled separately, which makes the approach comparably flexible. In addition, an automatic way of executing cross die checks and back annotating the data into die context may, for example, be enabled, which increases the usability and the ease of use of the suggested method. By way of example, since the considered 3D stack is not including all the interconnect stack from both or all involved dies, the design rule checks may run much faster. Also, by annotating the data into die context (e.g., involving the indication on the failing net or concerned gate), efficient debugging of the 3DIC design 120 may be enabled by giving the user the option to trace the full path of the failing net 146*.

[0082] Figure 2 depicts a functional block diagram of second example system 100 that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0083] Figure 2 shows a second example system 100 similar to the first example system depicted in Figure 1. While Figure 1 depicts a three-dimensional integrated circuit design 120 including a first circuit component 124 with a gate 132 and a number of (e.g., several) metal layers 130-1, 130-2 and a second circuit component 128 being an interposer with only one metal layer, Figure 2 depicts a three-dimensional integrated circuit design 120 including a first circuit component 124 and a second circuit component 128 that both have a gate 132 and a number of (e g., several) metal layers 130-1, 130-2.

[0084] Figure 3 depicts a functional block diagram of third example system 100 that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0085] The third example system 100 is similar to the second example system depicted in Figure 2. According to the third example system 100, the concerned respective representative metal layer 130 may be determined as explained above and may be output (e.g., to the user viathe ICV UI 116). Additionally or alternatively, the concerned respective net 146* and / or the concerned respective gate 132 *may be determined as explained above and may be output (e.g., to the user via the ICV UI 116). Herein, the corresponding output indication 150 may, in some examples, contribute to reduce or avoid the antenna effect and hence the process deficiency of the integrated circuit design 120 by allowing the user to focus on the properties of the electronic circuit design 120 that may predominantly cause the problematic antenna effect and hence the process deficiency of the integrated circuit design 120.

[0086] Figure 4 depicts a first aspect of an example methodology that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0087] On the left of Figure 4, the three-dimensional integrated circuit design 120 is depicted. The integrated circuit design 120 includes two circuit components 124, 128 of which the first circuit component 124 includes a first sub-circuit having a gate 132 and a number of (e.g., several) metal layers 130 of which 130-1 indicates the topmost layer. The second circuit component 128 includes an interposer having a metal layer. The first circuit component 124 and the second circuit component 128 are electrically connected to each other via the electric connection 126.

[0088] In the center of Figure 4, the topmost metal layer 130-1 is determined to be the representative metal layer 130-1 of the first circuit component 124 with respect to an antenna effect of the first circuit component 124. Further, at least one geometric property 134 of the representative metal layer 130-1 and at least one geometric property 134 of the gate 132 are determined. Herein, the representative metal layer 130-1 and its at least one geometric property 134 may be determined such as to represent the first circuit component 124 with respect to an antenna effect of the first circuit component 124 (e.g., including the other metal layers 130-2 and the gate 132 of the first circuit component 124). Since the interposer of the second circuit component 128 may have a very' simple design and, for example, only have one metal layer, this one metal layer of the interposer is determined to be the representative metal layer of the second circuit component 128.

[0089] On the right of Figure. 4, the three-dimensional integrated circuit design 120 is modeled by stacking the representative metal layer 130-1 of the first circuit component 124 and the second circuit component 128 to obtain the stacked arrangement 136.

[0090] This stacked arrangement 136 may then be used to determine a stacked antenna effect value 138 of the stacked arrangement 136 using the geometric properties 134 of the representative metal layers 130 and eventually to output that the integrated circuit design 120 has a process deficiency if the stacked antenna effect value 138 exceeds a preconfigurablethreshold.

[0091] Figure 5 depicts a second aspect of another example methodology that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0092] The example methodology depicted in Figure 5 is similar to the example methodology depicted in Figure. 4. One difference between the two methodologies is that the second circuit component 128 in Figure 5 is more complex and similar to the first circuit component 124.

[0093] Accordingly, as depicted in the center of Figure 5, the topmost metal layer 130-1 of the second circuit component 128 is determined to be the representative metal layer 130-1 of the second circuit component 128 with respect to an antenna effect of the second circuit component 128. Further, at least one geometric property 134 of the representative metal layer 130-1 and at least one geometric property 134 of the gate 132 are determined. Herein, the representative metal layer 130-1 and its at least one geometric property' 134 may be determined so as to represent the second circuit component 128 with respect to an antenna effect of the second circuit component 128 (e.g.. including other metal layers 130-2 and the gate 132 of the second circuit component 128).

[0094] As depicted on the right of Figure 5, the three-dimensional integrated circuit design 120 is modeled by stacking the representative metal layer 130-1 of the first circuit component 124 and the representative metal layer 130-1 of the second circuit component 128 to obtain the stacked arrangement 136.

[0095] Again, this stacked arrangement 136 may then be used to determine a stacked antenna effect value 138 of the stacked arrangement 136 using the geometric properties 134 of the representative metal layers 130 and eventually to output that the integrated circuit design 120 has a process deficiency if the stacked antenna effect value 138 exceeds a preconfigurable threshold.

[0096] Figure 6 depicts a first aspect relating to a further example methodology' that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0097] The first circuit component 124 includes a first sub-arrangement including the gate 132 and a number of (e.g., several) metal layers 130-1, 130-2 of which the metal layer 130-1 indicates the topmost metal layer of this first sub-arrangement (e.g., the metal layer 130 of the first sub-arrangement that is arranged most remotely from the gate 132). Further, the first circuit component 124 includes a second sub-arrangement that is connected to the metal layer 130-2 of the first sub-arrangement via a through-silicon-via (TSV) 142 and includes a number of (e.g., several) metal layers 130-3, 130-4, 130-5 of which 130-3 indicates the topmost metal layer 130-3 of this second sub-arrangement. Hence, the metal layer 130-3 of the second sub-arrangement is arranged most remotely from the gate 132.

[0098] The first circuit component 124 may be connected to further second components 128 via the electric connection 126.

[0099] In some examples, the topmost metal layer 130-1 of the first sub-arrangement and / or the topmost layer 130-3 of the second sub-arrangement may be determined to be the representative metal layer 130 of the first circuit component 124 with respect to an antenna effect of the first circuit component 124. At least one geometric property 134 of the representative metal layers 130 and at least one geometric property 134 of the gate 132 are determined. Herein, the representative metal layers 130 and its respective at least one geometric property 134 may be determined such as to represent the first circuit component 124 with respect to an antenna effect of the first circuit component 124 (e.g., including other metal layers 130 and the gate 132 of the first circuit component 124). By way of example, the topmost layer 130-3 of the second subarrangement may be determined to be the representative metal layer 130 of the first circuit component 124.

[0100] In further examples, the topmost metal layer 130-1 of the first sub-arrangement and the topmost layer 130-3 of the second sub-arrangement may be determined to be the representative metal layers 130-1, 130-3 of the first circuit component 124 with respect to an antenna effect of the first circuit component 124. At least one geometric property 134 of the representative metal layers 130-1, 130-3 and at least one geometric property 134 of the gate 132 are determined. Herein, the representative metal layers 130-1, 130-3 and their respective at least one geometric property7134 may be determined so as to represent the first circuit component 124 with respect to an antenna effect of the first circuit component 124 (e.g., including other metal layers 130-2, 130-4, 130-5 and the gate 132 of the first circuit component 124).

[0101] Figure 7 depicts a second aspect relating to another example methodology that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0102] As depicted in Figure 7. the respective geometric property 134 of the representative metal layer 130-1 may include an area, a diameter, and / or a perimeter of a metal surface of the representative metal layer 130-1, where the metal surface of the representative metal layer 130-1 may point away from the gate 132 and / or the remaining first circuit component 124. The respective geometric property 134 of the gate 132 may include an area, a diameter, and / or a perimeter of a metal surface of the gate 132, where the metal surface of the gate 132 may point away from representative metal layer 130-1 and / or the remaining first circuit component 124. Herein, the mentioned metal surface of the gate 132 may include the gate oxide.

[0103] Figure 8 depicts a third aspect relating to yet another example methodology that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design 120 in a product system 100.

[0104] The first circuit component 124 includes two nets 146, 146*, where each of the nets 146, 146* includes two or more gates 132 or elements 148, such as transistors, diodes, capacitors or resistors that are electrically connected to each other via respective electric connections 126?. For the sake of simplicity, only a few of the elements 148 are depicted in Figure 8. In some examples, the net 146* may be determined to include the at least one representative metal layer 130 that is at least partially causing the stacked antenna effect value 138 to exceed the preconfigurable threshold. The determined net 146* may. for example, be understood as a concerned or failing net 146* in the context of the occurrence of an antenna effect and the related process deficiency. By way of example, an output an indication 150 may be generated indicative of the determined failing net 146*.

[0105] In further examples, the gate 132* included in the determined failing net 146* may be determined. This gate 132* may, for example, be included additionally or alternatively in the output indication 150.

[0106] Figure 9 depicts a flow diagram of an example methodology Ml that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system. The method may start at M02. and the methodology may include a number of (e.g., several) acts carried out through operation of at least one processor.

[0107] Herein, the integrated circuit may include at least two electrically connected circuit components. A first circuit component of the circuit components may include at least one first sub-circuit. A second circuit component of the circuit components may include at least one interposer and / or at least one second sub-circuit. The respective sub-circuit may include one or more metal layers and at least one gate. The respective interposer may include at least one metal layer.

[0108] These acts may include: an act M04 of providing the integrated circuit design; an act M06 of determining at least one geometric property of at least one representative metal layer of the respective circuit component using the integrated circuit design, where the respective geometric property of the at least one representative metal layer is representative of the respective circuit component with respect to an antenna effect of the respective circuit component; an act M08 of determining a stacked arrangement of the representative metal layers representing the respective circuit components; an act M10 of determining a stacked antenna effect value of the stacked arrangement using the geometric properties of the representative metal layers; and an act M12 of outputting that the integrated circuit design has a processdeficiency if the stacked antenna effect value exceeds a preconfigurable threshold. At Ml 4, the methodology may end.

[0109] It should further be appreciated that the methodology Ml may include other acts and features discussed previously with respect to the computer-implemented method of determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system.

[0110] Figure 10 depicts a flow diagram of a further example methodology M2 that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product sy stem. The methodology' M2 may include the same acts as the above-described methodology Ml illustrated in Figure 9 and additionally an act M14 of outputting an indication of the at least one representative metal layer for which the antenna effect value exceeding the preconfigurable threshold has been determined, while the methodology M2 may end at M16.

[0111] Figure 11 depicts a flow diagram of a further example methodology M3 that facilitates determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit design in a product system. The methodology M3 may include the same acts as the above-described methodology Ml illustrated in Figure 9 and additionally an act M14 of determining a respective net of electrically connected elements in the respective circuit component including the at least one representative metal layer for which the antenna effect value exceeding the preconfigurable threshold has been determined; and an act Ml 6 of outputting an indication of the determined, respective net of electrically connected elements, and / or outputting an indication of the respective gate which is included by the determined, respective net, while the methodology M3 may end at Ml 8.

[0112] Further, the methodology Ml, M2, and M3 may be combined to include the abovedescribed acts.

[0113] Figure 12 depicts a block diagram of a data processing system 1000 (also referred to as a computer system) in which an embodiment may be implemented, for example, as a portion of a product system, and / or other system operatively configured by software or otherwise to perform the processes as described herein. The data processing system 1000 may include, for example, the computer or IT system or data processing system 100 mentioned above. The data processing system depicted includes at least one processor 1002 (e.g., a CPU) that may be connected to one or more bridges / controllers / buses 1004 (e.g., a north bridge, a south bridge). One of the buses 1004, for example, may include one or more I / O buses such as a PCI Express bus. Also connected to various buses in the depicted example may include a main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one ormore display devices 1010. It should also be noted that in some embodiments, one or more controllers (e.g., graphics, south bridge) may be integrated with the CPU (e.g., on the same chip or die). Examples of CPU architectures include IA-32, x86-64, and ARM processor architectures.

[0114] Other peripherals connected to one or more buses may comprise communication controllers 1012 (e.g., Ethernet controllers, WiFi controllers, cellular controllers) operative to connect to a local area network (LAN), Wide Area Network (WAN), a cellular network, and / or other wired or wireless networks 1014 or communication equipment.

[0115] Further components connected to various busses may include one or more I / O controllers 1016 such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (e.g., connected to speakers and / or microphones). It should also be appreciated that various peripherals may be connected to the I / O controller(s) (e.g., via various ports and connections) including input devices 1018 (e.g., keyboard, mouse, pointer, touch screen, touch pad, drawing tablet, trackball, buttons, keypad, game controller, gamepad, camera, microphone, scanners, motion sensing devices that capture motion gestures), output devices 1020 (e.g.. printers, speakers) or any other type of device that is operative to provide inputs to or receive outputs from the data processing system. Also, it should be appreciated that many devices referred to as input devices or output devices may both provide inputs and receive outputs of communications with the data processing system. For example, the processor 1002 may be integrated into a housing (e.g., a tablet) that includes a touch screen that serves as both an input and display device. Further, it should be appreciated that some input devices (e.g., a laptop) may include a plurality7of different types of input devices (e.g., touch screen, touch pad, keyboard). Also, it should be appreciated that other peripheral hardware 1022 connected to the I / O controllers 1016 may include any type of device, machine, or component that is configured to communicate with a data processing system.

[0116] Additional components connected to various busses may include one or more storage controllers 1024 (e.g., SATA). A storage controller may be connected to a storage device 1026 such as one or more storage drives and / or any associated removable media, which may be any suitable non-transitory machine usable or machine-readable storage medium. Examples include nonvolatile devices, volatile devices, read only devices, writable devices, ROMs, EPROMs, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disk drives (CDs. DVDs. Blu-ray), and other known optical, electrical, or magnetic storage devices drives and / or computer media. Also, in some examples, a storage device such as an SSD may be connected directly to an I / O bus 1004 such as a PCI Express bus.

[0117] A data processing system in accordance with an embodiment of the present disclosuremay include an operating system 1028, software / firmware 1030, and data stores 1032 (e.g., that may be stored on a storage device 1026 and / or the memory 1006). Such an operating system may employ a command line interface (CLI) shell and / or a graphical user interface (GUI) shell. The GUI shell permits multiple display windows to be presented in the graphical user interface simultaneously, with each display window providing an interface to a different application or to a different instance of the same application. A cursor or pointer in the graphical user interface may be manipulated by a user through a pointing device such as a mouse or touch screen. The position of the cursor / pointer may be changed and / or an event, such as clicking a mouse button or touching a touch screen, may be generated to actuate a desired response. Examples of operating systems that may be used in a data processing system may include Microsoft Windows, Linux, UNIX, iOS, and Android operating systems. Also, examples of data stores include data files, data tables, relational database (e.g., Oracle, Microsoft SQL Server), database servers, or any other structure and / or device that is capable of storing data that is retrievable by a processor.

[0118] The communication controllers 1012 may be connected to the network 1014 (not a part of data processing system 1000), which may be any public or private data processing system network or combination of networks, as know n to those of skill in the art, including the Internet. Data processing system 1000 may communicate over the network 1014 with one or more other data processing systems such as a server 1034 (also not part of the data processing system 1000). However, an alternative data processing system may correspond to a plurality of data processing systems implemented as part of a distributed system in which processors associated with a number of (e.g., several) data processing systems may be in communication via one or more network connections and may collectively perform tasks described as being performed by a single data processing system. Thus, it is to be understood that when referring to a data processing system, such a system may be implemented across a number of (e.g., several) data processing systems organized in a distributed system in communication with each other via a network.

[0119] Further, the term “controller” is any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0120] In addition, it should be appreciated that data processing systems may be implemented as virtual machines in a virtual machine architecture or cloud environment. For example, the processor 1002 and associated components may correspond to a virtual machine executing in a virtual machine environment of one or more servers. Examples of virtual machine architecturesinclude VMware ESCi, Microsoft Hyper-V. Xen, and KVM.

[0121] Those of ordinary skill in the art will appreciate that the hardware depicted for the data processing system may vary for particular implementations. For example, the data processing system 1000 in this example may correspond to a computer, workstation, server, PC, notebook computer, tablet, mobile phone, and / or any other type of apparatus / system that is operative to process data and carry out functionality and features described herein, associated with the operation of a data processing system, computer, processor, and / or a controller discussed herein. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0122] Also, it should be noted that the processor described herein may be located in a server that is remote from the display and input devices described herein. In such an example, the described display device and input device may be included in a client device that communicates with the server (and / or a virtual machine executing on the server) through a wired or wireless network (which may include the Internet). In some embodiments, such a client device, for example, may execute a remote desktop application or may correspond to a portal device that carries out a remote desktop protocol with the server in order to send inputs from an input device to the server and receive visual information from the server to display through a display device. Examples of such remote desktop protocols include Teradici's PCoIP, Microsoft's RDP, and the RFB protocol. In such examples, the processor described herein may correspond to a virtual processor of a virtual machine executing in a physical processor of the server.

[0123] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component may be a process, a process executing on a processor, or a processor. Additionally, a component or system may be localized on a single device or distributed across a number of (e.g., several) devices.

[0124] Also, as used herein, a processor corresponds to any electronic device that is configured via hardware circuits, software, and / or firmware to process data. For example, processors described herein may correspond to one or more (or a combination) of a microprocessor. CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit that is capable of processing data in a data processing system, which may have the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.

[0125] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure isdepicted and described. The remainder of the construction and operation of data processing system 1000 may conform to any of the various current implementations and practices known in the art.

[0126] Also, it should be understood that the words or phrases used herein should be construed broadly, unless expressly limited in some examples. For example, the terms “comprise” and “comprise.” as well as derivatives thereof, provide for inclusion without limitation. The singular forms “a”, “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, the term “and / or,” as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term “or” is inclusive, providing for and / or, unless the context clearly indicates otherwise. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may be to comprise, be comprised within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.

[0127] Also, although the terms “first,” “second.” “third,” and so forth may be used herein to describe various elements, functions, or acts, these elements, functions, or acts should not be limited by these terms. Rather these numeral adjectives are used to distinguish different elements, functions, or acts from each other. For example, a first element, function, or act may be termed a second element, function, or act, and. similarly, a second element, function, or act may be termed a first element, function, or act, without departing from the scope of the present disclosure.

[0128] In addition, phrases such as “processor is configured to” carry7out one or more functions or processes, may provide that the processor is operatively configured to or operably configured to carry out the functions or processes via software, firmware, and / or wired circuits. For example, a processor that is configured to carry out a function / process may7correspond to a processor that is executing the software / firmware, which is programmed to cause the processor to carry out the function / process and / or may correspond to a processor that has the software / firmware in a memory or storage device that is available to be executed by the processor to carry out the function / process. It should also be noted that a processor that is “configured to” carry' out one or more functions or processes, may also correspond to a processor circuit particularly fabricated or “wired” to carry out the functions or processes (e.g., an ASIC or FPGA design). Further the phrase “at least one” before an element (e.g., a processor) that is configured to carry out more than one function may correspond to one or more elements (e.g., processors) that each carry' out the functions and may also correspond to two or more of the elements (e.g., processors) that respectively carry7out different ones of the one or moredifferent functions.

[0129] In addition, the term “adjacent to” may provide that an element is relatively near to but not in contact with a further element, or that the element is in contact with the further portion, unless the context clearly indicates otherwise.

[0130] Although an example embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0131] None of the description in the present patent document should be read as implying that any particular element, step, act. or function is an essential element, which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims.

[0132] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0133] While the present invention has been described above by reference to various embodiments, it should be understood that many changes and modifications can be made to the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and / or combinations of embodiments are intended to be included in this description.

Claims

CLAIMS1. A computer-implemented method for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design, wherein the 3DIC design includes at least two electrically connected circuit components, wherein a first circuit component of the at least two electrically connected circuit components includes at least one first subcircuit, wherein a second circuit component of the at least two electrically connected circuit components includes at least one interposer, at least one second sub-circuit, or the at least one interposer and the at least one second sub-circuit, wherein a respective sub-circuit of the at least one first sub-circuit and the at least one second sub-circuit includes one or more metal layers and at least one gate, wherein a respective interposer of the at least one interposer includes at least one metal layer, the method comprising: providing the 3DIC design; determining at least one geometric property of at least one representative metal layer of the one or more metal layers of a respective circuit component of the at least two circuit components using the 3DIC design, wherein a respective geometric property of the at least one geometric property of the at least one representative metal layer is representative of the respective circuit component with respect to an antenna effect of the respective circuit component; determining a stacked arrangement of the representative metal layers representing the respective circuit components; determining a stacked antenna effect value of the stacked arrangement using the geometric properties of the representative metal layers; and outputting that the 3DIC design has a process deficiency when the stacked antenna effect value exceeds a preconfigurable threshold.

2. The computer-implemented method of claim 1, wherein: the at least one representative metal layer of the respective circuit component includes one or more metal layers arranged in a vicinity of an electric connection of the respective circuit component to at least one other circuit component of the at least two circuit components; the at least one representative metal layer of the respective sub-circuit includes one or more metal layers arranged remotely from a respective gate of the at least one gate; or a combination thereof.

3. The computer-implemented method of one of the preceding claims, wherein the at least one representative metal layer of the respective sub-circuit includes one or more metal layers connected to the remaining sub-circuit of the at least one first sub-circuit and the at least one second sub-circuit via a through-silicon via.

4. The computer-implemented method of claim 1, wherein: the respective geometric property of the respective metal layer includes an area, a diameter, a perimeter, or any combination thereof of a metal surface of the respective metal layer; the respective metal surface is arranged in a vicinity of the electric connection of the respective circuit component to at least one of the other circuit components; the respective metal surface is arranged remotely from the respective gate; or any combination thereof.

5. The computer-implemented method of claim 1, wherein a respective geometric property of a respective gate of the at least one gate includes an area, a diameter, a perimeter, or any combination thereof of a gate surface of the respective gate protruding from the 3DIC design.

6. The computer-implemented method of claim 1, wherein: the stacked arrangement excludes gates or other metal layers of the respective circuit component; the other metal layers are arranged remotely from an electric connection of the respective circuit component to at least one of the other circuit components; the other metal layers are arranged in a vicinity of the respective gate; or any combination thereof.

7. The computer-implemented method of claim 1, further comprising: determining a circuit component antenna effect value of the respective circuit component using the respective geometric property of the at least one representative metal layer of the respective circuit component; and outputting that the respective circuit component of the 3DIC design has a process deficiency when the respective circuit component antenna effect value exceeds the preconfigurable threshold.

8. The computer-implemented method of claim 1, further comprising:outputing an indication of the at least one representative metal layer that is at least partially causing the stacked antenna effect value to exceed the preconfigurable threshold.

9. The computer-implemented method of claim 1, further comprising: determining a respective net of electrically connected elements in the respective circuit component including the at least one representative metal layer that is at least partially causing the stacked antenna effect value to exceed the preconfigurable threshold; and outputing an indication of the determined respective net of electrically connected elements, outputting an indication of the respective gate that is included in the determined respective net, or outputing the indication of the determined respective net of electrically connected elements and outputing the indication of the respective gate that is included in the determined respective net.

10. The computer-implemented method of claim 1, further comprising: when the stacked antenna effect value does not exceed the preconfigurable threshold: transmiting the 3DIC design to an integrated circuit manufacturing machine.

11. A computer system arranged and configured to execute the steps of the computer- implemented method according to one of the preceding claims.

12. A computer program product, including computer program code that, when executed by a computer system, cause the computer system to carry out the method of one of the claims 1 to 10.

13. A computer-readable medium including a computer program product including computer program code that, when executed by a computer system, cause the computer system to carry7out the method of one of the claims 1 to 10.

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