Display device including sensor

Abstract

A display device including a sensor is disclosed. The display device includes: a pixel including a light emitting element; a first sensor including a first light sensing element connected to a first sensing node; a second sensor including a second light sensing element connected to a second sensing node; and a first connection transistor electrically connecting a first sensing node of the first sensor and a second sensing node of the second sensor in response to the switching signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0077660 filed in the Korean Intellectual Property Office on June 16, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein are directed to a display device including a sensor. Background Art

[0004] An electronic device such as a television (TV), mobile phone, tablet computer, navigation system or game console includes a display device for displaying images. In addition to general input devices such as buttons, keyboards or mice, the electronic device may also include a display device that provides a touch panel for enabling a user to easily and intuitively input information or commands.

[0005] A touch panel is an input device that enables a user to interact with an electronic device by touching the screen. A touch panel can be arranged on top of a display screen comprising a plurality of pixels. As an example, a touch pad can be resistive or capacitive. Resistive touch pads work by detecting changes in resistance, and capacitive touch pads work by detecting changes in capacitance. A touch sensor is embedded within the touch panel and is responsible for detecting changes in electrical properties caused by touch. The touch sensor generates a sensing signal that can be processed to determine where and how the user is touching the screen. However, when the signal-to-noise ratio of some of the sensing signals is weak, it may be difficult to correctly detect a touch of the touch panel. Utility Model Content

[0006] Embodiments of the present disclosure provide a display device in which the performance of touch recognition is improved.

[0007] According to an embodiment, a display device includes a pixel, a first sensor, a second sensor, and a first connection transistor. The pixel includes a light emitting element. The first sensor includes a first light sensing element connected to a first sensing node, and the second sensor includes a second light sensing element connected to a second sensing node. The first connection transistor electrically connects a first sensing node of the first sensor and a second sensing node of the second sensor in response to a switching signal.

[0008] In an embodiment, the first light sensing element may include a first light sensing anode connected to the first sensing node and a first cathode connected to the driving voltage line, and the second light sensing element may include a second light sensing anode connected to the second sensing node and a second cathode connected to the driving voltage line.

[0009] In an embodiment, the first sensor may include: a first transistor connected between a reset voltage line and a first sensing node; a second transistor connected between a sensor drive voltage line and an intermediate node and including a gate electrode connected to the first sensing node; and a third transistor connected between the intermediate node and a first readout line and including a gate electrode connected to a scan line.

[0010] In an embodiment, the first transistor and the first connection transistor are transistors of a first type, and the second transistor and the third transistor are transistors of a second type different from the first type.

[0011] In an embodiment, the second sensor may include: a first transistor connected between a reset voltage line and a second sensing node; a second transistor connected between a sensor drive voltage line and an intermediate node and including a gate electrode connected to the second sensing node; and a third transistor connected between the intermediate node and a second readout line and including a gate electrode connected to a scan line.

[0012] In an embodiment, the first transistor and the first connection transistor may be transistors of a first type, and the second transistor and the third transistor may be transistors of a second type different from the first type.

[0013] In an embodiment, the display device may further include: a third sensor including a third light sensing element connected to a third sensing node; and a second connecting transistor electrically connecting the second sensing node of the second sensor and the third sensing node of the third sensor in response to a switching signal.

[0014] According to an embodiment, a display device includes a display panel, a readout circuit and a drive controller. The readout circuit receives a first sensing signal and a second sensing signal from the display panel to output a readout signal. The drive controller enables an image to be displayed in the display panel. The display panel includes: a pixel including a light-emitting element; a first sensor including a first light sensing element connected to a first sensing node and outputting a first sensing signal; a second sensor including a second light sensing element connected to a second sensing node and outputting a second sensing signal; and a first connecting transistor electrically connecting a first sensing node of the first sensor and a second sensing node of the second sensor. The drive controller turns on the first connecting transistor when it is determined that the signal-to-noise ratio of the readout signal is less than a threshold value, and otherwise turns off the first connecting transistor.

[0015] In an embodiment, the first light sensing element may include a first light sensing anode connected to the first sensing node and a first cathode connected to the driving voltage line, and the second light sensing element may include a second light sensing anode connected to the second sensing node and a second cathode connected to the driving voltage line.

[0016] In an embodiment, the first sensor may include: a first transistor connected between a reset voltage line and a first sensing node; a second transistor connected between a sensor driving voltage line and an intermediate node and including a gate electrode connected to the first sensing node; and a third transistor connected between the intermediate node and a first readout line and including a gate electrode connected to a scan line. The first readout line may output a first sensing signal.

[0017] In an embodiment, the first transistor and the first connection transistor may be transistors of a first type, and the second transistor and the third transistor may be transistors of a second type different from the first type.

[0018] In an embodiment, the second sensor may include: a first transistor connected between a reset voltage line and a second sensing node; a second transistor connected between a sensor driving voltage line and an intermediate node and including a gate electrode connected to the second sensing node; and a third transistor connected between the intermediate node and a second readout line and including a gate electrode connected to the scan line. The second readout line may output a second sensing signal.

[0019] In an embodiment, the first transistor and the first connection transistor may be transistors of a first type, and the second transistor and the third transistor may be transistors of a second type different from the first type.

[0020] In an embodiment, the display panel may further include: a third sensor including a third light sensing element connected to a third sensing node and outputting a third sensing signal; and a second connecting transistor electrically connecting the second sensing node of the second sensor and the third sensing node of the third sensor. The driving controller may turn on the second connecting transistor when determining that the signal-to-noise ratio of the readout signal is less than a threshold value, and otherwise turn off the second connecting transistor.

[0021] In an embodiment, a display device includes: a substrate layer; a circuit layer disposed on the substrate layer; and an element layer disposed on the circuit layer and including a light emitting element, a first light sensing element, and a second light sensing element. The circuit layer includes: a first connection transistor connected to the first light sensing element and a first sensing node, connected to the second light sensing element and the second sensing node, and electrically connecting the first sensing node and the second sensing node in response to a switch signal.

[0022] In an embodiment, the first light sensing element may include a first light sensing anode connected to the first sensing node and a first cathode connected to the driving voltage line, and the second light sensing element may include a second light sensing anode connected to the second sensing node and a second cathode connected to the driving voltage line.

[0023] In an embodiment, the circuit layer may further include: a first transistor connected between a reset voltage line and a first sensing node; a second transistor connected between a sensor drive voltage line and an intermediate node and including a gate electrode connected to the first sensing node; and a third transistor connected between the intermediate node and a first readout line and including a gate electrode connected to a scan line.

[0024] In an embodiment, the first transistor and the first connection transistor may be transistors of a first type, and the second transistor and the third transistor may be transistors of a second type different from the first type.

[0025] In an embodiment, the circuit layer may further include: a first transistor connected between a reset voltage line and a second sensing node; a second transistor connected between a sensor drive voltage line and an intermediate node and including a gate electrode connected to the second sensing node; and a third transistor connected between the intermediate node and a second readout line and including a gate electrode connected to a scan line.

[0026] In an embodiment, the element layer may further include a third light sensing element, and the circuit layer may further include: a second connecting transistor, connected to the third light sensing element and the third sensing node, connected to the second light sensing element and the second sensing node, and electrically connecting the second sensing node and the third sensing node in response to a switching signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a perspective view illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0029] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 4 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure.

[0031] Figure 5 is a circuit diagram of a pixel and a sensor according to an embodiment of the present disclosure.

[0032] Figure 6 Is used to describe Figure 5 A timing diagram of the operation of a pixel is shown in FIG.

[0033] Figure 7 Is used to describe Figure 5 A timing diagram of the operation of the sensor shown in FIG.

[0034] Figure 8is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0035] Fig. 9 is a diagram illustrating pixels and sensors provided in a display panel.

[0036] Fig.10 is a diagram illustrating a connection relationship between a first sensor, a second sensor, and a connection transistor.

[0037] Fig.11 Is used to describe Fig.10 A timing diagram of the operation of the sensor shown in FIG.

[0038] Fig.12 is a diagram illustrating a connection relationship among a first sensor, a second sensor, a third sensor, a first connection transistor, and a second connection transistor. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. In the specification, the statement that a first component (or region, layer, part, etc.) is "on" a second component, "connected to" a second component, or "coupled to" a second component means that the first component is directly on the second component, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween. The term "and / or" includes one or more combinations of associated listed items. The words "one" and "the (said)" are singular because they have a single referent, but the use of the singular form in the specification should not exclude the presence of more than one referent. In addition, the terms "under...", "below...", "on...", "above...", etc. are used to describe the relationship between the components illustrated in the accompanying drawings. These terms are relative and described with reference to the directions indicated in the accompanying drawings.

[0040] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0041] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0042] Reference Figure 1 and Figure 2 , the display device DD may be a device activated depending on an electrical signal. For example, the display device DD may be a mobile phone, a tablet computer, a car navigation system, a game console, or a wearable device, but the present disclosure is not limited thereto. An example in which the display device DD is a smart phone is shown in Figure 1 middle.

[0043] In addition, a bar-shaped rigid display device DD is shown as an example. Figure 1 For example, the display device DD may be a foldable, rollable, or slidable display device DD.

[0044] The upper surface of the display device DD may be defined as a display surface IS, and may have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD may be provided to a user through the display surface IS. Below, a normal direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the specification, the expression "when viewed from above the plane" or "in a plan view" may mean "when viewed in the third direction DR3". That is, the plane may be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0045] The display surface IS may be divided into a transparent area TA and a border area BZA. The transparent area TA may be an area in which the image IM is displayed. The user visually perceives the image IM through the transparent area TA. In an embodiment, the transparent area TA is illustrated as a quadrilateral whose vertices are rounded. However, since the transparent area TA may have various shapes and is not limited to any one embodiment, this is merely illustrated as an example.

[0046] The border area BZA is adjacent to the transparent area TA. The border area BZA may have a given color. The border area BZA may surround the transparent area TA. In this way, the shape of the transparent area TA may be substantially defined by the border area BZA. However, this is illustrated as an example. The border area BZA may be disposed adjacent to only one side of the transparent area TA, or may be omitted.

[0047] The display device DD can sense external input applied from the outside. The external input may include various types of input provided from the outside of the display device DD. For example, in addition to contact made by a part of the body (such as the user's hand US_F), the external input may include an external input (e.g., hovering) applied when the user's hand US_F is close to the display device DD or adjacent to the display device DD within a given distance. In addition, the external input may be one of various types such as a force type, a pressure type, a temperature type, and a light type. The external input may be provided by a separate device such as an active pen or a digitizer pen. In addition, the display device DD can sense biometric information of the user applied from the outside. For example, biometric information may be data used to identify or verify individuals based on their unique biometric or behavioral characteristics.

[0048] The appearance of the display device DD can be realized by the window WM and the housing EDC. For example, the window WM and the housing EDC can be connected to each other. The remaining components of the display device DD, such as the display module DM, can be accommodated in the space formed by the window WM and the housing EDC thus connected.

[0049] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded by an adhesive, or may have a glass substrate and a plastic film bonded by an adhesive.

[0050] The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, or metal, or may include a plurality of frames and / or plates composed of a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. A battery module (e.g., a battery) for supplying power for the overall operation of the display device DD may be interposed between the display module DM and the housing EDC.

[0051] The display module DM may include a display panel DP and an anti-reflection layer CFL.

[0052] The display panel DP may be a component that generates an image. The display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic inorganic light-emitting display panel, a quantum dot display panel, a micron light-emitting diode (micro-LED) display panel, or a nano LED display panel. Below, a description will be given based on the assumption that the display panel DP is an organic light-emitting display panel.

[0053] The display panel DP includes a base layer BL, a pixel layer PXL, and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded about a folding axis or a rigid display panel.

[0054] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, but is not limited thereto. The base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0055] The pixel layer PXL is disposed on the base layer BL. The pixel layer PXL may include a circuit layer DP_CL and an element layer DP_ED. The circuit layer DP_CL is interposed between the base layer BL and the element layer DP_ED.

[0056] In an embodiment, the circuit layer DP_CL includes at least one insulating layer and a circuit element. Below, the insulating layer included in the circuit layer DP_CL is referred to as an "intermediate insulating layer". In an embodiment, the intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The circuit layer DP_CL may further include a signal line connected to the pixel circuit and / or the sensor driving circuit.

[0057] In an example embodiment of the present disclosure, each of the multiple sensors may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, and the like. In addition, each of the multiple sensors may include an optical sensor that optically recognizes biometric information. According to an embodiment of the present disclosure, multiple sensors may be used to sense external inputs (e.g., a user's touch) as well as biometric information such as fingerprints. Accordingly, the display device DD may not include a separate input sensing layer for sensing external inputs. In this case, the thickness of the display device DD can be further reduced, and thus the flexibility can be improved. This can enable various types of display devices DD to be realized, for example, the above-mentioned foldable, rollable, or slidable display device DD.

[0058] The element layer DP_ED may include a light emitting element included in each of the pixels and a light sensing element included in each of the sensors. In an exemplary embodiment of the present disclosure, the light sensing element may be a photodiode. The light sensing element may be a sensor that senses light reflected by a user's fingerprint or reacts to light. Figure 8 The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0059] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture and / or oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc., but is not limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0060] The anti-reflection layer CFL may be disposed on the display panel DP. The anti-reflection layer CFL may reduce the reflectivity of external light incident from the outside of the display device DD. The anti-reflection layer CFL may be formed on the display panel DP by a continuous process, but the present disclosure is not limited thereto. For example, the anti-reflection layer CFL may include a color filter, a black matrix, and a planarization layer. The color filter may have a specific arrangement. For example, the color filter may be arranged in consideration of the color of light emitted from the pixels included in the display panel DP. In another embodiment, the anti-reflection layer CFL may include a black matrix and a reflection control layer. The reflection control layer may selectively absorb light belonging to a partial band among light reflected from the inside of the display panel DP and / or the electronic device and / or light incident from the outside of the display panel DP and / or the electronic device. In another embodiment, the anti-reflection layer CFL may be a polarizing film.

[0061] The display device DD according to an embodiment of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the anti-reflection layer CFL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, or a pressure sensitive adhesive (PSA).

[0062] Figure 3 is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0063] Reference Figure 3 , the display device DD includes a display panel DP, a driving controller 100 (e.g., a controller circuit), a data driver 200 (e.g., a first driver circuit), a voltage generator 500, and a readout circuit 600. The display panel DP includes a scan and sensor driver 300 (e.g., a second driver circuit) and an emission driver 400 (e.g., a third driver circuit).

[0064] The drive controller 100 enables an image to be displayed in the display panel DP. The drive controller 100 receives an input image signal RGB and a control signal CTRL. The drive controller 100 generates an output image signal DATA by converting the data format of the input image signal RGB so as to be suitable for the data driver 200 and the display panel DP. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and an emission control signal ECS.

[0065] The data driver 200 receives the data control signal DCS and the output image signal DATA from the driving controller 100. The data driver 200 converts the output image signal DATA into a data signal and then outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal refers to an analog voltage corresponding to the grayscale of the output image signal DATA.

[0066] The voltage generator 500 generates voltages for operation of the display panel DP. In an embodiment, the voltage generator 500 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, a reset voltage VRST, and a sensor driving voltage VCOM.

[0067] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, reset lines RSL, emission lines EML1 to EMLn, data lines DL1 to DLm, readout lines RL1 to RLk, pixels PX, and sensors SX.

[0068] The display panel DP may include a transparent area TA (refer to Figure 1 ) and the corresponding display area DA and the frame area BZA (shown in Figure 1 The pixels PX and the sensors SX may be disposed in the display area DA.

[0069] The scan and sensor driver 300 and the emission driver 400 may be disposed in the non-display area NDA of the display panel DP.

[0070] In an embodiment, the scan and sensor driver 300 is disposed adjacent to a first side of the display area DA in the display panel DP. The scan and sensor driver 300 receives a scan control signal SCS from the drive controller 100. The scan and sensor driver 300 may output a scan signal to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn in response to the scan control signal SCS, and may output a reset signal to the reset line RSL. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and GBL1 to GBLn extend from the scan and sensor driver 300 in a first direction DR1.

[0071] In an embodiment, the scan and sensor driver 300 may provide a switching signal to the switching lines SWL1 to SWLx in response to the scan control signal SCS.

[0072] The emission driver 400 is disposed adjacent to the second side of the display area DA in the display panel DP. The emission driver 400 receives the emission control signal ECS from the drive controller 100. The emission driver 400 may output emission signals to the emission lines EML1 to EMLn in response to the emission control signal ECS. The emission lines EML1 to EMLn extend from the emission driver 400 in a direction away from the first direction DR1 or in a direction opposite to the first direction DR1.

[0073] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, the reset line RSL and the emission lines EML1 to EMLn are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driver 200 in a direction away from the second direction DR2 and are arranged to be spaced apart from each other in the first direction DR1. For example, the data lines DL1 to DLm may extend from the data driver 200 in a direction opposite to the second direction DR2.

[0074] The plurality of pixels PX are electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and GBL1 to GBLn, the emission lines EML1 to EMLn and the data lines DL1 to DLm. In an embodiment, each of the plurality of pixels PX may be electrically connected to four scan lines and one emission line. For example, Figure 3 As illustrated in FIG. 1 , pixels PX belonging to the first row may be connected to scan lines GIL1, GCL1, GWL1, and GBL1 and emission lines EML1. Also, pixels PX belonging to the second row may be connected to scan lines GIL2, GCL2, GWL2, and GBL2 and emission lines EML2.

[0075] Each of the plurality of pixels PX includes a light emitting element ED (refer to Figure 5 ) and a pixel circuit PDC (refer to Figure 5 ). The pixel circuit PDC may include one or more transistors and one or more capacitors. The scanning and sensor driver 300 and the emission driver 400 may include transistors formed by the same process as the pixel circuit PDC.

[0076] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1 , and a second initialization voltage VINT2 from the voltage generator 500 .

[0077] Each of the sensors SX includes a light sensing element OPD (refer to Figure 5 ) and sensor drive circuit SDC (refer to Figure 5 ). The sensor driving circuit SDC may include transistors formed by the same process as the pixel circuit PDC.

[0078] Each of the sensors SX can be connected to a corresponding one of the scan lines GWL1 to GWLn and a corresponding one of the readout lines RL1 to RLk. The sensors SX can be commonly connected to the reset line RSL. In an embodiment, the number of sensors SX can be less than the number of pixels PX. However, the present disclosure is not limited thereto. In an embodiment, the number of sensors SX provided in the display panel DP can be greater than or equal to the number of pixels PX. In an embodiment, the number of readout lines RL1 to RLk is less than the number of data lines DL1 to DLm. That is, k < m. However, the present disclosure is not limited thereto. In an embodiment, the number of readout lines RL1 to RLk provided in the display panel DP can be greater than or equal to the number of data lines DL1 to DLm.

[0079] The readout circuit 600 can receive sensing signals from the readout lines RL1 to RLk and can output a readout signal RS to the driving controller 100.

[0080] In an embodiment, the sensors SX and the readout circuit 600 operate in a biometric sensing mode or a touch sensing mode. In an embodiment, the sensors SX and the readout circuit 600 sense information about the user's blood pressure or fingerprint in the biometric sensing mode. In an embodiment, the sensors SX and the readout circuit 600 sense the position where the user touches in the touch sensing mode.

[0081] In Figure 3 In the example illustrated in, the scan and sensor driver 300 is arranged to face the emission driver 400, and the pixels PX are interposed therebetween, but the present disclosure is not limited thereto. For example, the scan and sensor driver 300 and the emission driver 400 can be arranged side by side at a position adjacent to one of the first side and the second side of the display area DA in the display panel DP. In an embodiment, the scan and sensor driver 300 and the emission driver 400 can be implemented with a single circuit.

[0082] In an embodiment, the display panel DP can further include connection transistors CT11 to CT1x. The connection transistor CT11 can be connected to the switch line SWL1, and the connection transistor CT1x can be connected to the switch line SWLx. How the connection transistors CT11 to CT1x and the sensors SX are connected will be described in detail below.

[0083] Figure 4 is an enlarged plan view of a partial area of the display panel DP according to an embodiment of the present disclosure.

[0084] Referring to Figure 4 , pixels PXR, PXG, and PXB are provided in the display panel DP. Each of the pixels PXR, PXG, and PXB includes a light-emitting element (one of ED_R, ED_G, and ED_B) and a pixel circuit PDC. Figure 3 Each of the pixels PX shown in FIG. Figure 4 Each of the sensors SX includes a light sensing element OPD and a sensor driving circuit SDC.

[0085] Reference Figure 4 , pixels PXR and PXB and sensors SX are arranged at odd rows (ie, the first row and the third row). In an embodiment, for each of the first row and the third row, pixels PXR and PXB and sensors SX are alternately arranged in the first direction DR1. Only pixels PXG are arranged at the second row.

[0086] In an embodiment, the pixel PXR may include a light emitting element ED_R that outputs light of a first color (e.g., red). The pixel PXG may include a light emitting element ED_G that outputs light of a second color (e.g., green). The pixel PXB may include a light emitting element ED_B that outputs light of a third color (e.g., blue).

[0087] like Figure 4 As illustrated in FIG. 1 , the pixels PXR and PXB may be alternately and repeatedly disposed in the second direction DR2 and the first direction DR1 . The pixels PXG may be arranged in the second direction DR2 such that each pixel PXG is interposed between two light sensing elements OPD.

[0088] The structure in which the pixels PX and the sensors SX are arranged may be variously changed or modified without limitation. Figure 4 The embodiment shown in FIG.

[0089] In an embodiment, the light emitting element ED_R may be larger in size than the light emitting element ED_G. In addition, the size of the light emitting element ED_B may be larger than or equal to the size of the light emitting element ED_R. The size of each of the light emitting elements ED_R, ED_G, and ED_B is not limited thereto and may be variously changed and applied. For example, in another embodiment of the present disclosure, the light emitting elements ED_R, ED_G, and ED_B may have the same size.

[0090] In addition, each of the light emitting elements ED_R, ED_G, and ED_B can be implemented in various shapes such as polygonal, circular, and elliptical. In an embodiment, the light emitting elements ED_R, ED_G, and ED_B can be implemented in different shapes. For example, the light emitting element ED_G can be circular, and the light emitting elements ED_R and ED_B can be quadrilateral.

[0091] In an embodiment, the area occupied by the sensor driving circuit SDC may be different from the area occupied by the pixel circuit PDC. For example, the area of ​​the sensor driving circuit SDC may be smaller than the area of ​​the pixel circuit PDC.

[0092] Figure 5 is a circuit diagram of a pixel PX and a sensor SX according to an embodiment of the present disclosure.

[0093] Figure 5 Show Figure 3 One pixel PX among the plurality of pixels PX shown in FIG. Figure 3 One sensor SX among the multiple sensors SX shown in the figure. Figure 3 Each of the plurality of pixels PX illustrated in FIG. Figure 5 The pixel PX shown in FIG. has the same circuit configuration. Figure 3 Each of the plurality of sensors SX shown in FIG. Figure 5 The sensor SX shown in FIG. 1 has the same circuit configuration.

[0094] Reference Figure 5 , the pixel PX includes a pixel circuit PDC and at least one light emitting element ED. The light emitting element ED may be a light emitting diode. As an example of the present disclosure, the light emitting element ED may be an organic light emitting diode including an organic emission layer. The pixel circuit PDC according to the embodiment includes first to seventh transistors T1, T2, T3, T4, T5, T6 and T7 and a capacitor Cst.

[0095] The third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 may be N-type transistors using an oxide semiconductor as a semiconductor layer, and each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all of the first transistor T1 to the seventh transistor T7 may be P-type transistors. In an embodiment, all of the first transistor T1 to the seventh transistor T7 may be N-type transistors. In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the others thereof may be P-type transistors. The construction of the pixel circuit PDC according to the present disclosure is not limited to Figure 5 The embodiment shown in FIG. Figure 5 The pixel circuit PDC illustrated in FIG. 1 is provided merely as an example, and the configuration of the pixel circuit PDC may be variously modified and implemented.

[0096] The pixel PX is electrically connected to the scan lines GILi, GCLi, GWLi and GBLi, the emission lines EMLi and the data lines DLj. The scan lines GILi, GCLi, GWLi and GBLi can transmit scan signals GIi, GCi, GWi and GBi, respectively, and the emission lines EMLi can transmit emission control signals EMi. The data lines DLj transmit data signals Dj. The data signals Dj can have the same value as that input to the display device DD (refer to Figure 3 ) The first to fourth driving voltage lines VL1, VL2, VL3 and VL4 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1 and the second initialization voltage VINT2, respectively.

[0097] The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 through the fifth transistor T5, a second electrode electrically connected to the anode of the light emitting element ED through the sixth transistor T6, and a gate electrode connected to the first end of the capacitor Cst. The first transistor T1 may receive a data signal Dj transmitted through the data line DLj depending on a switching operation of the second transistor T2, and may supply a driving current Id to the light emitting element ED.

[0098] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 may be turned on depending on the scan signal GWi transmitted through the scan line GWLi, and may transmit the data signal Dj from the data line DLj to the first electrode of the first transistor T1.

[0099] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 may be turned on depending on the scan signal GCi transmitted through the scan line GCLi. Therefore, the gate electrode and the second electrode of the first transistor T1 may be connected to each other, that is, the first transistor T1 may be diode-connected.

[0100] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the fourth driving voltage line VL4 through which the second initialization voltage VINT2 is transmitted, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on depending on the scan signal GIi transmitted through the scan line GILi. Therefore, the second initialization voltage VINT2 can be transmitted to the gate electrode of the first transistor T1. In this way, the voltage of the gate electrode of the first transistor T1 can be initialized. This operation can be referred to as an "initialization operation".

[0101] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emission line EMLi.

[0102] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a gate electrode connected to the emission line EMLi.

[0103] The fifth transistor T5 and the sixth transistor T6 may be turned on at the same time depending on the emission control signal EMi transmitted through the emission line EMLi. Therefore, the first driving voltage ELVDD may be compensated by the diode-connected transistor T1 to be supplied to the light emitting element ED.

[0104] The seventh transistor T7 includes a first electrode connected to the anode of the light emitting element ED, a second electrode connected to the third driving voltage line VL3, and a gate electrode connected to the scanning line GBLi. The seventh transistor T7 can be turned on depending on the scanning signal GBi transmitted through the scanning line GBLi, and can electrically connect the anode of the light emitting element ED to the third driving voltage line VL3.

[0105] A first end of the capacitor Cst is connected to the gate electrode of the first transistor T1, and a second end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. However, the structure of the pixel PX is not limited to Figure 5 For example, in one pixel PX, the number of transistors, the number of capacitors, and their connection relationship may be variously changed or modified.

[0106] The sensor SX is electrically connected to the scan line GWLi, the reset line RSL, and the readout line RLj.

[0107] The sensor SX includes a light sensing element OPD and a sensor driving circuit SDC. The light sensing element OPD may be a photodiode. As an example of the present disclosure, the light sensing element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. The light sensing anode O_AE of the light sensing element OPD may be connected to a sensing node SN, and its light sensing cathode may be connected to a second driving voltage line VL2 transmitting a second driving voltage ELVSS. In an embodiment, the light sensing cathode of the light sensing element OPD in the sensor SX receives the second driving voltage ELVSS supplied to the cathode of the light emitting element ED in the pixel PX, but the present disclosure is not limited thereto. The voltage supplied to the light sensing cathode of the light sensing element OPD in the sensor SX may be a voltage different from the second driving voltage ELVSS.

[0108] The sensor driving circuit SDC includes transistors ST1, ST2 and ST3. The transistors ST1, ST2 and ST3 may be a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3, respectively. The transistors ST1, ST2 and ST3 may also be referred to as a "first transistor ST1", a "second transistor ST2" and a "third transistor ST3", respectively.

[0109] Some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and others thereof may be N-type transistors. Figure 5 The third transistor T3 of the pixel PX illustrated in FIG. 1 is the same N-type transistor, and the amplifying transistor ST2 and the output transistor ST3 can be connected with Figure 5 The first transistor T1 and the second transistor T2 of the pixel PX illustrated in the figure are the same P-type transistors. However, the present disclosure is not limited thereto. In an embodiment, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors. In another embodiment, all of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be N-type transistors.

[0110] The reset transistor ST1 includes a first electrode connected to a reset voltage line VL5 receiving a reset voltage VRST, a second electrode connected to a sensing node SN, and a gate electrode connected to a reset line RSL receiving a reset signal RST. The reset transistor ST1 can reset the potential of the sensing node SN to the reset voltage VRST in response to the reset signal RST.

[0111] The amplifying transistor ST2 includes a first electrode connected to a sensor driving voltage line VL7 receiving a sensor driving voltage VCOM, a second electrode connected to an intermediate node IN, and a gate electrode connected to a sensing node SN. In an embodiment, the voltage level of the sensor driving voltage VCOM may be equal to the voltage level provided to the sensor driving voltage VCOM. Figure 5 The amplifying transistor ST2 may provide a current corresponding to the potential of the sensing node SN to the intermediate node IN.

[0112] The output transistor ST3 includes a first electrode connected to the intermediate node IN, a second electrode connected to the readout line RLj, and a gate electrode connected to the scan line GWLi receiving the scan signal GWi. The output transistor ST3 may transmit the sensing signal FSj to the readout line RLj in response to the scan signal GWi.

[0113] The circuit configuration of the sensor driving circuit SDC according to the present disclosure is not limited to Figure 5 The embodiment shown in FIG. Figure 5 The sensor driving circuit SDC illustrated in FIG. 1 is provided merely as an example, and the configuration of the sensor driving circuit SDC may be variously modified and implemented.

[0114] Figure 6 Is used to describe Figure 5 0 is a timing diagram of the operation of the pixel PX illustrated in FIG.

[0115] Reference Figure 5 and Figure 6 , one frame period Fs may include an emission period EP and a non-emission period NEP. The emission period EP may correspond to a low level period (ie, an effective period) of the emission control signal EMi, and the non-emission period NEP may correspond to a high level period (ie, an invalid period) of the emission control signal EMi.

[0116] The non-emission period NEP may include an initialization period and a data programming and compensation period.

[0117] When a high-level scan signal GIi is provided through the scan line GILi during the initialization period, the fourth transistor T4 is turned on. The second initialization voltage VINT2 is transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, and thus, the first transistor T1 is initialized.

[0118] In an embodiment, when a high-level scan signal GCi is supplied through the scan line GCLi during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is diode-connected by the third transistor T3 thus turned on, and is forward biased. In this case, when a low-level scan signal GWi is supplied through the scan line GWLi, the second transistor T2 is turned on. In this way, a compensation voltage obtained by subtracting a threshold voltage of the first transistor T1 from a voltage of a data signal Dj provided by the data line DLj is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 may be a compensation voltage.

[0119] Since the first driving voltage ELVDD and the compensation voltage are respectively applied to opposite ends of the capacitor Cst, charges of an amount corresponding to the difference between the first driving voltage ELVDD and the compensation voltage may be stored in the capacitor Cst.

[0120] At the same time, the seventh transistor T7 is turned on in response to the low-level scan signal GBi transmitted through the scan line GBLi. When the seventh transistor T7 is turned on, the anode of the light emitting element ED is electrically connected to the third driving voltage line VL3. Accordingly, the anode of the light emitting element ED can be initialized with the first initialization voltage VINT1.

[0121] Thereafter, during the emission period EP, the emission control signal EMi supplied by the emission line EMLi changes from a high level to a low level. During the emission period EP, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level emission control signal EMi. In this case, the drive current Id is generated depending on the difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and is supplied to the light emitting element ED through the sixth transistor T6. That is, the drive current Id flows through the light emitting element ED. The light emitting element ED can emit light having a brightness corresponding to the drive current Id.

[0122] Figure 7 Is used to describe Figure 5 0 is a timing diagram of the operation of the sensor SX shown in FIG.

[0123] Reference Figure 5 and Figure 7 When the reset signal RST turns to a high level, the reset transistor ST1 is turned on. When the reset transistor ST1 is turned on, the sensing node SN may be initialized with the reset voltage VRST.

[0124] After the reset signal RST turns to a low level, the sensor SX is exposed to light during the light exposure period LE. When the user's hand touches the display surface, the light sensing element OPD may generate photoelectrons corresponding to the light reflected by the user's hand, and the generated photoelectrons may be accumulated at the sensing node SN.

[0125] The amplification transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the amount of photoelectrons (or charges) of the sensing node SN input to the gate electrode of the amplification transistor ST2 .

[0126] When the scanning signal GWi is at an invalid level (i.e., at a high level), the output transistor ST3 is maintained in a cut-off state. When the scanning signal GWi is changed to an effective level (i.e., a low level), the output transistor ST3 is turned on. When the output transistor ST3 is turned on, a sensing signal FSj corresponding to the current flowing through the amplifying transistor ST2 can be output to the readout line RLj. That is, a sensing signal FSj corresponding to the amount of light sensed by the light sensing element OPD can be output to the readout line RLj.

[0127] In an embodiment, the scan signal GWi may be Figure 5and Figure 6 The scanning signals GWi shown in FIG. are the same signal. That is, Figure 3 The pixels PX and the sensors SX at the i-th row illustrated in can receive the same scan signal GWi.

[0128] In an embodiment, in the biometric sensing mode, the optical sensing element OPD may generate photoelectrons corresponding to light reflected by the ridges of the fingerprint or the valleys between the ridges of the fingerprint. The sensing signal FSj output from the sensor SX in the biometric sensing mode may be a signal corresponding to the fingerprint of the user. For example, in the first biometric sensing mode, the fingerprint of the user may be derived from the sensing signal FSj.

[0129] In an embodiment, in the biometric sensing mode, the optical sensing element OPD may generate photoelectrons corresponding to light reflected from blood vessels located below the dermis of the user's skin. During systole, blood moves toward the periphery, increasing arterial blood volume; during diastole, blood volume decreases. This change in blood volume changes the reflected light. The sensing signal FSj output from the sensor SX in the biometric sensing mode may be a signal corresponding to the user's blood pressure. For example, in the second biometric sensing mode, the user's blood pressure may be derived from the sensing signal FSj.

[0130] In an embodiment, in the touch sensing mode, the light sensing element OPD may generate photoelectrons corresponding to light reflected by a user's touch. The sensing signal FSj output from the sensor SX in the touch sensing mode may be a signal indicating whether a user has made a touch.

[0131] Figure 8 is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 The first transistor T1, the third transistor T3 and the reset transistor ST1 are partially shown in FIG. Figure 8 middle.

[0132] Reference Figure 8 , the display panel DP may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, a device layer DP_ED, and an encapsulation layer TFE.

[0133] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin material. In an embodiment, the synthetic resin layer is a polyimide resin layer, but is not limited thereto. The synthetic resin layer may include at least one of an acrylic resin (e.g., a methacrylic resin), polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, and the like.

[0134] At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of a plurality of layers. The plurality of inorganic layers may constitute barrier layers BR1 and BR2 and / or a buffer layer BFL to be described below. The barrier layers BR1 and BR2 and the buffer layer BFL may be selectively provided.

[0135] The barrier layers BR1 and BR2 prevent foreign matter from being introduced from the outside. The barrier layers BR1 and BR2 may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plural, and the plural silicon oxide layers and the plural silicon nitride layers may be alternately stacked.

[0136] The barrier layers BR1 and BR2 may include a first barrier layer BR1 and a second barrier layer BR2. A first bottom metal layer BMC1 may be interposed between the first barrier layer BR1 and the second barrier layer BR2. In an embodiment of the present disclosure, the first bottom metal layer BMC1 may be omitted.

[0137] The buffer layer BFL may be disposed on the barrier layers BR1 and BR2. The buffer layer BFL may increase the bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0138] The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern may include low temperature polycrystalline silicon.

[0139] Figure 8 Only a portion of the first semiconductor pattern disposed on the buffer layer BFL is shown, and the first semiconductor pattern may be further disposed in any other region. The first semiconductor pattern may be arranged across pixels according to a specific rule. The electrical characteristics of the first semiconductor pattern may vary depending on whether it is doped. The first semiconductor pattern may include a first region having a high electrical conductivity and a second region having a low electrical conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped with a concentration lower than that of the first region.

[0140] The conductivity of the first region may be higher than that of the second region, and the first region may substantially act as an electrode or a signal line. The second region may substantially correspond to an active region (or channel) of a transistor. In other words, a portion of the first semiconductor pattern may be an active region of a transistor, another portion of the first semiconductor pattern may be a source region or a drain region of the transistor, and the other portion of the first semiconductor pattern may be a connection electrode or a connection signal line.

[0141] The first electrode SE1, the channel portion A1, and the second electrode D1 of the first transistor T1 are formed of the first semiconductor pattern. The first electrode SE1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions.

[0142] A portion of the connection signal line CSL formed by the first semiconductor pattern is shown in FIG. Figure 8 In the plan view, the connection signal line CSL can be electrically connected to the sixth transistor T6 (refer to Figure 5 )'s second electrode.

[0143] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with a plurality of pixels collectively and may cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may be a single silicon oxide layer. In addition to the first insulating layer 10, the insulating layer of the circuit layer DP_CL to be described below may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but the present disclosure is not limited thereto.

[0144] The gate electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate electrode G1 may be a part of the metal pattern. The gate electrode G1 of the first transistor T1 overlaps with the channel portion A1 of the first transistor T1. The gate electrode G1 of the first transistor T1 may serve as a mask in a process of doping the first semiconductor pattern. The gate electrode G1 may include titanium (Ti), silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), or a plurality of other materials. x N y ), tungsten (W), tungsten nitride (W x N y ), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but the present disclosure is not limited thereto.

[0145] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multilayer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In an embodiment, the second insulating layer 20 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer.

[0146] The upper electrode UE and the second bottom metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate electrode G1. The upper electrode UE may be a portion of the metal pattern. A portion of the gate electrode G1 and the upper electrode UE overlapping the portion of the gate electrode G1 may define a capacitor Cst (refer to Figure 5 According to an embodiment of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may serve as a mask for forming the insulating pattern by the second insulating layer 20.

[0147] The second bottom metal layer BMC2 may be disposed to correspond to a lower portion of the oxide thin film transistor (eg, the third transistor T3 ). The second bottom metal layer BMC2 may be supplied with a constant voltage or signal.

[0148] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE and the second bottom metal layer BMC2. The third insulating layer 30 may have a single layer or a multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0149] The second semiconductor pattern may be disposed on the third insulating layer 30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions that are distinguished from each other depending on whether the metal oxide is reduced. The region in which the metal oxide is reduced (hereinafter referred to as a "reduction region") has a higher conductivity than the region in which the metal oxide is not reduced (hereinafter referred to as a "non-reduction region"). The reduction region may substantially act as a source / drain or signal line of a transistor. The non-reduction region actually corresponds to an active region (alternatively, a semiconductor region or a channel) of a transistor. In other words, a portion of the second semiconductor pattern may be an active region of a transistor, another portion of the second semiconductor pattern may be a source region or a drain region of a transistor, and other portions of the second semiconductor pattern may be connecting electrodes or connecting signal lines.

[0150] The first electrode SE3, the channel portion A3 and the second electrode D3 of the third transistor T3 are formed by the second semiconductor pattern. The first electrode SE3 and the second electrode D3 include metal reduced from a metal oxide semiconductor. When viewed in a cross-sectional view, the first electrode SE3 and the second electrode D3 may extend from the channel portion A3 in opposite directions.

[0151] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may overlap the plurality of pixels in common and may cover the second semiconductor pattern. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0152] The gate electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The gate electrode G3 may be a part of the metal pattern. The gate electrode G3 of the third transistor T3 overlaps with the channel portion A3 of the third transistor T3. The gate electrode G3 may act as a mask in the process of doping the second semiconductor pattern. According to an embodiment of the present disclosure, the fourth insulating layer 40 may be replaced with an insulating pattern.

[0153] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the gate electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0154] The first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 may be connected to the connection signal line CSL through a first contact hole CH1 penetrating the first to fifth insulating layers 10, 20, 30, 40, and 50.

[0155] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include: a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS); a polymer derivative having a phenol group; an acrylic polymer; an imide-based polymer; an aryl ether-based polymer; an amide-based polymer; a fluorine-based polymer; a paraxylene-based polymer; a vinyl alcohol-based polymer; or a blend thereof.

[0156] The second connection electrode CNE20 may be disposed on the sixth insulating layer 60. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the second connection electrode CNE20. The seventh insulating layer 70 may be an organic layer.

[0157] The first electrode layer is disposed on the circuit layer DP_CL. The pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a first anode R_AE and a light sensing anode O_AE. In an embodiment, the first anode R_AE and the light sensing anode O_AE are disposed on the seventh insulating layer 70. The first anode R_AE may be connected to the second connection electrode CNE20 through a third contact hole CH3 penetrating the seventh insulating layer 70. The first anode R_AE corresponding only to red light is shown in FIG. Figure 8 However, the first electrode layer may further include a second anode corresponding to green light and a third anode corresponding to blue light.

[0158] A first film opening PDL-OP1 and a second film opening PDL-OP2 may be provided in the pixel defining layer PDL. The first film opening PDL-OP1 exposes at least a portion of the first anode R_AE. The second film opening PDL-OP2 exposes at least a portion of the light sensing anode O_AE.

[0159] In an embodiment of the present disclosure, the pixel defining layer PDL may further include a black material. The pixel defining layer PDL may further include a black organic dye or pigment such as carbon black or aniline black. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repellent organic material.

[0160] like Figure 8 As illustrated in , the display panel DP may include an emission area PXA-R, a non-emission area NPXA-R, a sensing area SA, and a non-sensing area NSA. The non-emission area NPXA-R is adjacent to the emission area PXA-R, and the sensing area SA is adjacent to the non-sensing area NSA. The non-emission area NPXA-R may surround the emission area PXA-R. In an embodiment, the emission area PXA-R is defined to correspond to a portion of the first anode R_AE exposed by the first film opening PDL-OP1. The non-sensing area NSA may surround the sensing area SA. In an embodiment, the sensing area SA is defined to correspond to a portion of the light sensing anode O_AE exposed by the second film opening PDL-OP2.

[0161] The emission layer may be disposed on the first electrode layer. The emission layer may include a red emission layer, a green emission layer, and a blue emission layer. The red emission layer, the green emission layer, and the blue emission layer may be disposed in corresponding regions of the first film opening PDL-OP1, respectively. The red emission layer, the green emission layer, and the blue emission layer may be independently formed on Figure 4. In the red pixel PXR, green pixel PXG and blue pixel PXB illustrated in FIG. Each of the red emission layer, the green emission layer and the blue emission layer may include an organic material and / or an inorganic material. The red emission layer, the green emission layer and the blue emission layer may generate corresponding color light. For example, the emission layer R_EL may generate red light. An example diagram in which the emission layer R_EL is disposed in an area corresponding to the first film opening PDL-OP1 is shown in FIG. Figure 8 middle.

[0162] In the embodiment, the patterned red emission layer, green emission layer and blue emission layer are described as examples, but one emission layer can be commonly arranged in multiple emission areas. In this case, the emission layer can generate white light or blue light. In addition, the emission layer can have a multilayer structure called "series".

[0163] The emission layer R_EL may include a low molecular weight organic material or a high molecular weight organic material as a light emitting material. The cathode CE is disposed on the emission layer R_EL. As an example of the present disclosure, the cathode CE may be commonly disposed in the emission region PXA-R, the non-emission region NPXA-R, and the non-pixel region NPA.

[0164] The circuit layer DP_CL may further include a sensor driving circuit SDC (refer to Figure 5 ). For ease of description, the reset transistor ST1 included in the sensor driving circuit SDC is illustrated. The first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 are formed by a second semiconductor pattern. In an embodiment, the first electrode STS1 and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. The fourth insulating layer 40 is provided to cover the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. The gate electrode STG1 of the reset transistor ST1 is provided on the fourth insulating layer 40. In an embodiment, the gate electrode STG1 may be a part of the metal pattern. The gate electrode STG1 of the reset transistor ST1 overlaps with the channel portion STA1 of the reset transistor ST1.

[0165] In an embodiment of the present disclosure, the reset transistor ST1 is disposed on the same layer as the third transistor T3. That is, the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1 may be formed by the same process as the first electrode SE3, the channel portion A3, and the second electrode D3 of the third transistor T3. The gate electrode STG1 of the reset transistor ST1 may be formed simultaneously with the gate electrode G3 of the third transistor T3 by the same process. Although not illustrated separately, the first electrode and the second electrode of each of the amplifying transistor ST2 and the output transistor ST3 of the sensor driving circuit SDC may be formed by the same process as the first electrode SE1 and the second electrode D1 of the first transistor T1. The reset transistor ST1 and the third transistor T3 may be formed on the same layer by the same process. Accordingly, since no additional process is required for forming the reset transistor ST1, the efficiency of the process may be improved, and the manufacturing cost may be reduced.

[0166] Figure 3 The connection transistors CT11 to CT1x shown in the figure may also be provided on the same layer as the reset transistor ST1.

[0167] The device layer DP_ED may further include a light sensing device OPD. Only the light sensing device OPD is shown in FIG. Figure 8 middle.

[0168] The light sensing element OPD may include a light sensing anode O_AE, a photoelectric conversion layer O_RL, and a photocathode O_CE. The light sensing anode O_AE may be disposed on the same layer as the first electrode layer. That is, the light sensing anode O_AE may be disposed on the circuit layer DP_CL and may be formed simultaneously with the first anode R_AE through the same process.

[0169] The second film opening PDL-OP2 of the pixel defining layer PDL exposes at least a portion of the light sensing anode O_AE. The photoelectric conversion layer O_RL is disposed on the portion of the light sensing anode O_AE exposed by the second film opening PDL-OP2. The photoelectric conversion layer O_RL may include an organic photoelectric sensing material. The photocathode O_CE may be disposed on the photoelectric conversion layer O_RL. The photocathode O_CE may be formed simultaneously with the cathode CE by the same process. In an exemplary embodiment of the present disclosure, the photocathode O_CE is formed integrally with the cathode CE. For example, a single layer may be used to form the photocathode O_CE and the cathode CE.

[0170] Each of the light sensing anode O_AE and the photocathode O_CE can receive an electrical signal. The photocathode O_CE and the light sensing anode O_AE can receive different signals. Accordingly, a given electric field can be formed between the light sensing anode O_AE and the photocathode O_CE. The photoelectric conversion layer O_RL generates an electrical signal corresponding to the light incident on the sensor. The photoelectric conversion layer O_RL can generate charges by absorbing the energy of the incident light. For example, the photoelectric conversion layer O_RL may include a photosensitive semiconductor material.

[0171] The charges generated by the photoelectric conversion layer O_RL change the electric field between the light sensing anode O_AE and the photocathode O_CE. The amount of charge generated by the photoelectric conversion layer O_RL may vary depending on whether light is incident on the light sensing element OPD, the amount of light incident on the light sensing element OPD, and the intensity of light incident on the light sensing element OPD. In this way, the electric field formed between the light sensing anode O_AE and the photocathode O_CE may vary. The light sensing element OPD according to the present disclosure may obtain one of the multiple pieces of information about the user's fingerprint, blood pressure, and touch by changing the electric field between the light sensing anode O_AE and the photocathode O_CE.

[0172] However, this is provided only as an example. For example, the light sensing element OPD may also include a phototransistor in which the photoelectric conversion layer O_RL is used as an active layer. In this case, the light sensing element OPD may obtain fingerprint information by sensing the amount of current flowing through the phototransistor. The light sensing element OPD according to an embodiment of the present disclosure may include various photoelectric conversion elements each capable of generating an electrical signal in response to a change in the amount of light, but the present disclosure is not limited to a specific embodiment.

[0173] The encapsulation layer TFE is disposed on the element layer DP_ED. The encapsulation layer TFE includes at least one inorganic layer and / or at least one organic layer. According to an embodiment of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer interposed therebetween. According to an embodiment of the present disclosure, the thin film encapsulation layer may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0174] The inorganic layer of the encapsulation layer TFE protects the light emitting element ED_R and the light sensing element OPD from moisture / oxygen, and the organic layer of the encapsulation layer TFE protects the light emitting element ED_R and the light sensing element OPD from foreign matter such as dust particles. The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., but the present disclosure is not particularly limited thereto. The encapsulation organic layer may include an acryl-based organic layer, and the present disclosure is not limited thereto.

[0175] Fig. 9is a diagram illustrating pixels PX11 to PX44 and sensors SX11 to SX34 provided in a display panel DP according to an embodiment. Figure 3 Some of the pixels PX and sensors SX of the display panel DP shown in FIG. Fig. 9 middle.

[0176] Reference Fig. 9 , pixels PX11, PX12, PX13, and PX14 and sensors SX11, SX12, SX13, and SX14 are arranged in a first row R1 of the display panel DP. Pixels PX21, PX22, PX23, and PX24 are arranged in a second row R2 of the display panel DP. Pixels PX31, PX32, PX33, and PX34 and sensors SX31, SX32, SX33, and SX34 are arranged in a third row R3 of the display panel DP. Pixels PX41, PX42, PX43, and PX44 are arranged in a fourth row R4 of the display panel DP.

[0177] Fig. 9 The arrangement of the pixels PX11 to PX44 and the sensors SX11 to SX34 illustrated in FIG. 1 is provided merely as an example, and the present disclosure is not limited thereto.

[0178] In an embodiment, the display panel DP further includes connection transistors CT11 , CT12 , CT31 , and CT32 .

[0179] The connection transistor CT11 may electrically connect the sensors SX11 and SX12 in response to a switch signal SW1 received through the switch line SWL1. For example, the switch signal SW1 may be applied to a gate of the connection transistor CT11 by a control circuit (eg, 100).

[0180] The connection transistor CT12 may electrically connect the sensors SX13 and SX14 in response to a switch signal SW2 received through the switch line SWL2. For example, the switch signal SW2 may be applied to the gate of the connection transistor CT12 by the control circuit.

[0181] The connection transistor CT31 may electrically connect the sensors SX31 and SX32 in response to a switch signal SW1 received through the switch line SWL1. For example, the switch signal SW1 may be applied to a gate of the connection transistor CT31 by a control circuit.

[0182] The connection transistor CT32 may electrically connect the sensors SX33 and SX34 in response to a switch signal SW2 received through the switch line SWL2. For example, the switch signal SW2 may be applied to the gate of the connection transistor CT32 by the control circuit.

[0183] An example diagram in which the connection transistors CT31 and CT32 operate in response to the switch signals SW1 and SW2, respectively, is shown in FIG. Fig. 9 In the embodiment, the connection transistors CT31 and CT32 operate in response to a signal different from the switch signals SW1 and SW2.

[0184] Fig.10 is a diagram illustrating a connection relationship among a first sensor SX11 , a second sensor SX12 , and a connection transistor CT11 according to an embodiment.

[0185] Reference Fig.10 Each of the first sensor SX11 and the second sensor SX12 can be connected with Figure 5 The sensor SX illustrated in FIG. 1 includes the same circuit configuration. For ease of description, some of the components of the first sensor SX11 and the second sensor SX12 are labeled with the same reference numerals as those in FIG. Figure 5 The reference numerals of the sensors SX illustrated in FIG. 1 are the same, and thus additional description will be omitted to avoid redundancy.

[0186] The connection transistor CT11 is connected between the light sensing anode O_AE1 of the first light sensing element OPD1 in the first sensor SX11 and the light sensing anode O_AE2 of the second light sensing element OPD2 in the second sensor SX12. That is, the connection transistor CT11 is connected between the first sensing node SN1 in the first sensor SX11 and the second sensing node SN2 in the second sensor SX12. The gate electrode of the connection transistor CT11 is connected to the switch line SWL1. The connection transistor CT11 may be connected between the gates of the amplification transistors ST2 of the sensors SX11 and SX12.

[0187] In an embodiment, the connection transistor CT11 may be the same N-type transistor as the reset transistor ST1 of each of the first sensor SX11 and the second sensor SX12 . However, the present disclosure is not limited thereto.

[0188] When the switching signal SW1 transmitted through the switching line SWL1 is at an effective level (e.g., a high level), the connecting transistor CT11 may electrically connect the first sensing node SN1 in the first sensor SX11 and the second sensing node SN2 in the second sensor SX12. Similarly, when the switching signal SW1 transmitted through the switching line SWL1 is at an ineffective or deactivated level, the first sensing node SN1 may be disconnected from the second sensing node SN2.

[0189] Reference Figure 3 and Fig.10The readout circuit 600 may receive the first sensing signal FS1 from the first sensor SX11 and may receive the second sensing signal FS2 from the second sensor SX12. The readout circuit 600 provides a readout signal RS corresponding to the first sensing signal FS1 and the second sensing signal FS2 to the driving controller 100.

[0190] In the embodiment, when the amount of external light or the amount of light from the pixel PX (refer to Figure 3 ) is small (i.e., when the illumination is low) or less than a threshold amount, the signal-to-noise ratio of the first sensing signal FS1 and the second sensing signal FS2 received from the first sensor SX11 and the second sensor SX12, respectively, may be small or the first sensing signal FS1 and the second sensing signal FS2 may be weak. In this case, it is difficult for the readout circuit 600 to perform a normal sensing operation based on the first sensing signal FS1 and the second sensing signal FS2. The readout circuit 600 may provide the drive controller 100 with a readout signal RS indicating that a normal sensing operation is impossible. For example, when a normal sensing operation is impossible, the readout circuit 600 may provide the drive controller 100 with a readout signal RS having a preset specific value. For example, when the amount of external light or the amount of light output from one or more of the pixels PX is less than a threshold amount, the system may conclude that a normal sensing operation is impossible.

[0191] When the read signal RS has the specific value, the drive controller 100 provides the scan control signal SCS to the scan and sensor driver 300 so that the switch signal SW1 is set to an effective level (e.g., a high level). The drive controller 100 turns on the connection transistor CT11 when determining that the signal-to-noise ratio of the read signal RS is less than the threshold value, and otherwise turns off the connection transistor CT11.

[0192] The scan and sensor driver 300 outputs a high-level switching signal SW1 to the switching line SWL1 in response to the scan control signal SCS.

[0193] When the switch signal SW1 is at a high level, the connection transistor CT11 may be turned on, and thus, the light sensing anode O_AE1 of the first light sensing element OPD1 in the first sensor SX11 and the light sensing anode O_AE2 of the second light sensing element OPD2 in the second sensor SX12 may be electrically connected.

[0194] Fig.11 Is used to describe Fig.10 2 is a timing diagram of the operation of the sensors SX11 and SX12 shown in FIG.

[0195] Reference Fig.10 and Fig.11, when the reset signal RST turns to a high level, the reset transistor ST1 of each of the first sensor SX11 and the second sensor SX12 is turned on. When the reset transistor ST1 of the first sensor SX11 is turned on, the first sensing node SN1 may be initialized with the reset voltage VRST. When the reset transistor ST1 of the second sensor SX12 is turned on, the second sensing node SN2 may be initialized with the reset voltage VRST.

[0196] In an embodiment, after the first and second sensing nodes SN1 and SN2 are initialized with the reset voltage VRST, when the switch signal SW1 turns to a high level, the connection transistor CT11 is turned on. Therefore, the first sensing node SN1 of the first sensor SX11 and the second sensing node SN2 of the second sensor SX12 may be electrically connected.

[0197] The first sensor SX11 and the second sensor SX12 are exposed to light during the light exposure period LE. When the user's hand touches the display surface, the first light sensing element OPD1 and the second light sensing element OPD2 may generate photoelectrons corresponding to the light reflected by the user's hand, and the generated photoelectrons may be accumulated at the first sensing node SN1 and the second sensing node SN2.

[0198] In this case, since the light sensing anode O_AE1 of the first light sensing element OPD1 in the first sensor SX11 and the light sensing anode O_AE2 of the second light sensing element OPD2 in the second sensor SX12 are electrically connected by the connecting transistor CT11 having a conductive state, the amount of current flowing through the first light sensing element OPD1 and the second light sensing element OPD2 can be increased.

[0199] The amplifier transistor ST2 of the first sensor SX11 generates a source-drain current proportional to the amount of photoelectrons (or charges) of the first sensing node SN1 input to the gate electrode of the amplifier transistor ST2. The amplifier transistor ST2 of the second sensor SX12 generates a source-drain current proportional to the amount of photoelectrons (or charges) of the second sensing node SN2 input to the gate electrode of the amplifier transistor ST2.

[0200] When the scan signal GW1 is turned to an active level (ie, a low level), the output transistor ST3 of each of the first sensor SX1 and the second sensor SX2 is turned on.

[0201] When the output transistor ST3 of the first sensor SX11 is turned on, the first sensing signal FS1 corresponding to the current flowing through the amplifying transistor ST2 may be output to the first readout line RL1 .

[0202] When the output transistor ST3 of the second sensor SX12 is turned on, the second sensing signal FS2 corresponding to the current flowing through the amplifying transistor ST2 may be output to the second readout line RL2 .

[0203] That is, first and second sensing signals FS1 and FS2 corresponding to the amount of light sensed by the first and second light sensing elements OPD1 and OPD2 of the first and second sensors SX1 and SX2 may be output to the first and second readout lines RL1 and RL2 , respectively.

[0204] When the amount of current flowing through the first and second light sensing elements OPD1 and OPD2 increases, the signal-to-noise ratio characteristics of the first and second sensing signals FS1 and FS2 provided to the readout circuit 600 may be improved.

[0205] Fig.12 is a diagram illustrating a connection relationship among first, second and third sensors SX11, SX12 and SX13, a first connection transistor CT21 and a second connection transistor CT22 according to an embodiment.

[0206] Reference Fig.12 Each of the first sensor SX11 and the second sensor SX12 can be connected with Fig.10 The first sensor SX11 and the second sensor SX12 illustrated in FIG. 1 include the same circuit configuration. For ease of description, some of the components of the first sensor SX11 and the second sensor SX12 are labeled with reference numerals as Fig.10 The reference numerals of the sensors SX illustrated in the figure are the same, and thus additional description will be omitted to avoid redundancy. The third sensor SX13 includes a third light sensing element OPD3 and a sensor driving circuit SDC. A third sensing signal FS3 corresponding to the amount of light sensed by the third light sensing element OPD3 may be output to a third readout line RL3. The sensor driving circuit SDC of the third sensor SX13 may include the same circuit configuration as the sensor driving circuit SDC of the first sensor SX11.

[0207] The first connection transistor CT21 is connected between the light sensing anode O_AE1 of the first light sensing element OPD1 in the first sensor SX11 and the light sensing anode O_AE2 of the second light sensing element OPD2 in the second sensor SX12. That is, the first connection transistor CT21 is connected between the first sensing node SN1 in the first sensor SX11 and the second sensing node SN2 in the second sensor SX12. The gate electrode of the connection transistor CT21 is connected to the switch line SWL1.

[0208] The second connection transistor CT22 is connected between the light sensing anode O_AE2 of the second light sensing element OPD2 in the second sensor SX12 and the light sensing anode O_AE3 of the third light sensing element OPD3 in the third sensor SX13. That is, the second connection transistor CT22 is connected between the second sensing node SN2 in the second sensor SX12 and the third sensing node SN3 in the third sensor SX13. The gate electrode of the second connection transistor CT22 is connected to the switch line SWL1.

[0209] In an embodiment, the first connection transistor CT21 and the second connection transistor CT22 may be the same N-type transistor as the reset transistor ST1 of each of the first sensor SX11, the second sensor SX12, and the third sensor SX13. However, the present disclosure is not limited thereto.

[0210] When the switch signal SW1 transmitted through the switch line SWL1 is at an effective level (e.g., a high level), the first connection transistor CT21 may electrically connect the first sensing node SN1 in the first sensor SX11 and the second sensing node SN2 in the second sensor SX12. When the switch signal SW1 transmitted through the switch line SWL1 is at an effective level (e.g., a high level), the second connection transistor CT22 may electrically connect the second sensing node SN2 in the second sensor SX12 and the third sensing node SN3 in the third sensor SX13. The driving controller 100 turns on the second connection transistor CT22 when determining that the signal-to-noise ratio of the readout signal RS is less than the threshold value, and otherwise turns off the second connection transistor CT22.

[0211] When the signal-to-noise ratio of the sensing signal obtained from the sensor is not good (or weak), the display device having the above configuration electrically connects at least two sensors, and can improve the signal-to-noise ratio characteristics of the sensing signal obtained from the electrically connected sensors.

[0212] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A display device, comprising: Pixels, including light emitting elements; A first sensor including a first light sensing element connected to a first sensing node; a second sensor including a second light sensing element connected to a second sensing node; as well as The first connection transistor is configured to electrically connect the first sensing node of the first sensor and the second sensing node of the second sensor in response to a switching signal.

2. The display device according to claim 1, wherein: The first light sensing element includes a first light sensing anode connected to the first sensing node and a first cathode connected to a driving voltage line, and The second light sensing element includes a second light sensing anode connected to the second sensing node and a second cathode connected to the driving voltage line.

3. The display device according to claim 1, wherein: The first sensor comprises: A first transistor connected between a reset voltage line and the first sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the first sensing node; and a third transistor connected between the intermediate node and the first readout line and including a gate electrode connected to the scan line, wherein the first transistor and the first connecting transistor are transistors of a first type, and The second transistor and the third transistor are transistors of a second type different from the first type.

4. The display device according to claim 1, wherein: The second sensor comprises: A first transistor connected between a reset voltage line and the second sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the second sensing node; and a third transistor connected between the intermediate node and the second readout line and including a gate electrode connected to the scan line, wherein the first transistor and the first connecting transistor are transistors of a first type, and The second transistor and the third transistor are transistors of a second type different from the first type.

5. The display device according to any one of claims 1 to 4, further comprising: a third sensor including a third light sensing element connected to a third sensing node; as well as The second connection transistor is configured to electrically connect the second sensing node of the second sensor and the third sensing node of the third sensor in response to the switching signal.

6. A display device, comprising: Display panel; a readout circuit configured to receive a first sensing signal and a second sensing signal from the display panel to output a readout signal; as well as a driving controller configured to enable an image to be displayed on the display panel, The display panel includes: a pixel including a light-emitting element; a first sensor including a first light sensing element connected to a first sensing node and configured to output the first sensing signal; a second sensor including a second light sensing element connected to a second sensing node and configured to output the second sensing signal; and a first connecting transistor electrically connecting the first sensing node of the first sensor and the second sensing node of the second sensor, wherein the driving controller turns on the first connecting transistor when determining that the signal-to-noise ratio of the readout signal is less than a threshold value, and otherwise turns off the first connecting transistor.

7. The display device according to claim 6, wherein: The first sensor comprises: A first transistor connected between a reset voltage line and the first sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the first sensing node; and a third transistor connected between the intermediate node and the first readout line and including a gate electrode connected to the scan line, Wherein, the first readout line outputs the first sensing signal, wherein the first transistor and the first connecting transistor are transistors of a first type, and The second transistor and the third transistor are transistors of a second type different from the first type.

8. The display device according to claim 6, wherein: The second sensor comprises: A first transistor connected between a reset voltage line and the second sensing node; a second transistor connected between the sensor driving voltage line and the intermediate node and including a gate electrode connected to the second sensing node; and a third transistor connected between the intermediate node and the second readout line and including a gate electrode connected to the scan line, Wherein, the second readout line outputs the second sensing signal, wherein the first transistor and the first connecting transistor are transistors of a first type, and The second transistor and the third transistor are transistors of a second type different from the first type.

9. The display device according to any one of claims 6 to 8, wherein: The display panel further comprises: a third sensor including a third light sensing element connected to a third sensing node and configured to output a third sensing signal; and a second connecting transistor electrically connecting the second sensing node of the second sensor and the third sensing node of the third sensor, The driving controller turns on the second connection transistor when determining that the signal-to-noise ratio of the readout signal is less than the threshold value, and turns off the second connection transistor otherwise.

10. A display device, comprising: basal layer; A circuit layer, disposed on the base layer; as well as an element layer, disposed on the circuit layer and comprising a light emitting element, a first light sensing element and a second light sensing element, The circuit layer includes: a first connecting transistor connected to the first light sensing element and a first sensing node, connected to the second light sensing element and a second sensing node, and configured to electrically connect the first sensing node and the second sensing node in response to a switching signal.

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