Current sampling circuit

Abstract

The utility model discloses a current sampling circuit, which comprises a direct-current power supply, a parallel resonance circuit, a linkage circuit, a rectifying circuit, a filter circuit, a driving end, a voltage output end and a sampling end, according to the utility model, the parasitic resistance when the first N-channel MOS tube is conducted is used for sampling, and the resistance value of the circuit is not additionally increased, so that the circuit is optimized, and the loss of the circuit and the heat generated when the circuit works are reduced; the current sampling circuit is applied to circuits needing an LC resonance circuit, such as wireless power supply, wireless charging, metal induction heating, metal detection, an LC booster circuit and the like, has great advantages, can increase the efficiency and the power of the circuit, and reduces the heat of the circuit during working.

Description

Technical Field

[0001] The utility model relates to the technical field of sampling circuits, and particularly relates to a current sampling circuit. Background Art

[0002] With the rapid development of the intelligence of electronic technology, the requirements of electronic products for self-perception ability are gradually increasing. A large number of products need to continuously monitor their working currents. Especially when LC parallel resonance is used in a circuit, the current state of the parallel resonance is closely related to the safety of the product. In a conventional current sampling circuit, a current-limiting resistor is usually connected in series in the path of the power supply ground, and the working current is sampled by using Ohm's law to extract the voltage signal at the front end of the resistor. Such a conventional method will increase the overall impedance of the circuit, reduce the efficiency and power of the circuit at the same time. When a large current flows through the resistor, a large amount of heat will also be generated in the resistor, increasing the difficulty of heat dissipation of the product. And when driving the LC circuit, the transient current is extremely large. At this time, if a current-limiting resistor is connected in series in the path to the ground, the intensity of the transient current will be weakened, thus interfering with the normal operation of the entire circuit system or suppressing the effective power output of the entire system. Summary of the Utility Model

[0003] In view of this, the main purpose of the utility model is to provide a current sampling circuit.

[0004] To achieve the above purpose, the technical solution of the utility model is realized as follows:

[0005] An embodiment of the utility model provides a current sampling circuit, including a DC power supply, a parallel resonance circuit, a linkage circuit, a rectification circuit, a filtering circuit, a driving end, a voltage output end, and a sampling end;

[0006] The DC power supply is connected to the first end of the parallel resonance circuit for providing direct current;

[0007] The first end of the linkage circuit is respectively connected to the second end of the parallel resonance circuit, the first end of the rectification circuit, and the sampling end, and the second end of the linkage circuit is connected to the driving end;

[0008] The filtering circuit and the rectification circuit are connected in parallel and then connected to the voltage output end.

[0009] In the above solution, the parallel resonance circuit includes a first capacitor and a first inductor, and the first end of the first capacitor is respectively connected to the DC power supply and the first end of the first inductor.

[0010] In the above solution, the linkage circuit includes a first N-channel MOS transistor and a second N-channel MOS transistor. The drain of the first N-channel MOS transistor is connected to the drain of the second N-channel MOS transistor, the second terminal of the first capacitor, the second terminal of the first inductor, and the sampling terminal respectively. The gate of the second N-channel MOS transistor is connected to the gate of the first N-channel MOS transistor and the driving terminal respectively.

[0011] In the above solution, the rectifying circuit includes a first resistor and a diode. The positive electrode of the diode is connected to the source of the second N-channel MOS transistor. The negative electrode of the diode is connected to the first end of the first resistor. The second end of the first resistor is connected to the voltage output terminal.

[0012] In the above solution, the filtering circuit includes a second resistor and a third capacitor. The first end of the second resistor is connected to the first end of the third capacitor and the second end of the first resistor respectively. The second end of the second resistor is connected to the second end of the third capacitor and the source of the first N-channel MOS transistor respectively and then grounded.

[0013] In the above solution, the driving terminal can input a rectangular wave, a sawtooth wave, a sine wave or a PWM modulation wave.

[0014] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0015] The present utility model utilizes the parasitic resistance when the first N-channel MOS transistor is turned on for sampling. The circuit does not additionally increase the resistance value, so as to optimize the circuit, reduce the loss of the circuit and the heat generated during the operation of the circuit. This current sampling circuit is applied to circuits such as wireless power supply, wireless charging, metal induction heating, metal detection, and LC boost circuits that require the use of LC resonance circuits, and has great advantages. It can increase its efficiency and power, and reduce the heat generated during its operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to disclose a further understanding of the present utility model, and constitute a part of the present utility model. The schematic embodiments of the present utility model and their descriptions are used to explain the present utility model and do not constitute an improper limitation to the present utility model. In the drawings:

[0017] Figure 1 It is a schematic structural diagram of a current sampling circuit according to an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to make the objectives, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0019] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components; in the description of the present utility model, it should be understood that terms such as "first", "second", "third", etc. are only for facilitating the distinction and description of the same components, rather than indicating or implying the number of the components referred to, and should not be construed as a limitation of this patent. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0020] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, article or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of another identical element in the process, article or device including the element.

[0021] Embodiment 1 of the present utility model provides a current sampling circuit, as Figure 1 shown, including a DC power supply VDD, a parallel resonance circuit, a linkage circuit, a rectification circuit, a filtering circuit, a driving end IN, a voltage output end OUT, and a sampling end TEST;

[0022] The DC power supply is connected to the first end of the parallel resonance circuit for providing direct current;

[0023] The first end of the linkage circuit is respectively connected to the second end of the parallel resonance circuit, the first end of the rectification circuit, and the sampling end TEST, and the second end of the linkage circuit is connected to the driving end IN;

[0024] The filtering circuit and the rectification circuit are connected in parallel to the voltage output end OUT.

[0025] In the above solution, the parallel resonance circuit includes a first capacitor C1 and a first inductor L1, and the first end of the first capacitor C1 is respectively connected to the DC power supply VDD and the first end of the first inductor L1.

[0026] In the above solution, the linkage circuit includes a first N-channel MOS transistor M1 and a second N-channel MOS transistor M2. The drain of the first N-channel MOS transistor M1 is respectively connected to the drain of the second N-channel MOS transistor M2, the second end of the first capacitor C1, the second end of the first inductor L1, and the sampling end TEST. The gate of the second N-channel MOS transistor M2 is respectively connected to the gate of the first N-channel MOS transistor M1 and the driving end IN.

[0027] In the above solution, the rectifying circuit includes a first resistor R1 and a diode D1. The positive electrode of the diode D1 is connected to the source electrode of the second N-channel MOS transistor M2. The negative electrode of the diode D1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the voltage output terminal OUT.

[0028] In the above solution, the filtering circuit includes a second resistor R2 and a third capacitor C3. The first end of the second resistor R2 is respectively connected to the first end of the third capacitor C3 and the second end of the first resistor R1. The second end of the second resistor R2 is respectively connected to the second end of the third capacitor C3 and the source electrode of the first N-channel MOS transistor M1 and then grounded.

[0029] In the above solution, the driving terminal IN can input a rectangular wave, a sawtooth wave, a sine wave or a PWM modulation wave.

[0030] Embodiment II of the present invention provides a sampling method for the above current sampling circuit, including the following steps:

[0031] S1: Provide an alternating operating frequency signal to the driving terminal IN of the circuit to drive the circuit to operate;

[0032] S2: By simultaneously instantaneously turning off the first N-channel MOS transistor M1 and the second N-channel MOS transistor M2, the high voltage generated by the resonance of the first capacitor C1 and the first inductor L1 is blocked at the preset sampling terminal TEST;

[0033] S3: Simultaneously instantaneously turn on the first N-channel MOS transistor M1 and the second N-channel MOS transistor M2, so that a large current flowing through the first N-channel MOS transistor M1 during operation, and the voltage signal generated by the internal resistance of the first N-channel MOS transistor M1 passes through the second N-channel MOS transistor M2;

[0034] S4: Process the voltage signal passing through the second N-channel MOS transistor M2 in step S3 through a rectifying circuit and a filtering circuit, and generate a DC voltage signal at the voltage output terminal OUT, where the change of the DC voltage signal is proportional to the current flowing through the first N-channel MOS transistor M1, thereby realizing current sampling.

[0035] The working principle of the present invention is as follows:

[0036] Such as Figure 1As shown, the utility model uses the parasitic resistance generated when the first N-channel MOS transistor M1 is turned on as the basis for current sampling. In the LC resonance circuit, when the first N-channel MOS transistor M1 is instantaneously turned off, a high voltage will be generated at the sampling terminal TEST due to LC resonance. However, when the first N-channel MOS transistor M1 is turned on, the voltage at the sampling terminal TEST will be pulled down by the first N-channel MOS transistor M1 to charge the first inductor L1. However, when the first N-channel MOS transistor M1 conducts current, due to the natural parasitic resistance of the first N-channel MOS transistor M1, according to Ohm's law, a real-time voltage signal generated by the current can be collected at the sampling terminal TEST. The drive pins of the first N-channel MOS transistor M1 and the second N-channel MOS transistor M2 are directly connected, so that the on and off states of the first N-channel MOS transistor M1 and the second N-channel MOS transistor M2 can be synchronized. Therefore, the second N-channel MOS transistor M2 can be turned off synchronously when the first N-channel MOS transistor M1 is turned off to shield the high-voltage signal at the sampling terminal TEST, and only when the first N-channel MOS transistor M1 is turned on, the second N-channel MOS transistor M2 is turned on synchronously to collect the voltage signal at the sampling terminal TEST. The voltage collected in this way is used to judge the working current of the current circuit.

[0037] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A current sampling circuit, characterized in that: It includes a DC power supply, a parallel resonant circuit, a linkage circuit, a rectifier circuit, a filter circuit, a driving end, a voltage output end, and a sampling end; The DC power supply is connected to the first end of the parallel resonant circuit and is used to provide DC power; The first end of the linkage circuit is connected to the second end of the parallel resonant circuit and the first end and the sampling end of the rectifier circuit respectively, and the second end of the linkage circuit is connected to the driving end; The filter circuit and the rectifier circuit are connected in parallel to the voltage output terminal.

2. A current sampling circuit according to claim 1, characterized in that: The parallel resonant circuit includes a first capacitor and a first inductor, wherein a first end of the first capacitor is connected to a DC power supply and a first end of the first inductor respectively.

3. A current sampling circuit according to claim 2, characterized in that: The linkage circuit includes a first N-channel MOS transistor and a second N-channel MOS transistor, the drain of the first N-channel MOS transistor is respectively connected to the drain of the second N-channel MOS transistor, the second end of the first capacitor, the second end of the first inductor and the sampling end, and the gate of the second N-channel MOS transistor is respectively connected to the gate of the first N-channel MOS transistor and the driving end.

4. A current sampling circuit according to claim 3, characterized in that: The rectifier circuit includes a first resistor and a diode, wherein the anode of the diode is connected to the source of the second N-channel MOS tube, the cathode of the diode is connected to the first end of the first resistor, and the second end of the first resistor is connected to the voltage output end.

5. The current sampling circuit according to claim 4, characterized in that: The filtering circuit includes a second resistor and a third capacitor, wherein the first end of the second resistor is respectively connected to the first end of the third capacitor and the second end of the first resistor, and the second end of the second resistor is respectively connected to the second end of the third capacitor and the source of the first N-channel MOS tube and then grounded.

6. The current sampling circuit according to claim 5, characterized in that: The driving end can input a rectangular wave, a sawtooth wave, a sine wave or a PWM modulation wave.

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