In-memory computing device

Abstract

The utility model relates to an in-memory computing device. An in-memory computing device includes word line activation circuits that receive an input signal indicative of a plurality of input values and provide activation signals that each vary as the input values vary. The in-memory computing device also includes a memory array, a bias circuit that generates a bias voltage, and a digital detector. The memory array has memory cells coupled to bit lines and each coupled to word lines. Each memory cell stores a calculation weight. In response to the activation signal, a cell current that varies as the bias voltage, the activation signal, and the computational weight varies flows through each of the memory cells. A bit line current that varies as the sum of the cell currents varies flows through the bit line. A digital detector is coupled to the bit line, samples the bit line current, and in response provides an output signal.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of Italian Patent Application No. 102022000026760, filed on December 23, 2022, the content of which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical Field

[0003] The present utility model relates to a memory-in-compute device with improved drift compensation. Background Art

[0004] It is well known that memory-in-compute devices use a specific arrangement of memory cells in a memory array to perform analog data processing at the unit level.

[0005] For example, memory-in-compute devices are used to perform multiply-accumulate (MAC) operations, such as using MAC operations to implement machine learning algorithms such as neural networks.

[0006] The multiply-accumulate operation provides output vectors y 1 , …, y M , as input vectors x 1 , …, x N multiplied by a vector or matrix of computational weights g ij , for example:

[0007] That is:

[0008]

[0009] The memory-in-compute device stores the computational weights g ij in the cells of the memory and performs multiply and sum (accumulate) operations at the unit level.

[0010] Specifically, for each output vector y i , known memory-in devices generate a current indicative of the corresponding MAC operation, i.e., and include a read circuit having a corresponding analog-to-digital converter (ADC) that discretizes the current.

[0011] Memory-in-compute devices make it possible to avoid transferring data back and forth between the memory and the elaboration circuit. Therefore, the performance of memory-in-compute devices is not limited by the data transfer bandwidth between the memory and the elaboration circuit and has low power consumption.

[0012] However, it is noted that in known in-memory computing devices, the current indicating a MAC operation is subject to errors such as due to the time drift of the computed values stored in the memory cells. Therefore, known in-memory computing devices have low computing accuracy.

[0013] There is a need to overcome the disadvantages of the prior art. SUMMARY OF THE UTILITY MODEL

[0014] According to one aspect of the present utility model, an in-memory computing device is disclosed, characterized in that the in-memory computing device comprises: a word line activation circuit configured to receive an input signal indicating a plurality of input values and provide a plurality of activation signals, wherein each activation signal varies with the change of the corresponding input value; a bias circuit configured to provide a bias voltage in response to a reference current; a memory array comprising a plurality of memory cells coupled to bit lines and each coupled to a corresponding word line, wherein the bit lines are configured to receive the bias voltage, wherein each memory cell comprises a storage element for storing a corresponding computed weight and a selection element for receiving a corresponding activation signal from the corresponding word line, wherein a corresponding cell current flowing through each memory cell is generated by the storage element and the selection element based on the bias voltage, the corresponding activation signal and the corresponding computed weight, and wherein a bit line current flowing through the bit line varies with the change of the sum of the cell currents of the memory cells coupled to the bit line; and a digital detector coupled to the bit line and configured to sample the bit line current and, in response, provide at least one output signal.

[0015] According to at least one embodiment of the present utility model, the bias circuit comprises a reference network having a variable reference impedance through which the reference current flows, wherein the bias voltage varies with the change of the reference current and the variable reference impedance.

[0016] According to at least one embodiment of the present utility model, the reference network comprises a reference memory array configured to have a reference transconductance value, wherein the variable reference impedance varies with the change of the reference transconductance value, and the reference memory array represents a statistically significant sample of the memory array.

[0017] According to at least one embodiment of the present utility model, each of the activation signals is a pulse signal, and the duration of the pulse signal is a proportional function of the corresponding input value.

[0018] According to at least one embodiment of the present utility model, the word line activation circuit includes a timer configured to provide a timer signal, and a plurality of input time converters configured to compare the timer signal with a corresponding input value and provide a corresponding activation signal in response.

[0019] According to at least one embodiment of the present utility model, the timer is configured to provide the timer signal in response to an oscillator current, wherein the timer is configured to update the timer signal at an update frequency that varies with the change of the oscillator current.

[0020] According to at least one embodiment of the present utility model, the timer is configured to generate the oscillator current according to the reference current.

[0021] According to at least one embodiment of the present utility model, the in-memory computing device is further configured to receive an external signal from a user, wherein the oscillator current varies with the change of the external signal.

[0022] According to at least one embodiment of the present utility model, the timer includes an integration stage and a counter stage, and is configured to perform a plurality of consecutive timing iterations, wherein in each timing iteration: the integration stage is configured to generate a corresponding integration signal indicating the time integral of the oscillator current, compare the integration signal with an oscillator threshold, and reset the integration signal in response to the integration signal reaching the oscillator threshold; and the counter stage is configured to update the timer signal in response to the integration signal reaching the oscillator threshold.

[0023] According to at least one embodiment of the present utility model, the word line activation circuit is configured to compare the timer signal with a maximum count signal and, in response, provide an end calculation signal, wherein the digital detector is configured to receive the end calculation signal and stop sampling the bit line current in response to receiving the end calculation signal.

[0024] According to at least one embodiment of the present utility model, the digital detector includes an integration stage and a counter stage, and is configured to perform a plurality of consecutive sampling iterations, wherein in each sampling iteration: the integration stage is configured to generate an integration signal indicating the time integral of the bit line current, compare the integration signal with a sampling threshold, and reset the integration signal in response to the integration signal reaching the sampling threshold; and the counter stage is configured to update the output signal in response to the integration signal reaching the sampling threshold.

[0025] According to at least one embodiment of the present utility model, the integration stage of the digital detector has the same circuit diagram as the integration stage of the timer.

[0026] According to at least one embodiment of the present invention, the integration stage includes a first inverter having an output terminal for providing the integration signal and an integration capacitor element coupled to the output terminal of the first inverter, wherein the first inverter is configured to receive a bias current indicative of the bit line current.

[0027] According to at least one embodiment of the present invention, the first inverter has an input terminal configured to receive a control signal indicative of the integration signal reaching the sampling threshold, and wherein the first inverter is configured to charge or discharge the integration capacitor element with the bias current as the control signal changes.

[0028] According to at least one embodiment of the present invention, the integration stage includes a first operational amplifier having a first input terminal and an output terminal and an integration capacitor element coupled between the first input terminal and the output terminal of the first operational amplifier, and wherein the first operational amplifier is configured to receive a current indicative of the bit line current at the first input terminal.

[0029] According to at least one embodiment of the present invention, the integration stage includes a second inverter having a switching threshold and receiving the integration signal, wherein the sampling threshold is the switching threshold of the second inverter.

[0030] According to at least one embodiment of the present invention, the integration stage includes a second operational amplifier having a first input terminal and a second input terminal, and wherein the second operational amplifier is configured to receive the integration signal at the first input terminal and receive the sampling threshold at the second input terminal.

[0031] According to at least one embodiment of the present invention, the integration signal is a first integration signal and the sampling threshold is a first sampling threshold. The integration stage includes a first integration circuit configured to generate the first integration signal, compare the first integration signal with the first sampling threshold, and reset the first integration signal. The integration stage further includes a second integration circuit and a switching circuit coupled between the first integration circuit and the second integration circuit. Wherein, the second integration circuit is configured to generate a second integration signal indicating the time integration of the bit line current, compare the second integration signal with a second sampling threshold, and reset the second integration signal in response to the second integration signal reaching the second sampling threshold. Wherein, the counter stage is configured to further update the output signal in response to the second integration signal reaching the second sampling threshold. Wherein, the switching circuit is configured to disable the first integration circuit and enable the second integration circuit in response to the first integration signal reaching the first sampling threshold, and enable the first integration circuit and disable the second integration circuit in response to the second integration signal reaching the second sampling threshold.

[0032] According to at least one embodiment of the present invention, each of the memory cells has a current path including the storage element and the selection element and extending between a common node and a reference potential node. Wherein, the selection element is configured to selectively close the corresponding current path as the corresponding activation signal changes.

[0033] According to at least one embodiment of the present invention, the memory cells are non-volatile memory cells.

[0034] According to the present invention, a memory-in-computation device and a control method thereof are provided.

[0035] In an embodiment, an in-memory computing device is configured to receive an input signal indicative of a plurality of input values and provide at least one output signal. The in-memory computing device includes: a word line activation circuit configured to receive the input signal and provide a plurality of activation signals, each activation signal varying with a corresponding input value; a bias circuit configured to provide a bias voltage in response to a reference current; a memory array including a plurality of memory cells coupled to bit lines and each coupled to a corresponding word line, the bit lines being configured to receive the bias voltage, the memory cells being configured to each store a corresponding computing weight and each receive a corresponding activation signal from the corresponding word line, the memory cells being configured to each conduct a corresponding cell current that varies with the bias voltage, the corresponding activation signal, and the corresponding computing weight, the bit lines being configured to conduct a bit line current that is the sum of the cell currents; and a digital detector coupled to the bit lines, configured to sample the bit line current and, in response, provide the at least one output signal.

[0036] In an embodiment, a method is provided for controlling an in-memory computing device configured to receive an input signal indicative of a plurality of input values and provide at least one output signal. The in-memory computing device includes a word line activation circuit, a bias circuit, a memory array, and a digital detector, the memory array including a plurality of memory cells coupled to bit lines and each coupled to a corresponding word line, the memory cells being configured to each store a corresponding computing weight and each receive a corresponding activation signal from the corresponding word line, the memory cells being configured to each conduct a corresponding cell current that varies with a bias voltage, the corresponding activation signal, and the corresponding computing weight, the bit lines being configured to conduct a bit line current that is the sum of the cell currents. The method includes: providing, via the word line activation circuit, a plurality of activation signals to the memory cells, each activation signal varying with a corresponding input value; generating a bias voltage based on a reference current and applying the bias voltage to the bit lines; and sampling, by the digital detector, the bit line current and, in response, providing the at least one output signal. Description of the Drawings

[0037] To better understand the present invention, non-limiting embodiments are now described with reference to the drawings, in which:

[0038] Figure 1 A block diagram of the in-memory computing device is shown;

[0039] Figure 2 shows Figure 1 a current diagram of the line activation circuit of the in-memory computing device of

[0040] Figure 3 Shows Figure 2 a detailed circuit diagram of a part of the line activation circuit of;

[0041] Figure 4 Shows an example of an activation signal provided by a part of Figure 3 of;

[0042] Figure 5 Shows the circuit diagram of the digital detector of the computing device within this memory;

[0043] Figure 6 Shows Figure 5 a detailed circuit diagram of a part of the digital detector of;

[0044] Figure 7 Shows the exemplary waveform of the digital detector of Figure 5 in use;

[0045] Figure 8 Shows Figure 2 the circuit diagram of the timer of the line activation circuit of;

[0046] Figure 9 Shows Figure 8 a detailed circuit diagram of a part of the timer of;

[0047] Figure 10 Shows the circuit diagram of the digital detector of the computing device within this memory;

[0048] Figure 11 Shows the waveform example of the digital detector of Figure 10 in use; and

[0049] Figure 12 Shows the circuit diagram of the digital detector of the computing device within this memory. Detailed Description

[0050] Figure 1 Shows a computing device 10 within a memory (also hereinafter referred to as the IMC device 10), which includes a computing memory array (hereinafter indicated as the memory array) 12, a line activation circuit 14, a plurality of digital detectors 16, and a bias circuit 18.

[0051] The memory array 12 is of the non-volatile type and includes a plurality of memory cells 20 organized in a matrix arrangement having M columns and N rows.

[0052] The memory cells 20 arranged in the same column are interconnected through corresponding bit lines BL i where i = 1,..., M. The memory cells 20 arranged in the same row are interconnected through corresponding word lines WL jare interconnected, where j = 1, …, N.

[0053] In fact, the corresponding word lines WL j and the corresponding bit lines BL i are associated with each memory cell 20.

[0054] The memory cells 20 are programmed to respectively store the corresponding computed weights g ij , which can be used as weights for performing in-memory computations such as multiply-accumulate (MAC) operations.

[0055] The line activation circuit 14 provides a plurality of word line activation signals 21, one for each word line WL j , which are configured to respectively activate the memory cells 20 of the corresponding word line WL j , as discussed in further detail below.

[0056] The line activation circuit 14 receives an input vector X, which includes a plurality of input values x 1 , …, x N , one for each word line WL j .

[0057] The word line activation signals 21 are pulses each having a time width that varies with the corresponding input value x j , and are specifically rectangular pulses here.

[0058] The bias circuit 18 generates a bias voltage Vr from a reference current I REF and supplies the bias voltage Vr to the bit lines BL 1 , …, BL M , as discussed in further detail below.

[0059] In this embodiment, the bias circuit 18 supplies the same voltage Vr to all the bit lines BL 1 , …, BL M . However, the bias circuit 18 can supply different bias voltages to the bit lines BL 1 , …, BL M in response to the bias voltage Vr according to a specific application.

[0060] The digital detector 16 is an analog-to-digital converter (ADC) that is respectively coupled to the corresponding bit lines BL i and respectively provides an output signal y i by sampling the current I BL,i flowing through the corresponding bit line BL i .

[0061] The memory cells 20 each include a storage element 25 and a selection element 26.

[0062] The storage element 25 of each memory cell 20 is a variable resistor element, specifically based here on a phase change material (PCM), such as a chalcogenide.

[0063] Specifically, the calculated weight g ij Indicates the transconductance value of the storage element 25 of the corresponding memory cell 20, i.e., it indicates the programmed resistance of the storage element 25.

[0064] The phase change material has at least two phase states, e.g., an amorphous phase and a crystalline phase, each having a corresponding resistance.

[0065] The phase change material can be transformed from one phase state to another by means of heat transfer (e.g., by using current pulses).

[0066] The resistance of each storage element 25 associated with the corresponding phase state is used to distinguish between two or more logic states of the corresponding memory cell 20.

[0067] For example, the amorphous phase can have a higher resistance than the crystalline phase. The logic state "0" or the reset state can be associated with the amorphous phase of the storage element 25. The logic state "1" or the set state can be associated with the crystalline phase of the storage element 25.

[0068] The storage element 25 has a first terminal coupled to a node 28 of the corresponding bit line BL i and a second terminal coupled to a reference potential node (here the ground 29) through a selection element 26.

[0069] The selection element 26 is a switch, e.g., a BJT transistor, a diode, or a MOS transistor (here an NMOS transistor), which is arranged in series with the corresponding storage element 25, and whose switching is controlled by a word line activation signal 21 of the corresponding word line WL j The word line activation signal 21 controls the word line activation signal 21.

[0070] In this embodiment, the NMOS transistor forming the selection element 26 has a source coupled to the ground 29 (here directly connected); a drain coupled to the second terminal of the storage element 25 (here directly connected); and a gate coupled to the corresponding word line WL j coupled (here directly connected).

[0071] In fact, the storage element 25 and the selection element 26 form the current path of the corresponding memory cell 20; the selection element 26 closes the corresponding current path in response to receiving the corresponding activation signal 21, thereby enabling the cell current i cell to flow from the common node 28 to the ground 29.

[0072] The IMC device 10 can also include being coupled to the bit line BL 1 ..., BL MThe interface circuit 30 can be used, for example, to program the transconductance value g stored in the storage element 25 in a manner known per se. ij For programming.

[0073] Specifically, the bias circuit 18 includes a current source 32 that generates a reference current I REF and a reference network 33 having an input node 34 and a reference impedance Z REF .

[0074] In this embodiment, the current source 32 is a controllable current source that receives an external signal EXT, for example, from a user of the IMC device 10, and the external signal EXT indicates the desired value of the reference current I REF .

[0075] The reference network 33 receives the reference current I REF at the input node 34. The voltage at the input node 34 varies with the reference current I REF and the reference impedance Z REF .

[0076] The bias circuit 18 further includes a voltage divider circuit, which is formed here by an operational amplifier 36 having an output terminal 37 that provides a bias voltage Vr.

[0077] The operational amplifier 36 has a non-inverting input terminal coupled to the input node 34 of the reference network 33. The operational amplifier 36 has an inverting input terminal coupled (specifically, directly coupled here) to the output terminal 37 of the operational amplifier 36.

[0078] The output terminal 37 of the amplifier 36 is coupled to the bit lines BL 1 ,..., BL M according to a specific application, for example, directly or through a specific voltage divider circuit.

[0079] In fact, in this embodiment, the voltage at the input node 34 of the reference network 33 forms the bias voltage Vr.

[0080] Specifically, in this embodiment, the reference network 33 is formed by a reference memory array, and thus the reference memory array is also denoted by 33 hereinafter. The reference memory array has a total reference transconductance value g ref and includes one or more reference cells of a non-volatile type, which are a plurality of reference cells 40 here.

[0081] The reference memory array 33 can be part of the memory array 12 or can be a separate memory array.

[0082] The reference cell 40 has the same circuit configuration as the memory cell 20 of the memory array 12.

[0083] Specifically, each of the reference cells 40 includes a storage element 41 and a selection element 42, which are particularly equivalent to the storage element 25 and the selection element 26 of the memory cell 20 respectively.

[0084] In fact, the storage element 41 is based on the same technology used to obtain the storage element 25. For example, if the storage element 25 is based on a PCM material, the storage element 41 is also based on a PCM material, specifically the same PCM material.

[0085] The reference cells 40 are programmed to store corresponding reference transconductance values, which may be equal to or different from each other depending on the specific application.

[0086] The number of reference cells 40 and the corresponding reference transconductance values can be selected during the design phase such that the reference memory array 33 is a statistically significant sample of the memory array 12.

[0087] In fact, the total reference transconductance value g of the reference memory array 33 ref statistically represents the total transconductance of the memory array 12.

[0088] For example, the total transconductance of the memory array 12 can be equal to the transconductance that the memory array 12 would have when all the memory cells 20 are simultaneously activated.

[0089] For example, the number of reference cells 40 can be more than one hundred.

[0090] For example, the reference cells 40 can be programmed such that the total reference transconductance g of the reference memory array 33 ref is equal to the average value of the total transconductance of the memory array 12.

[0091] For example, the average value can represent the average transconductance value determined for the memory array 12 during use (e.g., during the calibration or initialization steps of the IMC device 10).

[0092] The storage element 41 has a first terminal coupled to the input node 34 of the reference network 33 and a second terminal coupled to a reference potential node (here the ground 29) through the selection element 42.

[0093] In fact, all the reference cells 40 share the same reference bit line BL ref .

[0094] Each of the selection elements 42 is formed by a corresponding switch (such as a BJT transistor, a diode, or a MOSFET transistor, here an NMOS transistor) arranged in series with the corresponding storage element 41, and is particularly equivalent to the selection element 26 of the memory cell 20.

[0095] In this embodiment, the selection elements 42 of all reference cells 40 are controlled by the same reference activation signal REF, which can be generated, for example, by the word line activation circuit 14 or by other components of the IMC device 10 not shown here.

[0096] However, during the calculation of the IMC device 10, the selection elements 42 can each be controlled by respective reference activation signals that are different from each other, for example, according to which reference cell 40 it is intended to activate.

[0097] Reference impedance Z ref Changes as the transconductance value g stored by the reference cell 40 ref And the reference activation signal REF change.

[0098] Figure 2 A detailed embodiment of the line activation circuit 14 is shown, which includes a timer 45 that provides a timer signal TM and a plurality of input time converters 46, each word line WL 1 、…、WL N One.

[0099] The plurality of input time converters 46 receive each timer signal TM and a corresponding input value x j And in response, provide corresponding word line activation signals 21.

[0100] The line activation circuit 14 also receives an address signal ADR indicating which word lines WL j To perform in-memory calculations. For example, the address signal ADR can be used to activate only some of the plurality of word lines WL 1 、…、WL N In use, for example, if the number of values of the input vector X is smaller than the number of rows N of the memory array 12.

[0101] Specifically, the timer 45 provides the timer signal TM in response to a supply current (specifically, here in response to a reference current I REF ).

[0102] The timer signal TM is a digital signal with L bits, also indicated as the timer signal TM in the following text and drawings <l:1>, the timer signal increases over time at an update frequency f u The update frequency f u varies with the change in the supply current.

[0103] In fact, the timer signal TM is a counter signal.

[0104] Timer 45 can reset the timer signal TM to an initial value, such as zero, at the start of a new calculation to be performed by the IMC device 10, for example, in response to receiving a start signal from a user of the IMC device 10.

[0105] Reference will be made Figure 8 and Figure 9 to describe embodiments of timer 45 in detail.

[0106] Figure 3 A plurality of word lines WL are shown 1 ,..., WL M and the word line WL j in an embodiment of the input time converter 46. The input time converter 46 includes: a comparator 50 that receives the timer signal TM <l:1>and the corresponding input value x j and provides a matching signal MTC as a response; and a pulse generation circuit, which is formed here by a NAND logic gate 51 and an inverter 52, so as to provide a corresponding word line activation signal 21.

[0107] In this embodiment, the input value x j is also a digital signal. The comparator 50 is a bit check circuit based on, for example, an exclusive OR (XOR) logic gate, and compares the input value x j with the timer signal TM <l:1>, and when the timer signal TM <l:1>becomes equal to the input value x j When this occurs, the match signal MTC is set to a high logic value.

[0108] The NAND logic gate 51 receives the address signal ADR and the match signal MTC indicating whether the word line WL j needs to be activated during the execution of the in-memory computation. If the word line WL j needs to be activated during the in-memory computation, the address signal ADR_EN can have a high logic value.

[0109] The inverter 52 is coupled to the output of the NAND logic gate 51 at the input and provides the word line activation signal 21 at the output. In fact, the inverter 52 operates as a driver circuit for the corresponding word line WL j

[0110] For the word line WL j as long as the timer signal TM <l:1>Different from the input value x j , the input time converter 46 then holds the corresponding word line activation signal 21 at a high logic value (i.e., thereby activating here the selection element 26 of the memory cell 20 coupled to the word line WL j ).

[0111] Therefore, the word line activation signals 21 each have a corresponding activation length T j , and this activation length T j is related to the timer signal TM <l:1>Update frequency f u and the corresponding input value x j are proportional.

[0112] By way of example, Figure 4 the word line activation signal 21 of the first word line WL 1 and the last word line WL N is shown. At the start of the calculation of the IMC device 10 (at time t 0 ), the timer signal TM is reset to its starting value, and the input time converters 46 each switch the corresponding word line activation signal 21 to a high value.

[0113] At Figure 4 the example of, 1 the input value x 1 associated with the first word line WL N is less than the input value x N associated with the last word line WL 1 ; thus, the input time converter 46 associated with the first word line WL N holds the corresponding word line activation signal 21 at a high value for a shorter time relative to the input time converter 46 associated with the last word line WL 1 . This results in the activation length T 1 of the word line activation signal 21 of the first word line WL N being less than the activation length T N of the word line activation signal 21 of the last word line WL

[0114] In use, the IMC device 10 can be used to perform multiply-accumulate (MAC) operations between an input vector X = x 1 , …, x N and a matrix formed by the computational weights g ij .

[0115] In fact, the cell current i cell absorbed by each memory cell 20, here from the corresponding node 28 to ground 29, depends on the transconductance g ij of the corresponding storage element 25 and the activation time T j of the corresponding selection element 26, that is, depends on the pulse length of the corresponding word line activation signal 21.

[0116] Specifically, the absolute value of each cell current i cell depends on the corresponding transconductance value g ij . The duration of each cell current i cell depends on the corresponding activation time T j .

[0117] Accordingly, charge can be associated with each cell current i cell ; the charge varies with the corresponding transconductance value g ij and the corresponding activation time T j .

[0118] Since the pulse length of the word line activation signal 21 varies with the corresponding input value x j , the charge associated with each cell current i cell varies with the product g ij ·x j .

[0119] For each bit line BL i , the corresponding bit line current I BL,i is the sum of the cell currents i cell . Thus, the total charge associated with each bit line current I BL,i varies with the product and accumulation operation g i1 ·x 1 +g i2 ·x 2 +…+g iN ·x N .

[0120] Accordingly, each output signal y BL,i obtained by measuring the corresponding bit line current I BL,i (specifically by integrating the corresponding bit line current I i ) indicates the MAC operation g i1 ·x 1 +g i2 ·x 2 +…+g iN ·x N .

[0121] The bit line currents I BL,1 、…、I BL,M also each depend on the bias voltage Vr received from the bias circuit 18.

[0122] The fact that the bias voltage Vr is generated by the reference current I REF enables the adjustment of the bias voltage Vr by changing the variable impedance reference Z REF and / or the reference current I REF .

[0123] During the lifetime of the IMC device 10, the IMC device 10 may be subject to temperature variations that may affect the transconductance value g ij of the memory cells 20. In addition, the transconductance value g ij may be subject to drift; for example, in the case where the memory cell 20 is a PCM memory cell, the storage element 25 may be subject to aging phenomena such as amorphization.

[0124] Transconductance value g ij This deviation from the programmed value may change the bit line current I BL,i , thereby causing an error in the output signal y i in.

[0125] In the IMC device 10, such a temperature change or drift will also affect the reference transconductance value of the reference memory cell 40 in the same way, and correspondingly, affect the total reference transconductance value g ref of the reference memory array 33, because the reference memory cell 40 represents a statistically significant sample of the memory cell 20.

[0126] A change in the reference transconductance value of the reference memory cell 40 will cause a change in the reference impedance Z REF and thus a change in the voltage at the input node 34 of the reference network 33. Therefore, the bias voltage Vr also changes.

[0127] Specifically, the change in the bias voltage Vr compensates for the change in the transconductance value g ij of the memory cell 20.

[0128] For example, if the memory cell 20 experiences drift that causes the corresponding transconductance value g ij to increase, the corresponding bit line current I BL,i will also increase. At the same time, the total reference transconductance value g ref of the reference memory array 33 will also increase, thereby causing a decrease in the reference impedance Z REF and correspondingly a decrease in the bias voltage Vr.

[0129] The decrease in the bias voltage Vr causes a decrease in the bit line current I BL,i .

[0130] In other words, the bias circuit 18 enables compensation for the change in the bit line current I ij caused by the drift of the transconductance value g BL,i .

[0131] In addition, in this embodiment, since the reference current I REF is generated by the current source 32, it is not affected by the drift of the reference transconductance value g ref , and the update frequency f u of the timer signal TM remains constant.

[0132] Therefore, the timing of the IMC device 10 remains constant. Thus, the IMC device 10 has a total refinement time that is independent of the drift that may affect the memory cell 20.

[0133] However, the user of the IMC device 10 can change the timing of the IMC device 10, and thus change the total refinement time of the IMC device 10, by, for example, changing the supply current of the timer 45 (i.e., here, the reference current I REF ) by using an external signal EXT.

[0134] Figure 5 An embodiment of the digital detector 16 is shown. Specifically, the digital detector 16 will be described hereinafter with respect to any one of the bit lines BL 1 ,..., BL M coupled to multiple bit lines. i

[0135] The digital detector 16 includes an integration stage 110 and a counter stage 111.

[0136] In this embodiment, the integration stage 110 includes a current mirror 115 that forms a mirror image of the bit line current I i of the bit line BL BL,i in the input node 116 of the corresponding integration stage 111.

[0137] The current mirror 115 has a mirror ratio of 1:k, such that the mirrored bit line current k·I BL,i flows through the input node 116 of the integration stage 110.

[0138] Specifically, the current mirror 115 has a first branch (formed here by the corresponding PMOS transistor 117) coupled to the bit line BL i and a second branch (formed here by the corresponding PMOS transistor 118) coupled to the corresponding integration stage 110.

[0139] The sources of the PMOS transistors 117, 118 are coupled to a supply node 120 that is at a voltage V DD here. The gates of the PMOS transistors 117, 118 are coupled together and to the drain of the PMOS transistor 117. The drain of the PMOS transistor 118 is coupled to (specifically, directly connected to here) the input node 116 of the integration stage 110.

[0140] The integration stage 110 includes a first integration circuit 121, a second integration circuit 122, and a switching circuit 123 coupled between the first integration circuit 121 and the second integration circuit 122.

[0141] The first integration circuit 121 and the second integration circuit 122 are coupled to the input node 116 to receive the mirrored bit line current k·I BL,i 。

[0142] The first integration circuit 121 includes a first inverter 124 having an output terminal 125, a capacitor 127 with a capacitance of C coupled at the output terminal 125 of the first inverter 124, and a second inverter 128 whose input terminal is coupled to the output terminal 125 of the first inverter 124. A

[0143] The first inverter 124 has a power supply node coupled to the input node 116 of the integration stage 110 ( Figure 6 ) and receives a first control signal IN at its input terminal A 。

[0144] In fact, the first inverter 124 is biased by a mirror bit line current k·I BL,i .

[0145] The capacitor 127 has a first terminal coupled to the output node 125 of the first inverter 124 and a second terminal coupled to a reference node (ground here).

[0146] The output node 125 of the first inverter 124 is at a first integration voltage V A , which appears across the capacitor 127.

[0147] The second inverter 128 has a first sampling threshold hereinafter referred to as a first threshold V th1 , receives the first integration voltage V A at its input terminal, and provides a first switching signal S1 at its output terminal that varies with the variation of the first threshold V th1 and the first integration voltage V A .

[0148] Specifically, the first switching signal S1 is a logic signal that has a high logic value when the first integration voltage V A is less than the first threshold V th1 and has a low logic value when the first integration voltage V A is higher than the first threshold V th1 .

[0149] The second integration circuit 122 includes a first inverter 130 having an output terminal 131, a capacitor 132 with a capacitance of C coupled at the output terminal 131 of the first inverter 130, and a second inverter 133 whose input terminal is coupled to the output terminal 131 of the first inverter 130. B

[0150] The first inverter 130 has a power supply node ( Figure 6 ) coupled to the input node 116 of the integration stage 110 and receives a second control signal IN at its input terminal B .

[0151] In fact, the first inverter 130 is biased by the mirror bit line current k·I BL,i .

[0152] The capacitor 132 has a first terminal coupled to the output node 131 of the first inverter 130 and a second terminal coupled to a reference node (here, ground).

[0153] The output node 131 of the first inverter 130 is at a second integration voltage V B , which drops across the capacitor 131.

[0154] The second inverter 133 has a second sampling threshold V th2 referred to hereinafter as the second threshold V th2 , receives the second integration voltage V B at the input, and provides a second switching signal S2 at the output that varies with the second threshold V th2 and the second integration voltage V B .

[0155] Specifically, the second switching signal S2 is a logic signal that has a high logic value when the second integration voltage V B is less than the second threshold V th2 and has a low logic value when the second integration voltage V B is higher than the second threshold V th2 .

[0156] In this embodiment, the first threshold V th1 is equal to the second threshold V th2 ; however, depending on the specific application, the first threshold V th1 can be different from the second threshold V th2 .

[0157] The switching circuit 123 is a latch formed by two inverters 135, 136 arranged in a ring configuration, a first switch 137 controlled by the first switching signal S1, and a second switch 138 controlled by the second switching signal S2.

[0158] The switching circuit 123 has a first node 140 coupled to the input of the inverter 136 and the output of the inverter 135, and a second node 141 coupled to the output of the inverter 136 and the input of the inverter 135.

[0159] The first node 140 provides a first control signal IN A . The second node 141 provides a second control signal IN B .

[0160] The first switch 137 is coupled between the first node 140 and the node at voltage V’ DD and the second switch 138 is coupled between the second node 141 and the node at voltage V’ DD .

[0161] The voltage V’ DD can be equal to or different from the voltage V of the power supply node 120 DD . For example, if the voltage V’ DD is different from (in particular, less than) the voltage V DD , then the digital detector 16 can include a voltage scaling circuit (e.g., a transistor) not shown here, and the source and drain terminals of the voltage scaling circuit are coupled between the power supply node 120 and the input node 116 of the integration stage 110

[0162] In this embodiment, the switch circuit 123 also receives an enable signal EN that controls the activation of the switch circuit 123. For example, the enable signal EN can be used to keep the switch circuit 123 off when not in use, thereby enabling optimization of power consumption. Additionally, for example, when the IMC device 10 is turned on, the enable signal EN can be used to set the switch circuit 123 in a defined state

[0163] The charge counter stage 111 is coupled to the first node 140 and the second node 141 of the switch circuit 123

[0164] Specifically, the charge counter stage 111 includes: an inverter 144 whose input terminal is coupled to the second node 141; and a counter that includes an inverter 145 whose input terminal is coupled to the first node 140 and a plurality of D flip - flops 147 including a first flip - flop 147.2, a second flip - flop 147.3, and a last flip - flop 147.F, where F is the number of bits of the output signal y i .

[0165] In fact, the counter of the charge counter stage 111 has F - 1 flip - flops 147

[0166] The output terminal of the inverter 144 provides the first bit y i of the output signal y i (1), i.e., the least significant bit

[0167] In other words, at the end of the calculation performed by the IMC device 10, the output terminal of the inverter 144 can be used as the least significant bit y i of the output signal y i (1)

[0168] The flip - flops 147 are cascaded with each other in order from the first flip - flop 147.2 to the last flip - flop 147.F

[0169] Each of the flip - flops 147 has a clock input terminal (CK input terminal), a data input terminal (D input terminal), a Q output terminal, and an output terminal.

[0170] The CK input terminal of the first flip - flop 147.2 is coupled to the output terminal of the inverter 145. The output terminal of the first flip - flop 147.2 is fed back to the D input terminal of the first flip - flop 147.2. The Q output terminal of the first flip - flop 147.2 forms the second bit y i (2) of the output signal y. i (2).

[0171] The CK input terminal of the second flip - flop 147.3 is coupled to the output terminal of the first flip - flop 147.2. The output terminal of the second flip - flop 147.3 is fed back to the D input terminal of the second flip - flop 147.3. The Q output terminal of the second flip - flop 147.3 forms the third bit y i (3) of the output signal y. i (3).

[0172] The description of the second flip - flop 147.3, with necessary modifications, applies to all subsequent flip - flops (not shown here) up to the (F - 1)th flip - flop (also not shown).

[0173] Finally, the CK input terminal of the last flip - flop 147.F is coupled to the output terminal of the (F - 1)th flip - flop. The output terminal of the last flip - flop 147.F is fed back to the D input terminal of the last flip - flop 147.F. The Q output terminal of the last flip - flop 147.F forms the most significant bit y i (F) of the output signal y. i (F).

[0174] Referring to Figure 6 , the first inverter 124 of the first integration circuit 121 is a CMOS inverter formed by a series circuit of a PMOS transistor 150 and an NMOS transistor 151 coupled to each other at the output node 125. The PMOS transistor 150 and the NMOS transistor 151 receive the first control signal IN A at their respective gate terminals.

[0175] The source of the PMOS transistor 150 is coupled to the input node 116 of the integration stage 110.

[0176] The second inverter 128 of the first integration circuit 121 is a CMOS inverter, which is formed by a series circuit of a PMOS transistor 152 and an NMOS transistor 153 that are mutually coupled at a node 154 where a first switching signal S1 is provided.

[0177] The first threshold V th1 of the second inverter 128 is the switching threshold of the second inverter 128, and thus depends on the characteristics of the PMOS transistor 152 and the NMOS transistor 153, for example, the threshold or the on-resistance. In fact, the switching threshold can be the input voltage that makes the output terminal of the inverter have a high logic value or the input voltage that makes the output terminal of the inverter have a low logic value.

[0178] For example, the switching threshold of the second inverter 128 can be defined as the operating point where the corresponding input voltage (i.e., the first integration voltage V A ) is equal to the corresponding output voltage (i.e., the first switching signal S1).

[0179] The first inverter 130 of the second integration circuit 122 is a CMOS inverter, which is formed by a series circuit of a PMOS transistor 155 and an NMOS transistor 156 that are mutually coupled at an output node 131. The PMOS transistor 155 and the NMOS transistor 156 receive a second control signal IN B .

[0180] The source of the PMOS transistor 155 is coupled to the input node 116 of the integration stage 110.

[0181] The second inverter 133 of the second integration circuit 122 is a CMOS inverter, which is formed by a series circuit of a PMOS transistor 157 and an NMOS transistor 158 that are mutually coupled at a node 159 where a second switching signal S2 is provided.

[0182] The second threshold V th2 of the second inverter 133 is the switching threshold of the second inverter 133, that is, it depends on the characteristics of the PMOS transistor 157 and the NMOS transistor 158. For example, the switching threshold depends on the gate-source voltage that enables current to flow through the source-drain path of the PMOS transistor 157 and the NMOS transistor 158.

[0183] As Figure 6 shown in the detailed implementation manner, the first inverter 135 and the second inverter 136 of the switching circuit 123 are cross-coupled CMOS inverters, each of which includes a corresponding PMOS transistor 160 and a corresponding NMOS transistor 161 that are mutually connected in series between a power supply node (here at a voltage V' DD ) and the ground.

[0184] In addition, the first inverter 135 and the second inverter 136 of the switch circuit 123 each further include an enable switch (here, the PMOS transistor 162), which is coupled between the power supply node at voltage V’ DD and the PMOS transistor 160 of the corresponding inverter.

[0185] The PMOS transistor 162 is controlled by the enable signal EN.

[0186] In use, the bit line current I i of the bit line BL BL,i forms a mirror image in the integration stage 110 of the corresponding digital detector 16.

[0187] Figure 7 Shows an example of the Figure 5 time behavior of the first control signal IN A , the first integration voltage V A and the second integration voltage V B of the digital detector 16.

[0188] For t 0 < t < t 1 , the first integration voltage V A is lower than the first threshold V th,1 . Accordingly, the PMOS transistor 152 of the second inverter 128 is turned on, and the NMOS transistor 153 of the second inverter 128 is turned off. Therefore, the first switch signal S1 (not shown here) has a high value, and the first switch 137 is turned off. The first control signal IN A has a low value.

[0189] It can be seen that, for the first inverter 124 of the first integration circuit 121, for t 0 < t < t 1 , the PMOS transistor 150 is turned on and the NMOS transistor 151 is turned off.

[0190] At the same time, for t 0 < t < t 1 , the second control signal IN B has a high value. Therefore, for the first inverter 130 of the second integration circuit 122, for t 0 < t < t 1 , the PMOS transistor 155 is turned off and the NMOS transistor 156 is turned on.

[0191] Accordingly, the mirror bit line current k·I BL,i flows from the input node 116 only through the first inverter 124 of the first integration circuit 121 and does not flow through the first inverter 130 of the second integration circuit 122.

[0192] Specifically, the mirror bit line current k·I BL,i flows through the PMOS transistor 150 and charges the capacitor 127. Thus, for t 0 <t < t 1 , the first integration voltage V A increases with time.

[0193] Specifically, in the example of Figure 7 , for t 0 <t < t 1 , the first integration voltage V A increases linearly with time; however, the behavior of the first integration voltage V A depends on the specific behavior of the bit line current I 0 <t < t 1 in the middle. BL,i of the specific behavior.

[0194] When the first integration voltage V A becomes equal to the first threshold voltage V th,1 , the NMOS transistor 153 of the second inverter 128 turns on and the PMOS transistor 152 turns off.

[0195] In this embodiment, the first control signal IN A presents a high value at time t 2 .

[0196] The time delay between times t1 and t2 can correspond to, for example, the propagation delay of the second inverter 128 of the first integration circuit 121 and / or the switching time of the first switch 137.

[0197] For t 1 <t < t 2 , the mirror bit line current I BL,i continues to charge the capacitor 127; correspondingly, the first integration voltage V A increases until the maximum value (time t 2 ).

[0198] At time t 2 , when the first control signal IN A presents a high value, the second control signal IN B (not shown here) presents a low value (the inverter 136 of the switching circuit 123 receives the first control signal IN A ) at the input.

[0199] When the first control signal IN A has a high value, the PMOS transistor 150 and the NMOS transistor 151 of the first inverter 124 of the first integration circuit 121 are turned off and on respectively. At the same time, when the second control signal IN B When it has a low value, the PMOS transistor 155 and the NMOS transistor 156 of the first inverter 130 of the second integration circuit 122 are turned on and off respectively.

[0200] Accordingly, for t > t 2 , the mirror bit-line current k·I BL,i flows from the input node 116 only through the first inverter 130 of the second integration circuit 122 and does not flow through the first inverter 124 of the first integration circuit 121.

[0201] Specifically, the mirror bit-line current k·I BL,i flows through the PMOS transistor 155 and charges the capacitor 132 of the second integration circuit 122. Therefore, the second integration voltage V B increases with time starting from the moment t 2 .

[0202] Specifically, in the example of Figure 7 , for t > t 2 , the second integration voltage V B increases linearly with time; however, the behavior of the second integration voltage V B depends on the specific behavior of the bit-line current I BL,i .

[0203] When the first control signal IN A has a high value, the capacitor 127 of the first integration circuit 121 discharges through the NMOS transistor 151 of the first inverter 124. Therefore, the first integration voltage V A decreases to zero.

[0204] When the second integration voltage V B becomes equal to the second threshold voltage V th,2 (at the moment t 3 ), the NMOS transistor 158 of the second inverter 133 is turned on and the PMOS transistor 157 is turned off.

[0205] Therefore, at the moment t 4 , the second control signal IN B presents a high value, similar to that discussed above for the first control signal IN 2 corresponding to the moment t A .

[0206] Specifically, in response to the second integration voltage V B reaching the second threshold V th,2 , the second switch signal S2 switches to a low value and the second switch 138 closes, such that the second node 141 is at the voltage V’ DD , and accordingly, the second control signal IN B Exhibits a high value.

[0207] Time t 3 and t 4 The time delay between can correspond to, for example, the propagation delay of the second inverter 133 of the second integration circuit 122 and / or the switching time of the second switch 138.

[0208] For t 3 <t < t 4 , the mirror bit line current k·I BL,i Keeps charging the capacitor 132 of the second integration circuit 122; correspondingly, the second integration voltage V B Increases until the maximum value (time t 4 ).

[0209] For t 2 <t < t 4 , the switching circuit 123 holds the first control signal IN A At a high value and holds the second control signal IN B At a low value.

[0210] At time t 4 , in response to the second control signal IN B Exhibiting a high value, the first control signal IN A Exhibits a low value again.

[0211] In response to the first control signal IN A Exhibiting a low value, the mirror bit line current k·I BL,i Returns to charging the capacitor 127 of the first integration circuit 121 until time t 6 , similar to what has been discussed for t 1 <t < t 2 Discussed.

[0212] Therefore, from time t 6 To time t 7 , the mirror bit line current k·I BL,i Charges the capacitor 132 of the second integration circuit 122 until time t 7 , similar to what has been discussed for t 2 <t < t 4 Discussed.

[0213] Referring again to Figure 5 , the counter stage 111 (specifically the flip - flop 147) counts the number of switching events of the first control signal IN A , specifically in this embodiment, counts the number of rising edges of the first control signal IN A .

[0214] In fact, each of the digital detectors 16 measures the corresponding bit line BL by performing a plurality of consecutive sampling iterations. i of the bit line current I BL,i . In each sampling iteration, for example, for the sampling iteration in which the mirrored bit line current k·I BL,i flows through the first integration circuit 121, the integration stage 110 generates a first integration voltage V A as the time integration of the mirrored bit line current k·I BL,i , compares the first integration voltage V A with a first threshold V th,1 , and in response to the first integration voltage V A reaching the first threshold V th,1 (specifically here by switching the first control signal IN A ) resets the first integration voltage V A . The counter stage 110 updates the corresponding output signal y A in response to the first integration voltage V th,1 reaching the first threshold V i .

[0215] In this embodiment, the least significant bit of the output signal y i is the value of the second control signal IN B at the end of the calculation performed by the IMC device 10.

[0216] In other words, the digital detector 16 samples the corresponding bit line current I BL,i by converting the bit line current I BL,i into a plurality of charge packets and counting the charge packets, where each charge packet corresponds to the charge accumulated on the capacitors 127, 132, which causes the switching of the second inverters 128, 133.

[0217] Thus, the capacitors 127, 132 can have a small capacitance compared to the case where the bit line current is integrated all at once into a single capacitor having a capacitance of C tot . Specifically, the capacitance of the capacitors 127, 132 can be 2 tot times smaller than the capacitance C F , where F is the number of bits of the output signal y i .

[0218] Therefore, the digital detector 16 can have a low die area, and correspondingly, the IMC device 10 can have a low manufacturing cost.

[0219] In addition, when the bit line current I BL,i flows through the corresponding bit line BL i , each of the digital detectors 16 starts to discretize the corresponding bit line current I BL,i Therefore, the output signal y i can be ready shortly after the computation performed by the IMC device 10 ends or shortly after the corresponding bit line current I BL,i stops.

[0220] For example, according to one embodiment, the digital detector 16 can sample each of the corresponding bit line currents I BL,i until the digital detector 16 receives a stop signal, such as from a user of the IMC device 10 or from the word line activation circuit 14, indicating the end of the computation performed by the IMC device 10.

[0221] Therefore, the digital detector 16 can have a fast measurement time, enabling the IMC device 10 to have a low computation time.

[0222] Furthermore, according to the illustrated embodiment, the switch circuit 123 disables the first integration circuit 121 and enables the second integration circuit 122 in response to the first integration signal V A reaching a first threshold V th,1 and enables the first integration circuit 121 and disables the second integration circuit 122 in response to the second integration signal V B reaching a second threshold V th,2 Thereby enabling the bit line current I

[0223] to be alternately sampled by the first integration circuit 121 and the second integration circuit 122, enabling the bit line current I BL,i to charge the capacitor 127 while the capacitor 132 is discharging and to charge the capacitor 132 while the capacitor 127 is discharging. By doing so, no charge is lost during sampling, and the digital detector 16 can achieve high measurement accuracy of the bit line current I BL,i BL,i According to one embodiment, referring again to Figure 2

[0224] , the word line activation circuit 14 can include an end-of-computation comparator 170, as indicated by the dashed line. Figure 2 The end-of-computation comparator 170 receives a timer signal TM

[0225] <l:1>and the maximum count signal MAX_COUNT <l:1>, and provides an end count signal END as a response.

[0226] Maximum count signal MAX_COUNT <l:1>May be received from a user of the IMC device 10 and indicate a maximum duration of a computation to be performed by the IMC device 10. For example, a maximum count signal MAX_COUNT <l:1>may indicate a maximum duration that is equal to or higher than the time it takes for any one of the output signals y i to reach a corresponding maximum value (e.g., all F bits equal to 1) when all the cells 20 associated with the bit line BL i are activated. However, the maximum count signal MAX_COUNT <l:1>It is possible to indicate a smaller maximum duration, for example, if a shorter computation time of the IMC device 10 is desired.

[0227] Referring again to Figure 6 , the integration stage 110 may also include a first stop switch and a second stop switch (here, the first NMOS transistor 171 and the second NMOS transistor 172) indicated by dashed lines, which prevent the corresponding digital detector 16 from sampling the corresponding bit line current I BL,i from being sampled.

[0228] Specifically, the first NMOS transistor 171 and the second NMOS transistor 172 have drain terminals respectively coupled to the output nodes 127, 131 of the first integrated circuit 121 and the second integrated circuit 122; and source terminals coupled to a reference potential line (here, ground). The first NMOS transistor 171 and the second NMOS transistor 172 receive an end count signal END at their respective gate terminals.

[0229] When the timer signal TM <l:1>Becomes equal to the maximum count signal MAX_CNT <l:1>When the calculation is completed, the end comparator 170 switches the end signal END to a high logic value, thereby turning on the first NMOS transistor 171 and the second NMOS transistor 172, and shorting the output nodes 127 and 131 of the first integration circuit 121 and the second integration circuit 122 to ground.

[0230] Accordingly, the first integration circuit 121 and the second integration circuit 122 stop integrating the bit line current BL i from being integrated.

[0231] In fact, the end count signal END can be used to determine the end of the MAC calculation of the IMC device 10.

[0232] Figure 8 and Figure 9 shows a circuit diagram of the timer 45 of the line activation circuit 14 according to one embodiment Figure 2 of.

[0233] The timer 45 includes a current mirror 180 that generates an oscillator current I REF from a reference current I OSC and a counting section 181 that provides a timer signal TM from the oscillator current I OSC .

[0234] The current mirror 180 has a mirror ratio of 1:p, such that the oscillator current I OSC is p·I REF .

[0235] Specifically, the current mirror 180 has a first branch (formed here by the corresponding PMOS transistor 183) coupled to the current source 32 and a second branch (formed here by the corresponding PMOS transistor 184) coupled to the counting section 181.

[0236] The source electrodes of the PMOS transistors 183 and 184 are coupled to a power supply node 185 (here at a voltage V DD ), the gate electrodes of the PMOS transistors 183 and 184 are coupled to each other and to the drain electrode of the PMOS transistor 183. The drain electrode of the PMOS transistor 184 is coupled to (specifically, here directly connected to) the input node 187 of the counting section 181.

[0237] The counting section 181 of the timer 45 includes an integration stage 190 formed here by a first integration circuit 191, a second integration circuit 192, and a switching circuit 193 coupled between the first integration circuit 191 and the second integration circuit 192, and a counter stage 195 coupled to the integration stage 190 and providing the timer signal TM.

[0238] The first integrating circuit 191 and the second integrating circuit 192 are coupled to the input node 187 to receive the oscillator current I OSC .

[0239] The first integrating circuit 191 includes a first inverter 197 having an output terminal 198, a capacitor 199 with a capacitance of C' coupled at the output terminal 198 of the first inverter 197, and a second inverter 200 whose input terminal is coupled to the output terminal 198 of the first inverter 197. A

[0240] The first inverter 197 has a power supply node coupled to the input node 187 of the counting unit 181 ( Figure 9 ) and receives the first oscillator control signal OS at the input terminal A .

[0241] In fact, the first inverter 197 is biased by the oscillator current I OSC .

[0242] The capacitor 199 has a first terminal coupled to the output node 198 of the first inverter 197 and a second terminal coupled to a reference potential node (ground here).

[0243] The output node 198 of the first inverter 197 is at the first oscillator integration voltage V', which appears across the capacitor 199. A

[0244] The second inverter 200 has a first oscillator threshold V' (hereinafter simply referred to as the first threshold V') th,1 , receives the first oscillator integration voltage V' at the input terminal th1 , and provides a first oscillator switch signal S'1 that varies with the change of the first threshold V' A and the first oscillator integration voltage V'. th1 A Specifically, when the first oscillator integration voltage V'

[0245] is less than the first threshold V', the first oscillator switch signal S'1 has a high logic value. When the first oscillator integration voltage V' A is higher than the first threshold V', the first oscillator switch signal S'1 has a low logic value. th1 A th1

[0246] The second integrating circuit 192 includes a first inverter 202 having an output terminal 203, a capacitor with a capacitance of C' coupled at the output terminal 203 of the first inverter 202 B ​​​​​​A capacitor 204, and a second inverter 205 whose input terminal is coupled to the output terminal 203 of the first inverter 202.

[0247] The first inverter 202 has a power supply node coupled to the input node 187 of the counting unit 181 ( Figure 9 ), and receives a second oscillator control signal OS at the input terminal B .

[0248] In fact, the first inverter 202 is biased by an oscillator current I OSC .

[0249] The capacitor 204 has a first terminal coupled to the output node 203 of the first inverter 202 and a second terminal coupled to a reference potential node (here, the ground).

[0250] The output node 203 of the first inverter 202 is at a second oscillator integration voltage V', B which drops across the capacitor 204.

[0251] The second inverter 205 has a second oscillator threshold V' hereinafter abbreviated as the second threshold V', th2 receives the second oscillator integration voltage V' at the input terminal, th2 and provides a second oscillator switch signal S'2 that varies with the change of the second threshold V' B and the second oscillator integration voltage V th2 at the output terminal. B Specifically, when the second oscillator integration voltage V

[0252] is less than the second threshold V', B the first oscillator switch signal S'2 has a high logic value. When the second oscillator integration voltage V' th2 is higher than the second threshold V', B the second oscillator switch signal S'2 has a low logic value. th2 In this embodiment, the first threshold V' of the second inverter 200

[0253] is equal to the first threshold V of the second inverter 128 of the digital detector 16 ( th1 ). The second threshold V' of the second inverter 205 Figure 5 and Figure 6 is equal to the second threshold V of the second inverter 133 of the digital detector 16 ( th1 ). th2 is equal to the second threshold V of the second inverter 133 of the digital detector 16 ( Figure 5 and Figure 6 ). th2

[0254] Referring again to Figure 8 , the switching circuit 193 is a latch formed by two inverters 208 and 209 arranged in a ring configuration, a first switch 210 controlled by a first oscillator switch signal S'1, and a second switch 211 controlled by a second switch signal S'2.

[0255] The switching circuit 193 has a first node 213 coupled to the input terminal of the inverter 209 and the output terminal of the inverter 208, and a second node 214 coupled to the output terminal of the inverter 209 and the input terminal of the inverter 208.

[0256] The first node 213 provides a first oscillator control signal OS A . The second node 214 provides a second oscillator control signal OS B .

[0257] The first switch 210 is coupled between the first node 213 and a node at voltage V' DD , and the second switch 211 is coupled between the second node 214 and a node at voltage V' DD .

[0258] According to one embodiment, the voltage V' of the counting section 181 of the timer 45 DD can be equal to the voltage V' of the integration stage 110 of the digital detector 16 ( Figure 5 ). DD .

[0259] In Figure 8 the embodiment, the switching circuit 193 also receives an oscillator enable signal EN' that controls the activation of the switching circuit 193. For example, the oscillator enable signal EN' can be used to keep the switching circuit 193 off when not in use, thereby enabling optimization of power consumption. Additionally, for example, when the IMC device 10 is turned on, the enable signal EN' can be used to set the switching circuit 193 in a defined state.

[0260] The counter stage 195 is coupled to the first node 213 and the second node 214 of the switching circuit 193.

[0261] Specifically, the charge counter stage 195 includes: an inverter 216 whose input terminal is coupled to the second node 214; and a counter that includes an inverter 217 whose input terminal is coupled to the first node 213 and a plurality of D flip - flops 218 including a first flip - flop 218.2, a second flip - flop 218.3, and a last flip - flop 218.L, where L is the timer signal TM <l:1>Number of bits.

[0262] In fact, the counter of the charge counter stage 195 has L-1 flip-flops 218.

[0263] The output terminal of the inverter 216 provides the first bit TM(1) of the timer signal TM, that is, the least significant bit.

[0264] The flip-flops 218 are cascaded with each other in order from the first flip-flop 218.2 to the last flip-flop 218.L.

[0265] Each of the flip-flops 218 has a clock input terminal (CK input terminal), a data input terminal (D input terminal), a Q output terminal and an output terminal.

[0266] The CK input terminal of the first flip-flop 218.2 is coupled to the output terminal of the inverter 217. The output terminal of the first flip-flop 218.2 is fed back to the D input terminal of the first flip-flop 218.2. The Q output terminal of the first flip-flop 218.2 forms the timer signal TM <l:1>The second TM (2).

[0267] The CK input terminal of the second flip-flop 218.3 is coupled to the output terminal of the first flip-flop 218.2. The output terminal of the second flip-flop 218.3 is fed back to the D input terminal of the second flip-flop 218.3. The Q output terminal of the second flip-flop 218.3 forms the timer signal TM <l:1>The third TM(3).

[0268] The description of the second flip-flop 218.3, with necessary modifications, applies to all subsequent flip-flops (not shown here) up to the (L-1)-th flip-flop (also not shown).

[0269] Finally, the CK input of the last flip-flop 218.L is coupled to the output of the (L-1)-th flip-flop. The output of the last flip-flop 218.L is fed back to the D input of the last flip-flop 218.L. The Q output of the last flip-flop 218.L forms the timer signal TM <l:1>The most significant bit TM(L).

[0270] Reference Figure 9 Referring to the detailed implementation of the integration stage 190 shown in Figure 9 , the first inverter 197 of the first integration circuit 191 is a CMOS inverter formed by a series circuit of a PMOS transistor 220 and an NMOS transistor 221 coupled to each other at an output node 198. The PMOS transistor 220 and the NMOS transistor 221 receive a first oscillator control signal OS at respective gate terminals. A .

[0271] The source of the PMOS transistor 220 is coupled to an input node 187 of the integration stage 190 of the timer 45.

[0272] The second inverter 200 of the first integration circuit 191 is a CMOS inverter formed by a series circuit of a PMOS transistor 222 and an NMOS transistor 223 coupled to each other at a node 224 providing a first oscillator switch signal S’1.

[0273] The first threshold V’ of the second inverter 200 th1 is the switching threshold of the second inverter 200 and thus depends on the characteristics of the PMOS transistor 222 and the NMOS transistor 223, e.g., the threshold or the on-resistance. In fact, the switching threshold can be the input voltage that makes the output terminal of the inverter have a high logic value or the input voltage that makes the output terminal of the inverter have a low logic value.

[0274] For example, the switching threshold of the second inverter 200 can be defined as the operating point where the corresponding input voltage (i.e., the first oscillator integration voltage V’ A ) is equal to the corresponding output voltage (i.e., the first oscillator switch signal S’1).

[0275] The first inverter 202 of the second integration circuit 192 is a CMOS inverter formed by a series circuit of a PMOS transistor 225 and an NMOS transistor 226 coupled to each other at an output node 203. The PMOS transistor 225 and the NMOS transistor 226 receive a second oscillator control signal OS at respective gate terminals. B .

[0276] The source of the PMOS transistor 225 is coupled to an input node 187 of the counting section 190 of the timer 45.

[0277] The second inverter 205 of the second integration circuit 192 is a CMOS inverter formed by a series circuit of a PMOS transistor 227 and an NMOS transistor 228 coupled to each other at a node 229 providing a second oscillator switch signal S’2.

[0278] The second threshold V' of the second inverter 205 th2 is the switching threshold of the second inverter 205 and thus depends on the characteristics of the PMOS transistor 227 and the NMOS transistor 228, such as the threshold or the on-resistance. In fact, the switching threshold can be the input voltage that makes the output terminal of the inverter have a high logic value or the input voltage that makes the output terminal of the inverter have a low logic value.

[0279] For example, the switching threshold of the second inverter 205 can be defined as the operating point where the corresponding input voltage (i.e., the second oscillator integration voltage V' B ) is equal to the corresponding output voltage (i.e., the second oscillator switching signal S'2).

[0280] As Figure 9 shown in the detailed implementation of, the first inverter 208 and the second inverter 209 of the switching circuit 193 are cross-coupled CMOS inverters, each including a corresponding PMOS transistor 230 and a corresponding NMOS transistor 231 that are serially coupled to each other between a power supply node (here at voltage V' DD ) and ground.

[0281] In addition, the first inverter 208 and the second inverter 209 of the switching circuit 193 also each include a corresponding enable switch (here a PMOS transistor 232) coupled between the power supply node at voltage V' DD and the PMOS transistor 230 of the corresponding inverter.

[0282] The PMOS transistor 232 is controlled by the oscillator enable signal EN'.

[0283] In this embodiment, referring to Figure 9 , the timer 45 includes a first stop switch and a second stop switch (here a first NMOS transistor 234 and a second NMOS transistor 235) configured to prevent the timer 45 from updating the timer signal TM.

[0284] Specifically, the first NMOS transistor 234 and the second NMOS transistor 235 have drain terminals respectively coupled to the output nodes 198, 203 of the first integrated circuit 191 and the second integrated circuit 192; and source terminals coupled to a reference value (here ground). The first NMOS transistor 234 and the second NMOS transistor 235 receive the end count signal END at their respective gate terminals.

[0285] When the end calculation comparator 195( Figure 2 )When the end signal END is switched to a high logic value, the first NMOS transistor 234 and the second NMOS transistor 235 are turned on, thereby shorting the output nodes 198 and 203 of the first integration circuit 191 and the second integration circuit 192 to ground.

[0286] Accordingly, the timer 45 stops updating the timer signal TM.

[0287] In fact, in this embodiment, the circuit diagram of the timer 45 (specifically, the corresponding integration stage 181) is identical to Figure 5 the circuit diagram of any one of the digital detectors 16 (specifically, the corresponding integration stage 110).

[0288] Therefore, in the same way as any one of the digital detectors 16 generates the output signal y BL,i based on the corresponding bit line current I i the timer 45 generates the timer signal TM based on the oscillator current I OSC <l:1>。

[0289] Therefore, timer 45 generates a timer signal TM by performing a plurality of consecutive timing iterations <l:1>. In each timing iteration, for example, for the timing iteration in which the oscillator current I OSC flows through the first integration circuit 191, the integration stage 190 generates a first integrated oscillation voltage V’ A as the time integration of the oscillator current I OSC , compares the first oscillator integrated voltage V’ A with a first threshold V’ th,1 , and in response to the first oscillator integrated voltage V’ A reaching the first threshold V’ th,1 (specifically here by switching the first control signal OS A ) resets the first oscillator integrated voltage V’ A . The counter stage 195 updates the timer signal TM A in response to the first oscillator integrated voltage V’ th,1 reaching the first threshold V’ <l:1>。

[0290] In this embodiment, the least significant bit of the timer signal TM is the second oscillator control signal OS B value.

[0291] In other words, timer 45 samples the oscillator current I OSC by converting it into a plurality of charge packets and counting the charge packets, where each charge packet corresponds to the charge accumulated on capacitors 199, 204, which causes the switching of the second inverters 200, 205. OSC

[0292] Therefore, the timer signal TM <l:1>Update frequency f u is given by the switching event frequency of the first oscillator control signal OS A (similar to that discussed for the first control signal IN Figure 5 ). Thus, the update frequency f A depends on the oscillator current I u , i.e., depends on the reference current I OSC and the mirror factor p of the current mirror 180, the capacitances C’ REF , C’ A as well as the first threshold V’ B and the second threshold V’ th,1 of the second inverters 200, 205 th,2 .

[0293] In fact, the integrator stage 110 of the timer 45 acts as a current-controlled oscillator

[0294] In use, the timer 45 generates the timer signal TM BL,i in the same way as the digital detector 16 generates the corresponding output signal y i respectively according to the respective bit line currents I OSC according to the oscillator current I <l:1>The fact (in particular the fact that the corresponding integrating circuits 110, 181 have the same circuit diagram) enables the timer signal TM to be obtained <l:1>with the output signals y 1 , …, y M a strong correlation exists.

[0295] Therefore, possible global variations such as the offset of the supply voltages V DD , V’ DD and / or temperature variations that may affect the IMC device 10 are compensated for by the timer 45 and the digital detector 16 and thus do not affect the accuracy of the MAC operations performed by the IMC device 10.

[0296] By varying the oscillator current I OSC , for example, by using the external signal EXT to vary the reference current I REF , the timer signal TM <l:1>Update frequency f u , thereby modifying the total calculation time of the IMC device 10.

[0297] In fact, for example, the oscillator current I OSC increase means that the oscillator integrated voltages V’ A , V’ B ( Figure 8 and 9 ) increase faster; correspondingly, the first oscillator control signal OS A and the second oscillator control signal OS B switch faster, thereby also increasing the timer signal TM <l:1>Update frequency f u 。

[0298] Figure 10 Shows different embodiments of the digital detector indicated here by 322.

[0299] By way of example, in the following, it will be directed to the bit line BL shown in detail in Figure 10 The digital detector 322 will be described with respect to the digital detector 322. M 。

[0300] The digital detector 322 includes an integration stage 330 and a counter stage 331.

[0301] The integration stage 330 includes a first integration circuit 334, a second integration circuit 335, and a switch circuit 336 coupled between the first integration circuit 334 and the second integration circuit 335.

[0302] Specifically, the switch circuit 336 includes a first switch 337 and a second switch 338 that respectively couple the bit line BL M To the first integration circuit 334 and the second integration circuit 335.

[0303] The first switch 337 and the second switch 338 are controlled by a selection signal SEL such that if the first switch 337 is open, the second switch 338 is closed, and if the first switch 337 is closed, the second switch 338 is open.

[0304] Specifically, in this embodiment, the switch circuit 336 further includes an inverter 339 that receives the selection signal SEL and is coupled to the first switch 337 at the output.

[0305] In fact, the switch circuit 336 enables the bit line current I BL,M To flow through the first integration circuit 334 or the second integration circuit 335.

[0306] The first integration circuit 334 includes a first operational amplifier 341, a feedback circuit 342, and a second operational amplifier 343.

[0307] The first operational amplifier 341 has an inverting input terminal coupled to the first switch 337 of the switch circuit 336, receives a bias voltage Vr from a bias circuit 18 ( Figure 1 ) at the non-inverting input terminal, and has an output terminal 344 that provides a voltage V q1 。

[0308] The feedback circuit 342 is coupled between the inverting input terminal and the output terminal 344 of the first operational amplifier 341 and is formed by a parallel circuit including a feedback capacitor 345 and a switch 346.

[0309] The second operational amplifier 343 has a non-inverting input terminal coupled to the output terminal 344 of the first operational amplifier 341, receives the first sampling threshold voltage V at the inverting input terminal th,1 , and has an output terminal 347 that provides the first output voltage V out1 .

[0310] The commutation of the switch 346 is controlled by the first output voltage V out,1 .

[0311] The second integration circuit 335 includes a first operational amplifier 350, a feedback circuit 351, and a second operational amplifier 352.

[0312] The first operational amplifier 350 has an inverting input terminal coupled to the second switch 338 of the switch circuit 336, receives the bias voltage Vr from the bias circuit 18 ( Figure 1 ) at the non-inverting input terminal, and has an output terminal 353 that provides the voltage V q2 .

[0313] The feedback circuit 351 is coupled between the inverting input terminal and the output terminal 353 of the first operational amplifier 350, and is formed by a parallel circuit including a feedback capacitor 355 and a switch 356.

[0314] The second operational amplifier 352 has a non-inverting input terminal coupled to the output terminal 353 of the first operational amplifier 350, receives the second sampling threshold voltage V at the inverting input terminal th,2 , and has an output terminal 357 that provides the second output voltage V out,2 .

[0315] The commutation of the switch 356 is controlled by the second output voltage V out,2 .

[0316] Here, the first threshold voltage V th,1 and the second threshold voltage V th,2 are equal; however, the first threshold voltage V th,1 and the second threshold voltage V th,2 can be different from each other.

[0317] The charge counter stage 331 includes a first counting circuit formed here by a plurality of flip-flops 360 coupled to the first integration circuit 334 and providing a first intermediate output signal y' M ; and a second counting circuit formed here by a plurality of flip-flops 361 coupled to the second integration circuit 335 and providing a second intermediate output signal y'' M .

[0318] Specifically, the flip-flop 360 is a D flip-flop and includes a first flip-flop 360.1, a second flip-flop 360.2, and a last flip-flop 360.F, where F is the number of bits of the first intermediate output signal y'. M of the bits.

[0319] The flip-flops 360 are cascaded with each other in order from the first flip-flop 360.1 to the last flip-flop 360.F.

[0320] Each of the flip-flops 360 has a clock input terminal (CK input terminal), a data input terminal (D input terminal), a Q output terminal, and an output terminal.

[0321] The CK input terminal of the first flip-flop 360.1 is coupled to the output terminal 347 of the second operational amplifier 343. The output terminal of the first flip-flop 360.1 is fed back to the D input terminal of the first flip-flop 360.1. The Q output terminal of the first flip-flop 360.1 forms the least significant bit y' M of the first intermediate output signal y' M (1).

[0322] The CK input terminal of the second flip-flop 360.2 is coupled to the output terminal of the first flip-flop 360.1. The output terminal of the second flip-flop 360.2 is fed back to the D input terminal of the second flip-flop 360.2. The Q output terminal of the second flip-flop 360.2 forms the second bit y' M of the first intermediate output signal y' M (2).

[0323] The description of the second flip-flop 360.2 is applied to all subsequent flip-flops 360 (not shown here) with necessary modifications until the (F - 1)-th flip-flop (also not shown).

[0324] Finally, the CK input terminal of the last flip-flop 360.F is coupled to the output terminal of the (F - 1)-th flip-flop. The output terminal of the last flip-flop 360.F is fed back to the D input terminal of the last flip-flop 360.F. The Q output terminal of the last flip-flop 360.F forms the most significant bit y' M of the first intermediate output signal y' M (F).

[0325] The flip-flop 361 is a D flip-flop and includes a first flip-flop 361.1, a second flip-flop 361.2, and a last flip-flop 361.F, where F is the number of bits of the second intermediate output signal y". M of the bits.

[0326] The flip - flops 361 are cascaded with each other in order from the first flip - flop 361.1 to the last flip - flop 361.F.

[0327] Each of the flip - flops 361 has a clock input terminal (CK input terminal), a data input terminal (D input terminal), a Q output terminal, and an output terminal.

[0328] The CK input terminal of the first flip - flop 361.1 is coupled to the output terminal 357 of the second operational amplifier 352. The output terminal of the first flip - flop 361.1 is fed back to the D input terminal of the first flip - flop 361.1. The Q output terminal of the first flip - flop 361.1 forms the least significant bit y” M of the second intermediate output signal y” M (1).

[0329] The CK input terminal of the second flip - flop 361.2 is coupled to the output terminal of the first flip - flop 361.1. The output terminal of the second flip - flop 361.2 is fed back to the D input terminal of the second flip - flop 361.2. The Q output terminal of the second flip - flop 361.2 forms the second bit y” M of the second intermediate output signal y” M (2).

[0330] The description of the second flip - flop 361.2, with the necessary modifications, applies to all subsequent flip - flops 361 (not shown here) up to the (F - 1)th flip - flop (also not shown).

[0331] Finally, the CK input terminal of the last flip - flop 361.F is coupled to the output terminal of the (F - 1)th flip - flop. The output terminal of the last flip - flop 361.F is fed back to the D input terminal of the last flip - flop 361.F. The Q output terminal of the last flip - flop 361.F forms the most significant bit y” M of the second intermediate output signal y” M (F).

[0332] The digital detector 322 further includes a combinational circuit 363 that receives the first intermediate output signal y’ M from the flip - flop 360 and the second intermediate output signal y” M from the flip - flop 361, and in response provides an output signal y M . For example, the combinational circuit 363 can provide the output signal y M by summing the first intermediate output signal y’ M with the second intermediate output signal y” M .

[0333] In use, the switch circuit 336 causes the bit line current I BL,M to flow through the first integration circuit 334 or the second integration circuit 335.

[0334] Referring Figure 11 to the exemplary waveforms of 0 , at t

[0335] the first switch 337 is closed and the second switch 338 is open. M Accordingly, the bit line BL

[0336] is biased by the bias voltage Vr at the non-inverting input terminal of the first operational amplifier 341 of the first integration circuit 334. 0 In addition, at t out,1 the first output voltage V out,2 and the second output voltage V

[0337] have a low logic value, thereby keeping the switches 346, 356 open. BL,M The bit line current I q1 charges the capacitor 345 of the first integration circuit 334. Accordingly, the voltage V

[0338] at the output terminal 344 of the first operational amplifier 341 increases with time. q1 When the voltage V th reaches the threshold voltage V 1 (at time t out,1 ), the second operational amplifier 343 switches the first output voltage V DD to a high logic value, here to V

[0339] In response, the switch 346 closes, thereby discharging the capacitor 345 of the first integration circuit 334. Correspondingly, the voltage V q1 at the output terminal 344 decreases.

[0340] In addition, in response to the first output voltage V out,1 presenting a high logic value, the select signal SEL switches, thereby disconnecting the first switch 337 of the switch circuit 336 and closing the second switch 338.

[0341] Accordingly, at time t 1 the bit line BL M is coupled to the second integration circuit 335 and is biased by the read voltage Vr at the non-inverting input of the first operational amplifier 350.

[0342] The bit line current I BL,M Flows through the second integration circuit 335, thereby charging the corresponding capacitor 355. The voltage V at the output terminal 353 of the first operational amplifier 350 q2 increases.

[0343] When the voltage V q2 reaches the threshold voltage V th (at time t 2 ), the second operational amplifier 352 switches the second output voltage V out,2 to a high logic value, here to V DD .

[0344] In response, the switch 356 closes, thereby discharging the capacitor 355 of the second integration circuit 335. Accordingly, the voltage V at the output terminal 353 q2 decreases.

[0345] In addition, in response to the first output voltage V out,1 presenting a high logic value, the selection signal SEL switches, thereby opening the first switch 337 of the switch circuit 336 and closing the second switch 338.

[0346] Thus, similar to that discussed above with reference to time t 1 , at time t2, the bit - line current I BL,M flows through the first integration circuit 334 again. The voltage V q1 therefore starts to increase.

[0347] The flip - flop 360 counts the number of rising events of the first output voltage V out,1 (i.e., the number of times the voltage V q1 becomes equal to the threshold voltage V th ).

[0348] The flip - flop 361 counts the number of rising events of the second output voltage V out,2 (i.e., the number of times the voltage V q2 becomes equal to the threshold voltage V th ).

[0349] In fact, additionally in this embodiment, the digital detectors 322 each measure the bit - line current I i of the corresponding bit - line BL BL,i by performing multiple consecutive corresponding sampling iterations. In each sampling iteration, for example, for the sampling iteration in which the bit - line current I BL,i flows through the first integration circuit 334, the integration stage 330 generates an integration voltage V q1 as the time integral of the bit - line current I BL,i , compares the integration voltage V q1 with the first threshold V th,1 , and in response to the integration voltage V q1 Reach the first threshold V th,1 (Specifically, here the integration voltage V is reset by closing switch 346) q1 . The counter stage 331 responds to the integration voltage V q1 Reach the first threshold V th,1 and update the output signal y i .

[0350] Similar to the content discussed for capacitors 127, 132 of the digital detector 16( Figure 5 ), capacitors 345, 355 can have small capacitance values and can measure the bit line current I BL,i when flowing through the corresponding bit line BL i BL,i .

[0351] Obviously, the IMC device 10 can be modified and varied without departing from the scope of the present utility model, as defined in the appended claims.

[0352] The memory cell 20 can be a resistive memory cell based on a different technology rather than on PCM material; for example, it can be a magnetoresistive (MRAM), resistive (RRAM), or static (SRAM) memory cell.

[0353] In addition, the storage element 25 of each memory cell 20 can be formed by, for example, a plurality of selectable resistive elements that are arranged in parallel with each other between the corresponding bit line and the ground, and these resistive elements can be selectively enabled or disabled during the programming of the memory array 12, so that the corresponding transconductance value g ij can be a multi-bit value.

[0354] For example, Figure 1 the reference impedance Z of the reference network 33 of REF can be a variable impedance that can be controlled by the user in response to the drift of the memory cell 20, and this variable impedance is obtained in a manner different from the shown manner (i.e., it may not include the reference memory cell 40).

[0355] For example, the timer 45 can be a current-controlled timer different from that shown in Figure 8 and Figure 9 . For example, the timer 45 can be based on a different current-controlled oscillator, such as a ring oscillator with an odd number of inverters.

[0356] For example, the timer signal TM can be an analog signal, and the input time converter 46 can be configured to convert the corresponding input value x j ​Convert it into an analog signal and compare the analog input signal with an analog timer signal. For example, the timer signal can be a voltage ramp generated from a current, especially a voltage ramp generated by a reference current I REF generated voltage ramp; in this case, the update frequency of the analog timer signal indicates the slope of the voltage ramp.

[0357] Alternatively, the timer of the word line activation circuit 14 can provide the timer signal TM in a different way, for example, provided without responding to a current. For example, the timer can be a voltage-controlled timer.

[0358] For example, the integration stages 110, 330 of the digital detectors 16, 322 may only include one integration circuit, and thus do not even include the corresponding switching circuits. For example, Figure 12 different embodiments of the digital detector indicated here by 422 are shown, and each digital detector only includes a first integration circuit 334 and a first counter circuit 360. In fact, Figure 12 the digital detector 422 does not include the reference Figure 10 the switching circuits 336, the second integration circuit 335 and the second counter circuit 361 discussed.

[0359] The integration stage of each digital detector can be coupled to the corresponding bit line BL differently from that shown and described. i For example, Figure 5 the integration stage 110 can be coupled to the bit line BL without the current mirror 115. i such that the integration stage 110 directly receives the bit line current I at the input node 116. BL,i .

[0360] The circuit diagram of the integration stage 190 of the timer 45 can be the same as that of the integration stage 110, 330, 430 of any one of the digital detectors 16, 322, 422, that is, they can have equivalent circuit elements for providing an integration signal and equivalent circuit elements for providing a control signal from the integration signal.

[0361] In other words, for example, as discussed above with reference to Figure 5 and Figure 8 the integration stage of the timer and the integration stage of the digital detector can each have a first inverter and a capacitor for providing an integration signal, and a second inverter for providing a control signal for the corresponding counter stage.

[0362] In this case, the capacitor of the integrating stage of the digital detector and the capacitor of the integrating stage of the timer may have the same capacitance value; and / or the first inverter of the integrating stage of the digital detector may be equivalent to the first inverter of the integrating stage of the timer; and / or the second inverter of the integrating stage of the digital detector may be equivalent to the second inverter of the integrating stage of the timer, for example, having the same switching threshold.

[0363] The integrating stages of the timer and the digital detector may each have only one integrating circuit (e.g., similar to that discussed in reference Figure 12 ), or have a first integrating circuit and a second integrating circuit coupled to each other through a switching circuit.

[0364] Finally, the illustrated embodiments can be combined to provide further solutions.

[0365] For example, the charge counter stage 110 of the digital detector 16 ( Figure 5 ) may include a second set of flip - flops coupled to the second node 141 of the switching circuit 123 instead of the inverter 144, and a combining circuit, similar to that described in reference Figure 10 .

[0366] Additionally or alternatively, the charge counter stage 195 of the timer 45 ( Figure 8 ) may include a second set of flip - flops coupled to the second node 214 of the switching circuit 193 instead of the inverter 216, and a combining circuit, similar to that described in reference Figure 10 .

[0367] For example, referring to Figure 10 , the operational amplifier 343 or 352 may be replaced by an inverter, as in the digital detector 16 of Figure 5 . In fact, the integrating stage and the counter stage of the digital detector may each be formed by a combination of elements of the digital detectors 16, 322 that respectively form Figure 5 and Figure 10 . Similar considerations apply, with the necessary modifications, to the integrating stage and the counter stage of the timer, and according to one embodiment, its circuit diagram may be the same as that of the integrating stage and the counter stage of the digital detector. ​ ​ ​

Claims

1. An in-memory computing device, characterized in that: The in-memory computing device comprises: a word line activation circuit configured to receive an input signal indicative of a plurality of input values ​​and to provide a plurality of activation signals, wherein each activation signal varies as a corresponding input value varies; a bias circuit configured to provide a bias voltage in response to a reference current; A memory array comprising a plurality of memory cells coupled to bit lines and each coupled to a corresponding word line, wherein the bit lines are configured to receive the bias voltage, wherein each memory cell comprises a storage element for storing a corresponding calculation weight and a selection element for receiving a corresponding activation signal from the corresponding word line, wherein a corresponding cell current flowing through each memory cell is generated by the storage element and the selection element based on the bias voltage, the corresponding activation signal and the corresponding calculation weight, and wherein the bit line current flowing through the bit line varies as a sum of cell currents of memory cells coupled to the bit line varies; and A digital detector is coupled to the bit line and configured to sample the bit line current and, in response, provide at least one output signal.

2. The in-memory computing device according to claim 1, characterized in that The bias circuit includes a reference network having a variable reference impedance, the reference current flows through the reference network, wherein the bias voltage varies with changes in the reference current and the variable reference impedance.

3. The in-memory computing device according to claim 2, wherein: The reference network includes a reference memory array configured to have a reference transconductance value, wherein the variable reference impedance varies as the reference transconductance value varies, the reference memory array representing a statistically significant sample of the memory array.

4. The in-memory computing device according to claim 1, wherein: The activation signals are each a pulse signal, the duration of which is a proportional function of the corresponding input value.

5. The in-memory computing device according to claim 1, wherein: The wordline activation circuit includes a timer configured to provide a timer signal, and a plurality of input time converters configured to compare the timer signal with corresponding input values ​​and to provide corresponding activation signals in response.

6. The in-memory computing device according to claim 5, characterized in that: The timer is configured to provide the timer signal in response to an oscillator current, wherein the timer is configured to update the timer signal at an update frequency that varies with changes in the oscillator current.

7. The in-memory computing device according to claim 6, characterized in that: The timer is configured to generate the oscillator current based on the reference current.

8. The in-memory computing device according to claim 7, wherein: The in-memory computing device is further configured to receive an external signal from a user, wherein the oscillator current varies as the external signal varies.

9. The in-memory computing device according to claim 8, characterized in that: The timer comprises an integration stage and a counter stage and is configured to perform a plurality of consecutive timing iterations, wherein in each timing iteration: the integrating stage being configured to generate a corresponding integrated signal indicative of a time integral of the oscillator current, compare the integrated signal to an oscillator threshold, and reset the integrated signal in response to the integrated signal reaching the oscillator threshold; and The counter stage is configured to update the timer signal in response to the integrated signal reaching the oscillator threshold.

10. The in-memory computing device according to claim 5, wherein: The word line activation circuit is configured to compare the timer signal to a maximum count signal and, in response, provide an end count signal, wherein the digital detector is configured to receive the end count signal and stop sampling the bit line current in response to receiving the end count signal.

11. The in-memory computing device according to claim 9, wherein: The digital detector comprises an integration stage and a counter stage and is configured to perform a plurality of consecutive sampling iterations, wherein in each sampling iteration: the integration stage being configured to generate an integration signal indicative of a time integral of the bit line current, compare the integration signal to a sampling threshold, and reset the integration signal in response to the integration signal reaching the sampling threshold; and The counter stage is configured to update the output signal in response to the integrated signal reaching the sampling threshold.

12. The in-memory computing device according to claim 11, wherein: The integrating stage of the digital detector has the same circuit diagram as the integrating stage of the timer.

13. The in-memory computing device according to claim 11, wherein: The integrating stage includes a first inverter having an output terminal providing the integrated signal and an integrating capacitive element coupled at the output terminal of the first inverter, wherein the first inverter is configured to receive a bias current indicative of the bit line current.

14. The in-memory computing device according to claim 13, wherein: The first inverter has an input terminal configured to receive a control signal indicating that the integrated signal reaches the sampling threshold, and wherein the first inverter is configured to charge the integral capacitance element with the bias current or discharge the integral capacitance element as the control signal changes.

15. The in-memory computing device according to claim 11, characterized in that: The integrating stage includes a first operational amplifier having a first input and an output, and an integrating capacitive element coupled between the first input of the first operational amplifier and the output of the first operational amplifier, and wherein the first operational amplifier is configured to receive a current indicative of the bit line current at the first input.

16. The in-memory computing device according to claim 11, wherein: The integration stage includes a second inverter having a switching threshold and receiving the integrated signal, wherein the sampling threshold is the switching threshold of the second inverter.

17. The in-memory computing device according to claim 11, wherein: The integrating stage comprises a second operational amplifier having a first input and a second input, and wherein the second operational amplifier is configured to receive the integrated signal at the first input and the sampling threshold at the second input.

18. The in-memory computing device according to claim 11, wherein: the integration signal is a first integration signal and the sampling threshold is a first sampling threshold, the integration stage includes a first integration circuit, the first integration circuit is configured to generate the first integration signal, compare the first integration signal with the first sampling threshold and reset the first integration signal, the integration stage also includes a second integration circuit and a switch circuit coupled between the first integration circuit and the second integration circuit; wherein the second integration circuit is configured to generate a second integration signal indicative of a time integral of the bit line current, compare the second integration signal with a second sampling threshold, and reset the second integration signal in response to the second integration signal reaching the second sampling threshold; wherein the counter stage is configured to update the output signal further in response to the second integrated signal reaching the second sampling threshold; The switch circuit is configured to disable the first integration circuit and enable the second integration circuit in response to the first integration signal reaching the first sampling threshold, and to enable the first integration circuit and disable the second integration circuit in response to the second integration signal reaching the second sampling threshold.

19. The in-memory computing device according to claim 1, wherein: The memory cells each have a current path including the storage element and the selection element and extending between a common node and a reference potential node, wherein the selection element is configured to selectively close a corresponding current path as a corresponding activation signal changes.

20. The in-memory computing device of claim 1, wherein: The memory cells are non-volatile memory cells.

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