Nationwide production, storage and calculation integrated device
By designing a nationally produced storage and computing integrated device, the non-national production, space unoptimized and security problems of VPX recording module are solved, and the integration of recording and storage functions and computing functions is realized, reducing costs and space requirements, and improving security performance.
Patent Information
- Application Number
- CN202421749784.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2034-07-23
AI Technical Summary
In the prior art, the non-national production of the VPX recording module, the space is not optimized, the recording and storage functions and the computing functions are not on the same PCB board, and the electronic disk is connected to the FPGA device through the imported PCIE switching chip, which lacks security.
A national production, storage and computing integrated device is designed, integrating the first FPGA device, the second FPGA device, the CPU processor and the electronic disk. All devices are set on the same PCB board, and domestically produced devices are used to achieve the integration of recording and storage functions and computing functions.
It achieves the effect of reducing costs and space, while improving safety performance and avoiding the security risks of imported devices.
Smart Images
Figure CN222896399U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of chassis, and specifically relates to a domestically produced storage and computing integrated device. Background Art
[0002] With its flexibility, efficiency, safety, and high cost-effectiveness, drones have become an important combat force that cannot be ignored in the future battlefield. They will undertake a large number of tasks such as aerial reconnaissance, auxiliary strikes, navigation and guidance, and precision destruction, and play a very critical role in the battlefield environment that integrates sea, land, air, space, and electricity. The collected QB data of sensors such as LD, SAR, infrared, remote sensing, and voice signals require online data storage and computing capabilities. Since WRJ is small in size and has high requirements for flexibility and maneuverability, too much load cannot be added.
[0003] In the face of these problems, the recording module should not only have the ability to record and store, but also the ability to process dynamic data online. That is, with the increasing amount of data and the diversification of data types, it should be able to process multi-source heterogeneous data in real time at the near data end. In addition, considering the space in the WRJ cabin, the size of the equipment should be strictly controlled. At present, most of the existing recording modules in the industry use the VPX architecture: the storage circuit uses imported PCIE switching chips + electronic disks; after the LD data is collected, it is stored in the recording module; the data is dumped to the debugging PC through a gigabit or 10-gigabit network for data processing and analysis.
[0004] However, the existing technology is limited by the technical solutions of the current VPX recording modules. They are not domestically produced, the space is not optimized to the minimum, the recording storage function and the computing function are not on the same PCB board, or even in the same chassis. If the recording storage function and the computing function are to be realized at the same time, greater costs and space are required; and the electronic disk is connected to the FPGA device through an imported PCIE switching chip, which lacks security. Utility Model Content
[0005] The purpose of the utility model is to solve the problems raised in the background technology and to provide a national production storage and calculation integrated device.
[0006] In order to achieve the above purpose, the technical solution adopted by the utility model is:
[0007] The utility model proposes a domestic storage and computing integrated device, which is located in a chassis. The domestic storage and computing integrated device is arranged on a PCB board. The domestic storage and computing integrated device includes a first FPGA device, a second FPGA device, a CPU processor and an electronic disk, wherein:
[0008] The electronic disk includes a preset number of solid-state hard disks, each of which is electrically connected to the second FPGA device;
[0009] The first FPGA device and the CPU processor are both electrically connected to the second FPGA device;
[0010] The CPU processor is mounted with a DDR4 cache chip.
[0011] Preferably, the national integrated storage and computing device further includes a BMC monitoring chip and a CPLD chip, the BMC monitoring chip is electrically connected to the CPLD chip respectively, and the CPLD chip is electrically connected to the CPU processor.
[0012] Preferably, the national integrated storage and computing device also includes a power supply module, which is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip respectively.
[0013] Preferably, the national integrated production, storage and computing device also includes a VPX connector, and the VPX connector is provided with a first interface, a second interface, a third interface and a fourth interface. The power supply module is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip through the first interface, the second interface is electrically connected to the BMC monitoring chip, the first FPGA device and the second FPGA device, the third interface is electrically connected to the second FPGA device, and the fourth interface is electrically connected to the second FPGA device.
[0014] Preferably, the national integrated storage and computing device also includes a network connector, which is electrically connected to the CPU processor.
[0015] Preferably, the network connector includes a first network connector and a second network connector, the first network connector includes a first PHY chip and an RJ45 interface, and the CPU processor, the first PHY chip and the RJ45 interface are electrically connected in sequence;
[0016] The first network connector further includes a second PHY chip, and the second PHY chip is electrically connected to the fourth interface;
[0017] The second network connector includes a network chip and a second photoelectric converter, and the CPU processor, the network chip and the second photoelectric converter are electrically connected in sequence.
[0018] Preferably, the national integrated storage and computing device also includes a first photoelectric converter, and the fourth interface is electrically connected to the second FPGA device through the first photoelectric converter.
[0019] Preferably, the national storage and computing integrated device also includes a debugging serial port arranged on the front panel of the chassis and electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip in a one-to-one correspondence.
[0020] Compared with the prior art, the beneficial effects of the utility model are:
[0021] The domestic storage and computing integrated device reduces costs and space by integrating a first FPGA device with computing functions, a second FPGA device, and an mSATA disk with recording and storage functions on a single PCB board. The domestic storage and computing integrated device uses domestically produced devices, does not require imported devices, and improves safety performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 This is a module block diagram of the national storage and computing integrated device of the utility model. DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0024] It should be noted that when a component is referred to as being "connected" to another component, it may be directly connected to the other component or there may be an intermediate component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0025] like Figure 1 As shown, a domestic storage and computing integrated device is located in a chassis, the domestic storage and computing integrated device is arranged on a PCB board, and the domestic storage and computing integrated device includes a first FPGA device, a second FPGA device, a CPU processor and an electronic disk, wherein:
[0026] The electronic disk includes a preset number of solid-state hard disks, each of which is electrically connected to the second FPGA device;
[0027] The first FPGA device and the CPU processor are both electrically connected to the second FPGA device;
[0028] The CPU processor is equipped with a DDR4 cache chip.
[0029] It should be noted that the devices on the domestic storage and computing integrated device of this invention are all arranged on the same PCB board and are located in the chassis. In this embodiment, the CPU processor adopts Feiteng processor, each FPGA device adopts Virtex-7 FPGA (domestic Fudan Micro FPGA chip), and the electronic disk includes six independent mSATA disks (mSATA SSDs), which are fixedly mounted on the PCB board, and each mSATA disk is connected to the second FPGA device through the SATA bus and the AVIC Optronics CTOLC / CSOLC series high-speed differential connector. The mSATA disk and the second FPGA device are used as the storage function of this structure, responsible for data recording and storage, and each mSATA SSD in this embodiment is 1TB, forming a total storage capacity of 6TB; the first FPGA device is used for user data calculation and processing; the first FPGA device and the second FPGA device are connected through the high-speed bus GTH, and an eight-way high-speed bus GTH is provided to realize the communication between the first FPGA device and the second FPGA device (following the Aurora protocol), and the second FPGA device sends the recorded and stored data to the first FPGA device for data processing and analysis, and realizes both the recording and storage function and the calculation and processing function through the first FPGA device, the second FPGA device and the mSATA disk;
[0030] The CPU processor communicates with the second FPGA device through a 2-way X8 PCI Express bus. The CPU sends commands to the second FPGA device to control the second FPGA device to start the data reading and writing function, and to record and store data. The second FPGA device uses an IP core to implement the PCI Express interface. Four DDR4 cache chips are mounted on the CPU processor as data cache.
[0031] In one embodiment, the national storage and computing integrated device also includes a BMC monitoring chip (model BMC GD32) and a CPLD chip. The BMC monitoring chip is electrically connected to the CPLD chip, and the CPLD chip is electrically connected to the CPU processor.
[0032] It should be noted that the first FPGA device, the second FPGA device and the CPU processor all have built-in temperature sensors. The first FPGA device reports the temperature detected by the temperature sensor to the second FPGA device via the GTH bus, and then the second FPGA device reports the received information to the CPU processor. The second FPGA device reports the temperature detected by the temperature sensor to the CPU processor via the PCIE bus. The CPU processor transmits the temperature information of each FPGA device and its own temperature to the BMC monitoring chip through the CPLD chip to realize the temperature monitoring function. The CPU processor is connected to the domestic CPLD chip via the GPIO bus.
[0033] In one embodiment, the integrated storage and computing device also includes a power supply module (using a 12V power supply voltage), which is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip respectively to provide power to each device.
[0034] In one embodiment, the national storage and computing integrated device also includes a VPX connector, which is provided with a first interface, a second interface, a third interface and a fourth interface. The power supply module is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip through the first interface, the second interface is electrically connected to the BMC monitoring chip, the first FPGA device and the second FPGA device, the third interface is electrically connected to the second FPGA device and the CPU processor, and the fourth interface is electrically connected to the second FPGA device.
[0035] Among them, Figure 1 In the example, the first interface is the P0 interface, the second interface is the P1 interface, the third interface is the P3 interface, and the fourth interface is the P4 interface. Figure 1 A P2 interface is also provided on the VPX connector, which can be used according to needs (wherein the P0 interface, P1 interface, P2 interface, P3 interface, and P4 interface are the five interfaces on the VPX connector); the power supply module is electrically connected to the first FPGA device, the second FPGA device, the CPU processor, and the BMC monitoring chip through the first interface (P0 interface) to realize power supply to each device; the second interface (P1 interface) is electrically connected to the BMC monitoring chip to provide an RS232 serial port of the BMC monitoring chip for debugging, the second interface (P1 interface) is electrically connected to the first FPGA device to provide a group of SPIO X4 high-speed buses, the second interface (P1 interface) is electrically connected to the second FPGA device to provide two groups of SRIO X4 high-speed buses; the third interface (P3 interface) is electrically connected to the second FPGA device to provide two groups of SRIO X4 high-speed buses, and the third interface (P3 interface) is electrically connected to the CPU processor to provide an RS232 serial port of the CPU processor.
[0036] In one embodiment, the national storage and computing integrated device also includes a network connector, which is electrically connected to the CPU processor.
[0037] The network connector includes a first network connector and a second network connector, the first network connector includes a first PHY chip and an RJ45 interface, and the CPU processor, the first PHY chip and the RJ45 interface are electrically connected in sequence;
[0038] The first network connector also includes a second PHY chip, and the second PHY chip is electrically connected to the fourth interface;
[0039] The second network connector includes a network chip and a second photoelectric converter, and the CPU processor, the network chip and the second photoelectric converter are electrically connected in sequence.
[0040] It should be noted that the network connector includes a Gigabit network connector (first network connector) and a 10 Gigabit network connector (second network connector). The Gigabit network connector includes a first network card (first PHY chip and RJ45 interface) directly output from the CPU processor, which is converted to the 1000base-T Gigabit Ethernet standard through the first PHY chip, connected to the RJ45 interface set on the front panel of the chassis through a high-speed interface signal, and provides an external MDI Ethernet interface to realize network data interaction and command transmission with an external PC;
[0041] The Gigabit network connector also includes a second network card (second PHY chip) directly output from the CPU processor, which is converted into the SGMII / 1000base-X Gigabit Ethernet standard through the second PHY chip and connected to the P3 interface of the VPX connector to realize network data interaction with other boards.
[0042] The 10 Gigabit network connector is connected to the network chip (using WX1820 chip) by the CPU processor through the PCIE bus, expanding a 10 Gigabit network 10G SFI interface, and converting it into an optical signal through the second photoelectric converter. The LC interface of the second photoelectric converter (the second photoelectric converter is embedded in the front panel and provides an external LC interface) provides an external 10 Gigabit network optical fiber interface to realize 10 Gigabit network data interaction.
[0043] In one embodiment, the integrated storage and computing device also includes a first photoelectric converter, and the fourth interface is electrically connected to the second FPGA device through the first photoelectric converter.
[0044] It should be noted that the second FPGA device provides 24 GTH high-speed buses, of which 12 are used as GTH TX and 12 are used as GTH RX, all of which are connected to the first photoelectric converter. The first photoelectric converter converts the electrical signal into an optical signal, and provides a 24-core MT optical interface to the outside through the first photoelectric converter to transmit the optical signal; the MT connector of the first photoelectric converter is fixed on the G1 hole of the P4 interface of the VPX connector.
[0045] In one embodiment, the national storage and computing integrated device also includes a debugging serial port arranged on the front panel of the chassis and electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip in a one-to-one correspondence.
[0046] The debugging serial port includes two JTAG serial ports for debugging two FPGA devices respectively, and the debugging serial port also includes two RS232 serial ports for debugging the BMC monitoring chip and the CPU processor respectively.
[0047] The first FPGA device and the second FPGA device are respectively connected to two DDR4 cache chips and a FLASH flash memory, and the CPU processor is also connected to an M.2 boot disk and a FLASH flash memory.
[0048] The domestic storage and computing integrated device reduces costs and space by integrating a first FPGA device with computing functions, a second FPGA device, and an mSATA disk with recording and storage functions on a single PCB board. The domestic storage and computing integrated device uses domestically produced devices, does not require imported devices, and improves safety performance.
[0049] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0050] The above-described embodiments only express the more specific and detailed embodiments described in this application, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this application, which all belong to the protection scope of this application. Therefore, the protection scope of the patent application shall be based on the attached claims.
Claims
1. A domestic storage and computing device, located in a chassis, characterized in that: The nationally produced storage and computing integrated device is arranged on a PCB board, and the nationally produced storage and computing integrated device comprises a first FPGA device, a second FPGA device, a CPU processor and an electronic disk, wherein: The electronic disk includes a preset number of solid-state hard disks, each of which is electrically connected to the second FPGA device; The first FPGA device and the CPU processor are both electrically connected to the second FPGA device; The CPU processor is mounted with a DDR4 cache chip.
2. The integrated national production, storage and computing device according to claim 1, characterized in that: The national integrated storage and computing device also includes a BMC monitoring chip and a CPLD chip. The BMC monitoring chip is electrically connected to the CPLD chip, and the CPLD chip is electrically connected to the CPU processor.
3. The integrated national production, storage and computing device according to claim 2, characterized in that: The national integrated storage and computing device also includes a power supply module, which is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip respectively.
4. The national integrated production, storage and computing device according to claim 3, characterized in that: The national integrated production, storage and computing device also includes a VPX connector, on which a first interface, a second interface, a third interface and a fourth interface are provided. The power supply module is electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip through the first interface, the second interface is electrically connected to the BMC monitoring chip, the first FPGA device and the second FPGA device, the third interface is electrically connected to the second FPGA device, and the fourth interface is electrically connected to the second FPGA device.
5. The national integrated production, storage and computing device according to claim 4, characterized in that: The national integrated storage and computing device also includes a network connector, which is electrically connected to the CPU processor.
6. The integrated national production, storage and computing device according to claim 5, characterized in that: The network connector includes a first network connector and a second network connector, the first network connector includes a first PHY chip and an RJ45 interface, and the CPU processor, the first PHY chip and the RJ45 interface are electrically connected in sequence; The first network connector further includes a second PHY chip, and the second PHY chip is electrically connected to the fourth interface; The second network connector includes a network chip and a second photoelectric converter, and the CPU processor, the network chip and the second photoelectric converter are electrically connected in sequence.
7. The national production, storage and calculation integrated device as claimed in claim 4, characterized in that: The national integrated production, storage and computing device also includes a first photoelectric converter, and the fourth interface is electrically connected to the second FPGA device through the first photoelectric converter.
8. The integrated national production, storage and computing device according to claim 2, characterized in that: The national storage and computing integrated device also includes a debugging serial port arranged on the front panel of the chassis and electrically connected to the first FPGA device, the second FPGA device, the CPU processor and the BMC monitoring chip in a one-to-one correspondence.