Semiconductor device

Abstract

A semiconductor device includes a semiconductor nanostructure stack, a source / drain region adjacent to the semiconductor nanostructure stack, a bottom dielectric layer underlying the source / drain region, a liner layer, and a conductive core layer. The source / drain region has a top surface, a plurality of sidewalls and a bottom surface. An aperture is present between the source / drain region and the bottom dielectric layer. A liner layer is on the source / drain region. A conductive core layer is on the liner layer, wherein the conductive core layer is in contact with the liner layer on a top surface, sidewalls, and a bottom surface of the source / drain region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling has also increased the complexity of processing and manufacturing ICs. Summary of the Utility Model

[0003] According to at least one embodiment, a semiconductor device includes a semiconductor nanostructure stack, a source / drain region adjacent to the semiconductor nanostructure stack, a bottom dielectric layer underlying the source / drain region, a liner layer, and a conductive core layer. The source / drain region has a top surface, a plurality of sidewalls, and a bottom surface. A pore exists between the source / drain region and the bottom dielectric layer. The liner layer is located on the source / drain region. The conductive core layer is located on the liner layer, wherein the conductive core layer contacts the liner layer on the top surface, sidewalls, and bottom surface of the source / drain region.

[0004] According to at least one embodiment, a semiconductor device includes a semiconductor nanosheet channel stack, a source / drain region, a dielectric layer, an interlayer dielectric, and a conductive core layer. The semiconductor nanosheet channel stack is located on a semiconductor fin. The source / drain region is adjacent to the semiconductor nanosheet channel stack, wherein a pore exists between the source / drain region and the semiconductor fin. The dielectric layer is on the source / drain region and in the pore. The interlayer dielectric is on the source / drain region and the dielectric layer. The conductive core layer contacts a top surface and a plurality of sidewalls of the source / drain region.

[0005] According to at least one embodiment, a semiconductor device includes: a semiconductor nanostructure stack; a source / drain region adjacent to the stack, the source / drain region having a top surface, a plurality of sidewalls, and a bottom surface; a bottom dielectric layer underlying the source / drain region; a source / drain contact that contacts the top surface and the plurality of sidewalls of the source / drain region and is between an upper surface of the bottom dielectric layer and the source / drain contact. Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a diagrammatic cross-sectional side view of a part of an IC device according to an embodiment of the present disclosure;

[0008] Figures 2A to 12 are views of various embodiments of an IC device according to various aspects of the present disclosure at various manufacturing stages;

[0009] Figure 13 is a flowchart of a method of manufacturing a semiconductor device according to various aspects of the present disclosure.

[0010]

Reference Signs

[0011] 10: IC wafer

[0012] 20A: First nanostructure device

[0013] 20B: Second nanostructure device

[0014] 21: First semiconductor layer

[0015] 21A~21C: First semiconductor layer

[0016] 22: Nanostructure

[0017] 22A~22C: Channel / nanostructure

[0018] 22A2~22C2: Channel

[0019] 23: Second semiconductor layer

[0020] 24: Nanostructure

[0021] 25: Multilayer stack

[0022] 26: Vertical stack

[0023] 32: Semiconductor fin

[0024] 36: Isolation region

[0025] 40:Dummy or sacrificial gate structure

[0026] 41: Gate spacer layer / sidewall spacer

[0027] 45: Sacrificial gate layer

[0028] 47: Mask layer

[0029] 49: Source / drain opening

[0030] 49V: Pore

[0031] 49U: Undercut region

[0032] 64: Recess

[0033] 74: Inner spacer

[0034] 82: Source / drain region

[0035] 92: Recess

[0036] 110: Substrate

[0037] 110A: First epitaxial layer

[0038] 120: Source / drain contact

[0039] 120L: Liner layer

[0040] 120C: Core layer

[0041] 120S: Spacer layer

[0042] 120X: Source / drain contact opening

[0043] 130: Interlayer dielectric

[0044] 131: Protection layer / dielectric layer / CESL

[0045] 131T: Top part

[0046] 131S: Sidewall part

[0047] 131B: Bottom part

[0048] 131V: Pore part

[0049] 170: Region

[0050] 200: Gate structure

[0051] 210: Interface layer

[0052] 290: Gate filling layer / metal filling layer

[0053] 600: Gate dielectric layer

[0054] 800A: Bottom dielectric layer

[0055] 802: Backside interconnect structure

[0056] 810: First backside interlayer dielectric

[0057] 820: Second dorsal interlayer dielectric

[0058] 830: First dorsal via or contact

[0059] 840: First dorsal trace or wire

[0060] 860: Plasma treatment

[0061] 900: Work function tuning layer

[0062] 1000: Method of manufacturing a semiconductor device

[0063] 1100: Operation

[0064] 1200: Operation

[0065] 1300: Operation

[0066] 1400: Operation

[0067] 1500: Operation

[0068] 1600: Operation

[0069] 1700: Operation

[0070] 1800: Operation

[0071] 1900: Operation

[0072] 2000: Operation

[0073] 2100: Operation

[0074] 2200: Operation

[0075] 2300: Operation

[0076] 2400: Operation

[0077] CD1: Distance Detailed Description

[0078] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0079] Additionally, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, may be used herein for ease of description to describe the relationship of one or more elements or features shown in the figures to another element or feature. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly as well.

[0080] Throughout this disclosure, depending on the context, the source / drain region may refer to the source or the drain individually or collectively.

[0081] This disclosure is generally directed to electronic devices, and more particularly to electronic devices including: FETs such as planar field-effect transistors (FETs); three-dimensional fin FETs (FinFETs) or nanostructure FETs such as gate-all-around (GAA) FETs, nanosheet (NS) FETs, nanowire (NW) FETs; and the like. In a GAA FET, the gate-all-around structure provides beneficial electrostatic control of the channel region. When the gate surrounds the nanosheet from all sides, gate control is enhanced and the likelihood of leakage current is reduced, which improves transistor performance, including improved on-state current, reduced off-state leakage, and enhanced switching characteristics.

[0082] In an embodiment of this disclosure, source / drain contacts are formed to cover the source / drain region. The source / drain contacts covering the source / drain region are beneficial for reducing parasitic resistance, which improves the duty cycle performance. In an embodiment, pores are formed in the source / drain region, and a dielectric film rather than a contact etch stop layer (CESL) film is formed in the source / drain region. The dielectric film treatment is performed in the vertical direction to harden the dielectric film. The unexposed portion (e.g., the untreated side portion) of the dielectric film is removed, which prepares and leaves the dielectric film as a protective layer on the upper surface of the source / drain region while opening pores for depositing the conductive material of the source / drain contacts in a later operation.

[0083] The nanostructure device structure can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine optical lithography processes with self-alignment processes, thereby allowing patterns to be generated that have, for example, smaller pitch compared to the pitch that could otherwise be obtained using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate using an optical lithography process and patterned. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure device structure.

[0084] Figure 1A and Figure 1B is a diagrammatic cross-sectional side view of a portion of an IC wafer 10 according to various embodiments. Figure 1A Depicts a portion of the IC wafer 10 taken along a first direction that is the X-axis direction along a semiconductor fin 32 (or “fin” or “fin structure”). Figure 1B Depicts a portion of the IC wafer 10 taken along a second direction along a source / drain region 82, the second direction being the Y-axis direction perpendicular to the X-axis direction.

[0085] In Figure 1A is shown a portion of the IC wafer 10. The IC wafer 10 includes a first nanostructure device 20A and a second nanostructure device 20B, which are collectively referred to as nanostructures 20A, 20B. Each of the nanostructure devices 20A, 20B includes channels 22A, 22B, 22C, a source / drain region 82, and a gate structure 200. In the nanostructure devices 20A, 20B, the channels 22A, 22B, 22C of each device are in contact with the source / drain region 82 on either side (for simplicity, only one source / drain region 82 is depicted in Figure 1A ). The gate structure 200 envelops the respective channels 22A, 22B, 22C of each of the nanostructure devices 20A, 20B. A voltage bias applied at the gate structure 200 causes the channels 22A, 22B, 22C to conduct current that flows from one of the source / drain regions 82 to the other source / drain region in the source / drain region 82 based on the voltage bias applied to each. The voltage bias can be applied to the source / drain region 82 via source / drain contacts 120 that include a liner layer 120L and a core layer 120C that each envelop the source / drain region 82, as depicted in Figure 1B . Other features of the IC wafer 10 are seen as in Figures 2A to 13The process 1000 depicted therein is described in more detail. In some embodiments, the nanostructure devices 20A, 20B are part of a static random access memory (SRAM) circuit, a logic circuit, an input / output (IO) circuit, a passive device, or the like.

[0086] Figures 2A to 12 are views of various embodiments of an IC device, such as an IC wafer 10, at various manufacturing stages in accordance with various aspects of the present disclosure. Figure 13 is a flowchart of a method 1000 for fabricating a semiconductor device illustrated in accordance with various aspects of the present disclosure. The various manufacturing stages of the IC device illustrated in Figures 2A to 12 can be performed according to the method of Figure 13 . Figure 13 is a flowchart of a method 1000 for forming an IC device or a portion thereof from a workpiece illustrated in accordance with one or more aspects of the present disclosure. Method 1000 is an example and is not intended to limit the present disclosure to what is explicitly illustrated in method 1000. Additional actions can be provided before, during, and after method 1000, and some of the described actions can be replaced, eliminated, or repeated for additional embodiments of the method. For simplicity, not all actions are described in detail herein. Method 1000 is described below in connection with partial perspective views and / or cross-sectional views of the workpiece at different manufacturing stages in accordance with embodiments of method 1000 illustrated in Figures 2A to 12 . For the sake of clarity, throughout the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to both the X direction and the Y direction. Note that since the workpiece can be fabricated into a semiconductor device, the workpiece can be referred to as a semiconductor device as is beneficial for the context.

[0087] Figures 2A to 12 are a graphical perspective view and a cross-sectional view of an intermediate stage in the fabrication of a FET, such as a nanosheet FET, according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A illustrate perspective views. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 8E , Figure 8G , Figure 8I , Figure 8K ,Figure 8M , Figure 9B , Figure 10B , Figure 11C , Figure 11E , Figure 11G , Figure 11H , Figure 11I and Figure 12 The figure shows a side view taken along the reference cross-section B-B' (gate cut-away view or source / drain cut-away view; YZ plane) shown in Figure 2A , Figure 3A and Figure 4A . (Gate cut-away view or source / drain cut-away view; YZ plane). Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 8D , Figure 8F , Figure 8H , Figure 8J , Figure 8L , Figure 9C , Figure 10C , Figure 11A , Figure 11B , Figure 11D , Figure 11F and Figure 11J The figure shows a side view taken along the reference cross-section C-C' (fin cut-away view: XZ plane) shown in Figure 4A . (Fin cut-away view: XZ plane).

[0088] In Figure 2A and Figure 2B , a substrate 110 is provided. The substrate 110 can be a semiconductor substrate, such as a bulk semiconductor or the like, and the semiconductor substrate can be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor material of the substrate 110 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates can be used, such as single-layer, multi-layer, or gradient substrates.

[0089] In addition, in Figure 2A and Figure 2B , corresponding to Figure 13For the operation 1100, a multi-layer stack 25, or "lattice" or "super-lattice", is formed above a substrate 110 of alternating layers of a first semiconductor layer 21A, 21B, 21C (collectively referred to as the first semiconductor layer 21) and a second semiconductor layer 23. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for an n-type nano-FET, such as silicon, silicon carbide, or the like, and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for a p-type nano-FET, such as silicon germanium or the like. Each of the plurality of layers of the multi-layer stack 25 may be epitaxially grown using a process such as: chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.

[0090] FIG. illustrates three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23. In some embodiments, the multi-layer stack 25 may include one or both of the first semiconductor layer 21 and the second semiconductor layer 23, one by one, or may include one or both of the first semiconductor layer 21 and the second semiconductor layer 23, four or more, one by one. Although the multi-layer stack 25 depicts including the second semiconductor layer 23 as the bottommost layer, in some embodiments, the bottommost layer of the multi-layer stack 25 may be the first semiconductor layer 21.

[0091] Due to the high etch selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region of a nanostructure FET. In some embodiments, the first semiconductor layer 21 is removed, and the second semiconductor layer 23 is patterned to form the channel region. The high etch selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of a nanostructure FET.

[0092] In Figure 3A and Figure 3B corresponds to Figure 13For the operation 1200, a vertical stack 26 of fins 32 and nanostructures 22A, 22B, 22C, 24 is formed in the substrate 110 and the multi-layer stack 25. The nanostructures 22A to 22C may be collectively referred to as nanostructure 22. In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching trenches in the multi-layer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels") are formed from the first semiconductor layer 21, and the second nanostructure 24 is formed from the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be about 18 nm to about 100 nm, less than 18 nm or greater than 100 nm. For simplicity of illustration, in Figure 3A and Figure 3B a portion of the device 10 including two fins 32 is illustrated. The process 1000 illustrated in Figures 2A to 13 may be extended to any number of fins and is not limited to the two fins 32 illustrated in Figures 3A to 11J In some of the figures, three fins are depicted instead of two fins.

[0093] The fins 32 and the nanostructures 22, 24 may be patterned by any suitable method. For example, one or more optical lithography processes including double patterning or multiple patterning processes may be used to form the fins 32 and the nanostructures 22, 24. Generally, double patterning or multiple patterning processes combine optical lithography with self-alignment processes, thereby allowing a pitch smaller than that obtained using a single direct optical lithography process otherwise. As an example of a multiple patterning process, a sacrificial layer may be formed over the substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32.

[0094] Figure 3A and Figure 3B illustrate fins 32 having tapered sidewalls such that the width of each fin 32 and / or nanostructures 22, 24 continuously increases in the direction towards the substrate 110. In such embodiments, each nanostructure 22, 24 may have a different width and is trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fins 32 and the nanostructures 22, 24 are substantially similar, and each nanostructure 22, 24 is rectangular in shape.

[0095] In Figure 3A andFigure 3B In Figure 13 corresponding to operation 1300 in, an isolation region 36 of a shallow trench isolation (STI) region may be formed adjacent to the fin 32. The isolation region 36 may be formed by depositing an insulating material above the substrate 110, the fin 32, and the nanostructures 22, 24 and between the adjacent fin 32 and the nanostructures 22, 24. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. In some embodiments, a liner (not shown separately) may be first formed along the surfaces of the substrate 110, the fin 32, and the nanostructures 22, 24. Thereafter, an insulating material such as those materials discussed above may be formed above the liner.

[0096] The insulating material undergoes a removal process such as chemical mechanical polish (CMP), an etch-back process, a combination thereof, or the like, to remove the excess insulating material above the nanostructures 22, 24. The top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material after the removal process is completed.

[0097] The insulating material is then recessed to form the isolation region 36. After the recessing, the upper portions of the nanostructures 22, 24 and the fin 32 may protrude from between the adjacent isolation regions 36. The isolation regions 36 may have top surfaces that are flat, convex, concave, or a combination thereof as illustrated. In some embodiments, the isolation region 36 is recessed by an acceptable etching process such as oxide removal using, for example, diluted hydrofluoric acid (dHF), which is selective for the insulating material and leaves the fin 32 and the nanostructures 22, 24 substantially unchanged.

[0098] Figures 2A to 3B An embodiment (e.g., post-etch) of forming the fin 32 and the nanostructures 22, 24 is illustrated. In some embodiments, the fin 32 and / or the nanostructures 22, 24 are epitaxially grown in trenches in a dielectric layer (e.g., pre-etch). The epitaxial structure may include the alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0099] In some embodiments, the spacing between channels 22A to 22C (e.g., between channel 22B and channel 22A or channel 22C) is in the range of about 8 nanometers (nm) to about 12 nm. In some embodiments, the spacing is less than 8 nm. In some embodiments, the thickness of each of channels 22A to 22C (e.g., measured in the Z direction) is in the range of about 5 nm to about 8 nm. In some embodiments, the thickness is less than 5 nm. In some embodiments, the width of each of channels 22A to 22C (e.g., measured in the Y direction) is at least about 8 nm. In some embodiments, the width is less than 8 nm.

[0100] Additionally, in Figure 3A and Figure 3B , appropriate wells (not shown separately) may be formed in fins 32, nanostructures 22, 24, and / or isolation region 36. Using a mask, N-type impurity implantation may be performed in the P-type region of substrate 110, and P-type impurity implantation may be performed in the N-type region of substrate 110. Example N-type impurities may include phosphorus, arsenic, antimony, or the like. Example P-type impurities may include boron, boron fluoride, indium, or the like. Annealing may be performed after implantation to repair implantation damage and activate the P-type and / or N-type impurities. In some embodiments, in-situ doping during the epitaxial growth of fins 32 and nanostructures 22, 24 may eliminate separate implantations, although in-situ doping and implant doping may be used together.

[0101] In Figures 4A to 4B , corresponding to Figure 13 of operation 1400, a dummy or sacrificial gate structure 40 is formed over fins 32 and / or nanostructures 22, 24. A sacrificial gate layer 45 is formed over fins 32 and / or nanostructures 22, 24. The sacrificial gate layer 45 may be made of a material having a high etch selectivity relative to isolation region 36, or include such materials. The sacrificial gate layer 45 may be a conductive, semiconductor, or non-conductive material, and may include amorphous silicon, polycrystalline silicon (polysilicon), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, metal, combinations thereof, and the like. The sacrificial gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. A mask layer 47 is formed over the sacrificial gate layer 45, and may include, for example, silicon nitride, silicon oxynitride, or the like. The mask layer 47 may include one or more layers, such as a first mask layer and a second mask layer. The first mask layer may be formed in a first deposition process, and the second mask layer may be formed in a second deposition process after the first deposition process. In some embodiments, a gate dielectric layer (not shown separately) is formed between the sacrificial gate layer 45 and fins 32 and / or nanostructures 22, 24 before the sacrificial gate layer 45.

[0102] A spacer layer or sidewall spacer 41 is formed over the sidewalls of the masking layer 47, the sacrificial gate layer 45, and the isolation region 36 and covers the masking layer 47, the sacrificial gate layer 45, and the isolation region 36. According to some embodiments, the spacer layer 41 is formed of an insulating material such as SiN, SiO, SiCN, SiON, SiOCN, SiOC, or the like and may have a single-layer structure or a multi-layer structure that includes a plurality of dielectric layers. The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the masking layer 47 and the sacrificial gate layer 45. In some embodiments, the spacer layer 41 includes one or more material layers. For example, the spacer layer 41 may include a first spacer layer in contact with the sacrificial gate structure 40 and a second spacer layer in contact with the first spacer layer. The first spacer layer may be formed in a first deposition process, and the second spacer layer may be formed in a second deposition process after the first deposition process.

[0103] In some embodiments, the portions of the spacer material layer between the sacrificial gate structures 40 are not removed. For example, horizontal portions of the spacer layer 41 are present on and in contact with the respective upper surfaces of the isolation regions 36. The thickness of the spacer layer 41 may be in the range of about 5 nm to about 20 nm after its deposition. Although not depicted in a top view, the spacer layer 41 may cover the isolation regions 36. The spacer layer 41 may completely cover the isolation regions 36. In some embodiments, the spacer layer 41 substantially completely covers the isolation regions 36. For example, the spacer layer 41 may cover at least 95%, at least 90%, at least 80%, or another suitable percentage of each isolation region 36, which is beneficial to provide protection for the isolation regions 36 during an etching operation when forming source / drain openings and epitaxial layers for the isolation channels 22 and the source / drain regions 82. In some embodiments, the first spacer layer and the second spacer layer cover the isolation regions 36 as just described. In some embodiments, the second spacer layer may be removed from over the isolation regions 36 such that only the first spacer layer covers the isolation regions 36. It should be understood that the first spacer layer and the second spacer layer may cover respective peripheral portions of the isolation regions 36 regardless of whether the second spacer layer is removed from over, for example, the central portions of the isolation regions 36.

[0104] Figure 4A and Figure 4B A process for forming the spacer layer 41 is depicted. In some embodiments, an additional spacer layer may be formed after the sacrificial gate layer 45 is removed. In such embodiments, the sacrificial gate layer 45 is removed, leaving an opening, and the spacer layer may be formed by conformally coating the material of the spacer layer along the sidewalls of the opening. Before forming an active gate, such as the gate structure 200, the conformally coated material may then be removed from the bottom of the opening corresponding to the top surface of the topmost channel, e.g., channel 22A.

[0105] In Figures 5A to 5C , an etching process including one or more etching operations is performed to etch portions of the protruding fins 32 and / or nanostructures 22, 24 that are not covered by the sacrificial gate structure 40, resulting in the structures shown. Corresponding to Figure 13 action 1500, source / drain openings 49 are formed between adjacent stacks of the channel 22 that are above the same fin 32. The recessing can be anisotropic such that portions of the fin 32 directly underlying the sacrificial gate structure 40 and the spacer layer 41 are protected and not etched. According to some embodiments, the top surface of the recessed fin 32 can be substantially coplanar with the top surface of the isolation region 36. In some embodiments, the top surface of the recessed fin 32 can be recessed and slightly lower than the top surface of the isolation region 36. Figure 5C For simplicity, two vertical stacks 26 of the nanostructures 22, 24 after the etching process are shown. Generally, the etching process can be used to form any selected number of vertical stacks 26 of the nanostructures 22, 24 above the fin 32. In some embodiments, the spacer layer 41 covers the isolation region 36 such that the etching to form the source / drain openings 49 does not substantially attack the isolation region 36, and the isolation region 36 protects the sidewalls of the fin 32.

[0106] Figures 6A to 6C and Figures 7A to 7C illustrates the formation of the internal spacer 74. A selective etching process is performed to recess the end portions of the nanostructure 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructure 22, as depicted in Figures 6A to 6C . After the selective etching process, recesses 64 are formed in the nanostructure 24 at the locations where the end portions were removed. The resulting structure is shown in Figures 6A to 6C .

[0107] Next, after the recesses 64 are formed in Figures 6A to 6C , internal spacers are formed to fill (e.g., partially or completely) the recesses 64 formed in the nanostructure 22 by the previous selective etching process, as depicted in Figures 7A to 7C . The internal spacer layer can be a suitable dielectric material formed by a suitable deposition method such as PVD, CVD, ALD, or the like, such as silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. An etching process such as an anisotropic etching process is performed to remove portions of the internal spacer layer disposed outside the recesses in the nanostructure 24. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the recesses 64 in the nanostructure 24) forms the internal spacer 74. The resulting structure is shown in Figures 7A to 7C .

[0108] Corresponding to Figure 13 action 1600,Figure 7C also depicts the formation of the epitaxial layer and the bottom dielectric layer 800A according to various embodiments. After forming the source / drain openings 49 and the inner spacers 74, the source / drain openings 49 extend below the upper surface of the fins 32. In some embodiments, a first epitaxial layer 110A is formed in a portion of the source / drain openings 49 that is below the level of the upper surface of the fins 32, as Figure 7C depicted. The first epitaxial layer 110A can be an undoped semiconductor layer, such as an undoped silicon layer. The undoped silicon layer 110A can be grown in an epitaxial chamber using a process such as chemical vapor deposition (CVD). In CVD, a silicon source gas such as silane (SiH 4 ) can be introduced into the heated chamber together with a carrier gas such as hydrogen (H 2 ). The gases react on the surface of the fins 32, which can be heated to a temperature between about 900 °C and 1100 °C. During the reaction, the silicon source gas decomposes and releases silicon atoms, which then diffuse onto the surface of the fins 32 and form a single-crystalline silicon layer. A low-pressure environment can be beneficial to reduce the presence of impurities and improve deposition rate uniformity. To grow doped silicon, no additional dopant gas is introduced into the chamber. The resulting layer has a low level of impurities and is electrically neutral, such that the first epitaxial layer 110A can be an insulator layer. The formation of the first epitaxial layer 110A can be global, meaning that, for example, while CVD is in progress, no mask is present on the IC wafer 10.

[0109] After forming the first epitaxial layer 110A, a second epitaxial layer (not depicted) can be formed in a portion of the source / drain openings 49. The second epitaxial layer can be an undoped semiconductor layer, such as an undoped silicon layer, and its formation can be similar to the formation of the first epitaxial layer 110A. The second epitaxial layer can extend from the top of the fins 32 to a level above one or more of the channels 22, in order to electrically and / or physically isolate one or more channels from the source / drain regions 82 formed in subsequent processes. For example, the second epitaxial layer extends to a level higher than the lowest channel 22C. In some embodiments, the second epitaxial layer can extend to any level above the lowest channel 22C and below the uppermost channel 22A.

[0110] In Figure 7CIn [the context], after forming the first epitaxial layer 110A and optionally the second epitaxial layer, a bottom dielectric layer 800A is formed. The bottom dielectric layer 800A or a flexible bottom insulator ("FBI") is beneficial to prevent mesa leakage current in the IC wafer 10. The bottom dielectric layer 800A can be in direct contact with the first epitaxial layer 110A. The bottom dielectric layer 800A can be formed in a deposition operation and can include SiN, SiOC, SiOCN, SiCN, combinations thereof, or the like. In some embodiments, the bottom dielectric layer can have a thickness ranging from about 1 nm to about 5 nm. In some embodiments, the bottom dielectric layer has a thickness greater than 5 nm.

[0111] Figures 8A to 8M The illustration corresponds to Figure 13 the formation of the source / drain region 82 including respective pores 49V of the operation 1700. For simplicity of illustration and to provide a reference Figures 8A to 8C context description, the pores 49V are Figures 8A to 8C omitted from the view in Figures 8D to 8M [the context]. The formation of the pores 49V and the protective layer 131 is seen in

[0112] In the illustrated embodiment, the source / drain region 82 is epitaxially grown from epitaxial material. In some embodiments, the source / drain region 82 applies stress in the respective channels 22A2 to 22C2, thereby improving performance. The source / drain region 82 is formed such that each sacrificial gate structure 40 is disposed between respective adjacent pairs of source / drain regions 82. In some embodiments, the spacer layer 41 separates the source / drain region 82 from the sacrificial gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device.

[0113] The source / drain region 82 can include any acceptable material, such as an acceptable material suitable for an n-type device or a p-type device. For an n-type device, in some embodiments, the source / drain region 82 includes a material that applies tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, or the like. According to certain embodiments, when a p-type device is formed, the source / drain region 82 includes a material that applies compressive stress in the channel region, such as SiGe, SiGeB, Ge, GeSn, or the like. The source / drain region 82 can have a surface that is elevated from the respective surfaces of the fins and can have facets. Adjacent source / drain regions 82 can be merged in some embodiments to form a single source / drain region 82 adjacent to two adjacent fins 32.

[0114] In some embodiments, a first epitaxial growth process may be performed to form an n-type source / drain region 82, and a second epitaxial growth process may be performed to form a p-type source / drain region 82. It should be understood that "first" and "second" may be interchanged in this context. For example, the n-type epitaxial growth may precede or follow the p-type epitaxial growth.

[0115] The source / drain region 82 may be implanted with dopants after annealing. The source / drain region may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 . The n-type and / or p-type impurities of the source / drain region 82 may be any of the impurities discussed previously. In some embodiments, the source / drain region 82 is in-situ doped during growth. The contact etch stop layer (CESL) and the interlayer dielectric (ILD), which are not shown for simplicity in Figures 8A to 8C , may then be formed to cover the sacrificial gate structure 40 and the source / drain region 82. The formation of the contact etch stop layer (CESL) or "protective layer" 131 is described in Figures 8F to 8K , and the formation of the interlayer dielectric 130 is described in Figure 8L and Figure 8M .

[0116] In Figure 8D and Figure 8E , pores 49V are formed during the growth of the source / drain region 82. The pores 49V may have a width in the horizontal direction (e.g., the X-axis direction and / or the Y-axis direction) that is in the range of about 10 nm to about 15 nm. The pores 49V may have a height in the vertical direction (e.g., the Z-axis direction) that is in the range of about 10 nm to about half the height of the source / drain region 82. The pores 49V may be formed by selecting the parameters of the epitaxial growth process for forming the source / drain region 82. For example, the pores 49V may be formed by the early merging of the left and right sides of the source / drain region 82 depicted in Figure 8D . That is, the upper portion of the source / drain region 82 may merge before the lower portion of the source / drain region 82 is able to merge. Thus, the merged upper portion blocks the further growth of the lower portion, leaving the depicted pores 49V.

[0117] The pores 49V may extend from the bottom dielectric layer 800A to a level above the bottom dielectric layer 800A. In Figure 8DIn the example depicted in , aperture 49V extends to a level that is at or slightly above the upper surface of channel 22B. In some embodiments, aperture 49V extends to a level that overlaps channel 22B, such as a level between the upper surface of channel 22B and the lower surface of channel 22B. In some embodiments, aperture 49V extends to a level that is between the lower surface of channel 22A and the upper surface of channel 22B. In some embodiments, aperture 49V extends to a level that overlaps channel 22A, such as a level between the upper surface of channel 22A and the lower surface of channel 22A.

[0118] In the X-axis direction, Figure 8D As depicted in FIG. 4 , the lower region of the aperture 49V may include an undercut region 49U that extends below the portion of the source / drain region 82 that contacts the lowermost channel region 22A. In some embodiments, the undercut region 49U does not exist, as indicated by Figure 8D That is, the source / drain region 82 may extend downward to contact the bottom dielectric layer 800A.

[0119] Pore ​​49V Figure 8D 22B. In some embodiments, the top of aperture 49V is concave, convex, or concave and convex. In some embodiments, the sidewalls of aperture 49V are curved rather than straight. In some embodiments, the sidewalls of aperture 49V are approximately vertical or vertical.

[0120] Some process parameters may be beneficial for forming the pores 49V. For example, process parameters may be selected that increase the growth rate of the source / drain regions 82. Increasing the growth temperature may accelerate the epitaxial growth rate. For example, the source / drain regions 82 may be grown at a temperature greater than about 1000 degrees Celsius, greater than about 1100 degrees Celsius, or greater than about 1150 degrees Celsius. Increasing the temperature of the source / drain regions 82 may increase the growth rate of the epitaxial growth. 4 ) or dopant source precursor gases can increase the epitaxial growth rate. For example, source / drain regions 82 can be grown using a flow rate for one or more precursor gases (e.g., silane) that exceeds about 100 standard cubic meters per minute (sccm), exceeds about 150 sccm, exceeds about 200 sccm, or the like. Flowing a precursor gas other than silane can produce a faster growth rate. For example, dichlorosilane (SiH 2 Cl 2) can be used as a precursor for growing the source / drain regions 82 instead of silane as the silicon source. Adjusting the pressure during epitaxial growth can change the diffusion of the reactant gas and increase the growth rate. For example, a higher pressure can accelerate the epitaxial growth rate. Increasing the surface cleanliness of channels 22A to 22C can increase the nucleation rate and growth rate. For example, one or more of thorough cleaning, oxide removal, and surface treatment can be performed, which is beneficial for increasing the epitaxial growth rate. Using a rotating or showerhead reactor can increase mass transport and promote a faster growth rate by improving gas distribution and reducing boundary layer effects. One or more of the process parameter selections just described can be used individually or in combination to increase the growth rate of the source / drain regions 82, which is beneficial for promoting the early coalescence and formation of the pores 49V.

[0121] corresponding to Figure 13 action 1800, in Figure 8F and Figure 8G In, after forming the source / drain regions 82 including the pores 49V, a dielectric layer 131 is formed on the source / drain regions 82. The dielectric layer 131 can include a top portion 131T, sidewall portions 131S, a bottom portion 131B, and pore portions 131V. The top portion 131T can be on the upper surface of the source / drain regions 82. The sidewall portions 131S can be on the sidewalls of the source / drain regions 82. The bottom portion 131B can be on the exposed upper surface of the fin 32. The pore portions 131V can be in the pores 49V. In some embodiments, the pore portions 131V completely or partially fill the pores 49V. The dielectric layer 131 can be a nitride, such as SiN, SiON, SiCN, SiOCN, or the like, and the nitride can have an increased etch selectivity via plasma treatment using N2 or Ar gas. The formation of the dielectric layer 131 can include one or more suitable deposition operations, such as PVD, CVD, ALD, or the like.

[0122] In Figure 8H and Figure 8I corresponding to Figure 13 action 1900, after forming the dielectric layer 131, a plasma treatment 860 can be performed, and the plasma treatment 860 hardens the top portion 131T and the bottom portion 131B of the dielectric layer 131 and / or increases the etch selectivity of the top portion 131T and the bottom portion 131B. The plasma treatment 860 can use, for example, N 2performed with a gas of Ar or the like, and may be directional in the Z-axis direction such that the sidewall portion 131S and the pore portion 131V are not hardened and / or their etching selectivity is not increased. Increasing the etching selectivity of the top portion 131T relative to the sidewall portion 131S and the pore portion 131V slows down the etching of the top portion 131T, which allows the sidewall portion 131S and the pore portion 131V to be removed without substantially removing the top portion 131T. Thus, the top portion 131T and the bottom portion 131B can remain in contact with the contact etch stop layer (CESL) 131T, 131B, and the CESL 131T, 131B protects the source / drain regions 82 and the fins 32 in subsequent processes. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1 nm to about 5 nm.

[0123] In Figure 8J and Figure 8K corresponding to the operation 2000 of Figure 13 after the plasma treatment in Figure 8H and Figure 8I the sidewall portion 131S and the pore portion 131V are removed without substantially removing the top portion 131T and the bottom portion 131B. The removal may include one or more etching operations, such as wet etching, to produce the structures depicted in Figure 8J and Figure 8K .

[0124] In Figure 8L and Figure 8MIn , after removing the sidewall portion 131S and the pore portion 131V of the dielectric layer 131, the interlayer dielectric 130 is formed between the source / drain regions 82 and the fins 32 between the sacrificial gate layers 45 with the dielectric layer 131 therebetween. In some embodiments, the interlayer dielectric 130 may be or include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), porous dielectric materials, or the like. The interlayer dielectric 130 may be formed by suitable deposition operations, such as PVD, CVD, or ALD. In some embodiments, the interlayer dielectric 130 is formed by CVD and deposited at a relatively high deposition rate to avoid filling the pores 49V with the interlayer dielectric 130. For example, the interlayer dielectric 130 may be formed by CVD having directionality in the Z-axis direction such that the pores 49V are protected by the source / drain regions 82 and the top portion 131T. In some embodiments, some materials of the interlayer dielectric 130 may be deposited in the pores 49V on the bottom dielectric layer 800A under the source / drain regions 82, and the bottom dielectric layer 800A is depicted by a dotted line in Figure 8M In some embodiments, the interlayer dielectric 130 occupies more than 50% of the volume of the pores 49V, less than 20% of the volume of the pores 49V, less than 10% of the volume of the pores 49V, or less than 5% of the volume of the pores 49V. In some embodiments, the interlayer dielectric 130 occupies a percentage volume of the pores 49V, and the percentage is in the range of 0% to about 5%. The interlayer dielectric 130 that occupies a smaller percentage volume of the pores 49V increases the process window for forming the source / drain contacts 120 in the pores 49V to cover the source / drain regions 82.

[0125] In Figures 9A to 9C In , after forming the source / drain regions 82, the fin channels 22A to 22C are released by removing the nanostructures 24, the mask layer 47, and the sacrificial gate layer 45. A planarization process, such as CMP, is performed to make the top surfaces of the sacrificial gate layer 45 and the gate spacer layer 41 flush. The planarization process may also remove the mask layer 47 on the sacrificial gate layer 45 and multiple portions of the gate spacer layer 41 along the sidewalls of the mask layer 47. Thus, the top surface of the sacrificial gate layer 45 is exposed.

[0126] Next, the sacrificial gate layer 45 is removed in an etching process, such that a recess 92 is formed. In some embodiments, the sacrificial gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 45 without etching the spacer layer 41. When the sacrificial gate layer 45 is etched, the sacrificial gate dielectric, if present, can be used as an etch stop layer. The sacrificial gate dielectric may then be removed after the sacrificial gate layer 45 is removed.

[0127] The nanostructure 24 is removed to release the nanostructure 22. After the nanostructure 24 is removed, the nanostructure 22 forms a plurality of nanosheets that are horizontally extended (e.g., parallel to the major upper surface of the substrate 110) and vertically stacked. The nanosheets may be collectively referred to as a nanostructure device, such as a channel 22 of a nanosheet FET (NSFET) that can be a GAAFET.

[0128] In some embodiments, the nanostructure 24 is removed by a selective etching process using an etchant that is selective for the material of the nanostructure 24, such that the nanostructure 24 is removed without substantially attacking the nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and, optionally, a carrier gas, wherein the etching gas contains F 2 and HF, and the carrier gas can be an inert gas such as Ar, He, N 2 , combinations thereof, or the like.

[0129] In some embodiments, the nanostructure 24 is removed and the nanostructure 22 is patterned to form the channel regions of both PFETs and NFETs. However, in some embodiments, the nanostructure 24 may be removed and the nanostructure 22 may be patterned to form the channel region of a first nanostructure device, and the nanostructure 22 may be removed and the nanostructure 24 may be patterned to form the channel region of a second nanostructure device. In some embodiments, the nanostructure 22 may be removed and the nanostructure 24 may be patterned to form the channel region of a first nanostructure device, and the nanostructure 24 may be removed and the nanostructure 22 may be patterned to form the channel region of a second nanostructure device. In some embodiments, the nanostructure 22 may be removed and the nanostructure 24 may be patterned to form the channel regions of both PFETs and NFETs.

[0130] In some embodiments, the nanosheets 22 of the nanostructure device are reshaped (e.g., thinned) by another etching process to improve the gate fill window. The reshaping can be performed by an isotropic etching process that is selective to the nanosheets 22. After reshaping, the nanosheets 22 may exhibit a dog-bone-like tubular shape, where along the X direction, the middle portion of the nanosheets 22 is thinner than the peripheral portion of the nanosheets 22.

[0131] Next, corresponding to Figure 13 operation 2100, in Figures 10A to 10C , a replacement gate 200 such as gate structure 200 is formed. Each replacement gate 200 generally includes an interfacial layer (IL) 210, a gate dielectric layer 600, and a gate fill layer 290 (see Figure 12 ). In some embodiments, the replacement gate 200 further includes a work function metal layer. The formation of the gate structure 200 is described in Figure 12 in more detail.

[0132] Figure 11A FIG. shows a semiconductor device including an interlayer dielectric (ILD) 130. The interlayer dielectric 130 provides electrical isolation between various components of the semiconductor device discussed above, such as between the gate structure 200 and the subsequently formed source / drain contacts. In some embodiments, the insulating material for forming the interlayer dielectric 130 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), a low dielectric constant (low-k) dielectric such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxide or porous oxide (e.g., xerogel / aerogel), or the like, or a combination thereof. The dielectric material for forming the interlayer dielectric 130 can be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or the like or a combination thereof.

[0133] In Figures 11B to 11HIn [the above], a source / drain contact 120 covering the source / drain region 82 is formed. Forming the source / drain contact 120 covering the source / drain region 82 such that the conductive material of the source / drain contact 120 contacts the source / drain region 82 on at least three sides (e.g., four sides) is beneficial to reduce parasitic capacitance and improve the duty cycle ratio (DC%) of the device including the source / drain region 82.

[0134] In Figure 11B and Figure 11C corresponding to Figure 13 operation 2200, after forming the interlayer dielectric 130 and the replacement gate 200, a source / drain contact opening 120X is formed. The source / drain contact opening 120X is formed through the interlayer dielectric 130 and the CESL 131. As Figure 11B illustrated in [the above], the source / drain contact opening 120X may not completely remove the interlayer dielectric 130 and the CESL 131 in the X-Z plane. For example, the width of the source / drain contact opening 120X in the X-axis direction may be smaller than the width of the source / drain region 82. The source / drain contact opening 120X is connected to the pore 49V, as Figure 11C depicted in [the above]. For example, a portion of the source / drain contact opening 120X extends along the sidewall of the source / drain region 82 to a level below the interface between the source / drain region 82 and the pore 49V. Since the CESL 131 is removed from the sidewall of the source / drain region 82, the source / drain contact opening 120X may expose the sidewall of the source / drain region 82. Thus, the source / drain contact 120 formed in a later operation can contact the sidewall of the source / drain region 82 and the bottom surface of the source / drain region 82 exposed by the pore 49V.

[0135] Forming the source / drain contact opening 120X may include a first anisotropic etch (e.g., RIE, plasma etch, or the like) that removes the material of the interlayer dielectric 130 without substantially attacking the source / drain region 82. The anisotropic etch may terminate on the CESL 131 and / or expose the CESL 131 on top of the source / drain region 82. Then, after the first anisotropic etch, another etch operation may be performed to break through the CESL 131, and the another etch operation may be a second anisotropic etch that removes the material of the CESL 131 and substantially attacks the material of the interlayer dielectric 130. As Figure 11BAs depicted, after the second anisotropic etch, the upper surface of the source / drain region 82 may be slightly recessed and may have a recessed shape in the X-Z plane. In some embodiments, after the etch process that forms the source / drain contact opening 120X, the source / drain contact opening 120X may not be connected to the void 49V. For example, the source / drain contact opening 120X may be formed to a level that is higher than the interface between the source / drain region 82 and the void 49V such that the source / drain contact opening 120X is separated from the void 49V by the interlayer dielectric 130. In such embodiments, the later-formed source / drain contact 120 may surround the source / drain region 82 on three sides in the Y-Z plane.

[0136] Figure 11D , Figure 11E , Figure 11F and Figure 11G Illustrated is the formation of the source / drain contact 120 according to various embodiments. The source / drain contact 120 may include a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The source / drain contact 120 may be surrounded by a barrier layer or liner layer 120L such as TiN, TiSi, TiSiN, or the like, which helps prevent or reduce the diffusion of materials to and from the contact 120. A silicide layer (not separately depicted) may also be formed between the source / drain feature 82 and the source / drain contact 120 to reduce the source / drain contact resistance. The silicide layer may include nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. In some embodiments, the thickness (in the Z-axis direction) of the silicide layer is in the range of about 0.5 nm to about 5 nm. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm. In some embodiments, a spacer layer 120S is formed in the source / drain contact opening 120X on the sidewalls of the interlayer dielectric 130. The spacer layer 120S may be or include a dielectric layer such as SiN, SiCN, SiOCN, SiON, or the like. Forming the spacer layer 120S may include one or more suitable deposition operations such as PVD, CVD, ALD, or the like.

[0137] In Figure 11D and Figure 11E correspond to Figure 13The operation 2300 forms the liner layer 120L. The liner layer 120L can be or include a silicide, such as TiSi, or another one of the silicides just described. In some embodiments, the liner layer 120L is or includes a conductive nitride, such as TiN, TiSiN, or the like. The liner layer 120L can be a multi-layer including one or more silicides and one or more conductive nitrides. The liner layer 120L can be formed on the exposed surface of the source / drain region 82, including the upper surface of the source / drain region 82 exposed by the pore 49V, the sidewalls of the source / drain region 82, and the bottom surface of the source / drain region 82. In Figure 11D In it, the liner layer 120L is depicted as being formed on the upper surface of the bottom dielectric layer 800A and on the sidewalls of the interlayer dielectric 130 directly above the bottom dielectric layer 800A. In some embodiments, the liner layer 120L does not exist on the bottom dielectric layer 800A or the interlayer dielectric 130, and / or has a different material composition compared to the upper surface of the source / drain region 82 on the bottom dielectric layer 800A and the interlayer dielectric 130. That is, the liner layer 120L can exist only on the exposed surface of the source / drain region 82 and can be in direct contact with the source / drain region 82. The liner layer 120L can be formed by one or more deposition operations such as PVD, CVD, ALD, or the like, and can be further formed, for example, by a suitable annealing operation when forming a silicide as just described. In some embodiments, the formation of the liner layer 120L is optional. That is, in some embodiments, the liner layer 120L does not exist.

[0138] In Figure 11F and Figure 11G In, corresponding to Figure 13 the operation 2400, after forming the liner layer 120L, a conductive core layer 120C is formed. The conductive core layer 120C can be a material different from the liner layer 120L, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. In some embodiments, the conductive core layer 120C is cobalt. In some embodiments, the conductive core layer 120C is deposited in the source / drain contact opening 120X by PVD, CVD, ALD, or the like. The conductive core layer 120C can inherit the shape of the source / drain contact opening 120X. The conductive core layer 120C can completely or partially fill the remaining portion of the source / drain contact opening 120X. For example, as depicted in Figure 11G In, the conductive core layer 120C can completely fill the pore 49V such that the conductive core layer 120C is in direct contact with the liner layer 120L (when present) in the pore 49V, or in direct contact with the bottom surface of the source / drain region 82 exposed by the pore 49V (for example, when the liner layer 120L is absent).

[0139] In some embodiments, a portion of the conductive core layer 120C in the pore 49V may partially fill the pore 49V. This situation is diagrammatically depicted in Figure 11H . In such embodiments, the conductive core layer 120C may not contact the bottom surface of the source / drain region 82 and / or the liner layer 120L, but may be separated from the bottom surface of the source / drain region 82 by the pore 49V. In some embodiments, a portion of the pore 49V may remain after depositing the conductive core layer 120C, and the conductive core layer 120C may directly contact the bottom surface of the source / drain region 82 and / or the liner layer 120L. This situation is diagrammatically depicted in Figure 11I . In some embodiments, the thickness of the conductive core layer 120C on the bottom surface of the source / drain region 82 and / or the liner layer 120L is in the range of about 1 nm to about 5 nm or more. The conductive core layer 120C that contacts the bottom surface of the source / drain region 82 and / or the liner layer 120L and has a thickness of more than about 1 nm is beneficial to reduce the parasitic resistance of the source / drain contact 120.

[0140] Figure 11J Illustrates a semiconductor device including a backside interconnect structure 802 according to various embodiments. For clarity of discussion, the front-side interconnect features are omitted from the view in Figure 11J . In some embodiments, after forming the front-side interconnect features, the substrate 110 is thinned or removed, and the fins 32 are thinned or removed. After thinning the substrate 110 and, if necessary, the fins 32, the backside interconnect structure 802 is formed. The first backside interlayer dielectric 810 may be formed on the backside of the semiconductor device. The materials and formation processes may be similar to those described with reference to the interlayer dielectric 130. Then, a first removal operation, such as an etching operation, may be performed to pattern the first backside interlayer dielectric 810 and, if necessary, the fins 32 to form a first opening that exposes one or more of the source / drain regions 82. A first backside via or contact 830 is formed in one of the openings and is electrically coupled to the backside of the source / drain region 82. In some embodiments, the first backside via 830 contacts the liner layer 120L, the conductive core layer 120C, or the source / drain region 82. The second backside interlayer dielectric 820 is formed on the first backside interlayer dielectric 810. The materials and formation processes may be similar to those described with reference to the interlayer dielectric 130. A second opening is formed in the second backside interlayer dielectric 820 by a second removal process, such as a second etching operation, that patterns the second backside interlayer dielectric 820. A first backside trace or wire 840 is formed in the second opening. Forming the first backside contact 830 is similar in many respects to forming the contact 120.

[0141] Figure 12 For Figure 10BCross-sectional side view illustration of region 170. The gate structure 200 is disposed respectively above and between channels 22A to 22C. The gate structure 200 may cover each of channels 22A to 22C. In some embodiments, the gate structure 200 is disposed above and between channels 22A to 22C, and these channels 22A to 22C may be silicon channels for N-type devices or silicon germanium channels for P-type devices, or may be silicon channels for both N-type devices and P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600, one or more work function tuning layers 900, and a metal fill layer 290.

[0142] The interface layer 210, which may be an oxide of the material of channels 22A to 22C, is formed on the exposed regions of channels 22A to 22C and on the top surface of fin 32. The interface layer 210 facilitates the adhesion of the gate dielectric layer 600 to channels 22A to 22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (A) to about 50 angstroms (A). In some embodiments, the interface layer 210 has a thickness of about 10 A. An interface layer 210 with an overly thin thickness may exhibit porosity or insufficient adhesion properties. An overly thick interface layer 210 consumes the gate fill window, which is related to threshold voltage tuning and resistance as described above. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage tuning.

[0143] The gate dielectric layer 600 may be formed on the interface layer 210. In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material with a high dielectric constant greater than that of silicon dioxide (k≈3.9). Exemplary high-k dielectric materials include HfO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO 2 、Ta 2 O 5 or a combination thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 A to about 100 A.

[0144] In some embodiments, the gate dielectric layer 600 may include dopants, such as metal ions driven from La 2 O 3 、MgO、Y 2 O 3 、TiO 2 、Al 2 O 3 、Nb 2 O 5 or the like into the high-k gate dielectric, or from B 2 O 3Boride ions are driven, and these ions are at a concentration to achieve threshold voltage tuning. As an example, for an N-type transistor device, a higher concentration of lanthanum ions reduces the threshold voltage relative to a layer having a lower concentration of lanthanum ions or no lanthanum ions, while the opposite is true for a P-type device. In some embodiments, the gate dielectric layer 600 of certain transistor devices (e.g., IO transistors) is free of dopants that are present in certain other transistor devices (e.g., N-type core logic transistors or P-type IO transistors). In an N-type IO transistor, for example, a relatively high threshold voltage is desired, such that for an IO transistor, a high-k dielectric layer is preferably free of lanthanum ions, which would otherwise reduce the threshold voltage.

[0145] In some embodiments, the gate structure 200 further includes one or more work function metal layers collectively denoted as the work function metal layer 900. When configured as an NFET, the work function metal layer 900 of the GAA device 20 may include at least one N-type work function metal layer, an in-situ capping layer, and an oxygen barrier layer. In some embodiments, the N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, or the like. The in-situ capping layer is formed on the N-type work function metal layer and may include TiN, TiSiN, TaN, or another suitable material. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which would cause an undesired shift in the threshold voltage. The oxygen barrier layer may be formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the work function metal layer 900 includes more or fewer layers than described.

[0146] The work function metal layer 900 may further include one or more barrier layers, the one or more barrier layers comprising a metal nitride such as TiN, WN, MoN, TaN, or the like. Each of the one or more barrier layers may have a thickness in the range of about 5 Å to about 20 Å. Including one or more barrier layers provides additional threshold voltage tuning flexibility. Generally, each additional barrier layer increases the threshold voltage. Thus, for NFETs, higher threshold voltage devices (e.g., IO transistor devices) may have at least one or two or more additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have fewer additional barrier layers or no additional barrier layers. For PFETs, higher threshold voltage devices (e.g., IO transistor devices) may have fewer additional barrier layers or no additional barrier layers, while lower threshold voltage devices (e.g., core logic transistor devices) may have at least one or two or more additional barrier layers. In the following discussion, the threshold voltage is described in terms of magnitude. As an example, NFET IO transistors and PFET IO transistors may have similar threshold voltages in terms of magnitude but opposite polarities, such as +1 volt for NFET IO transistors and -1 volt for PFET IO transistors. Thus, since each additional barrier layer increases the threshold voltage in absolute terms (e.g., +0.1 volt / layer), this increase gives an increase in the threshold voltage (magnitude) of NFET transistors and a decrease in the threshold voltage (magnitude) of PFET transistors.

[0147] The gate structure 200 also includes a metal fill layer 290. The metal fill layer 290 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. Between channels 22A to 22C, the metal fill layer 290 is surrounded in a circular form (in a cross-sectional view) by one or more work function metal layers 900, which are in turn surrounded in a circular form by a gate dielectric layer 600, which is surrounded in a circular form by an interface layer 210. The gate structure 200 may also include an adhesive layer formed between one or more work function layers 900 and the metal fill layer 290 to increase adhesion. The adhesive layer is not specifically shown in Figure 12 for simplicity. In some embodiments, a conductive layer is formed over the gate structure 200 and contacts the metal fill layer 290, one or more work function layers 900, and the gate dielectric layer 600. The conductive layer may include fluorine-free tungsten (FFW) or another suitable material. In some embodiments, a dielectric capping layer is present over the conductive layer.

[0148] Additional processing may be performed after fabricating the semiconductor device. For example, a gate contact electrically coupled to the gate structure 200 may be formed, and a source / drain via electrically coupled to the source / drain contact 120 may be formed. An interconnect structure (e.g., a "front-side interconnect structure") may then be formed over the source / drain contact 120 and the gate contact. The interconnect structure may include multiple interconnect layers, each of which may include one or more dielectric layers embedded with metal features such as conductive traces and conductive vias that form electrical connections between the devices of the IC wafer 10. In some embodiments, a conductive layer or a conductive cap is present over the gate structure 200. In some embodiments, a dielectric capping layer is present over the gate structure 200 and / or over the source / drain contact 120. A configuration where the dielectric capping layer is present only over the gate structure 200 (e.g., no second capping layer is present over the source / drain contact 120) may be referred to as a "single DAC" structure, and a configuration where the capping layer is present over both the gate structure 200 and the source / drain contact 120 may be referred to as a "dual SAC" structure.

[0149] Embodiments may provide several advantages. The source / drain contact 120 is formed to surround the source / drain region 82. The source / drain contact 120 surrounding the source / drain region 82 is beneficial to reduce parasitic resistance, which improves the duty cycle performance.

[0150] According to at least one embodiment, a method includes the steps of: forming a semiconductor nanostructure stack on a semiconductor fin; forming a source / drain opening adjacent to the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source / drain region in the source / drain opening, with a pore existing between the source / drain region and the bottom dielectric layer; forming a dielectric layer on the source / drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having a higher etch selectivity compared to other portions of the dielectric layer; removing the other portions of the dielectric layer to expose the pore; forming a source / drain contact opening that extends to and connects with the pore, the source / drain contact opening exposing multiple sidewalls of the source / drain region; forming a liner layer on the multiple exposed surfaces of the source / drain region; and forming a conductive core layer on the liner layer, the conductive core layer contacting the liner layer on a top surface, multiple sidewalls, and a top surface of the source / drain region. In some embodiments, the pore has a width in a range of about 10 nanometers to about 15 nanometers in a horizontal direction. In some embodiments, the pore has a height in a vertical direction, the height being in a range of about 10 nanometers to half the height of the source / drain region. In some embodiments, the step of forming a dielectric layer is the step of forming a dielectric nitride layer. In some embodiments, the step of forming a hardened portion includes the steps of: forming a top portion on an upper surface of the source / drain region and forming a bottom portion on the semiconductor fin. In some embodiments, the step of forming a conductive core layer includes the steps of: forming a conductive core layer in the pore, the conductive core layer including a second pore.

[0151] According to at least one embodiment, a method includes the steps of: forming a semiconductor nanosheet channel stack on a semiconductor fin; forming a source / drain opening adjacent to the stack; forming a source / drain region in the source / drain opening, with a void existing between the source / drain region and the semiconductor fin; forming a dielectric layer on the source / drain region and in the void; exposing the void by removing the dielectric layer on multiple sidewalls of the source / drain region and in multiple portions of the void; forming an interlayer dielectric on the source / drain region and the dielectric layer; forming a source / drain contact opening that extends through the interlayer dielectric and connects to the void, the source / drain contact opening exposing multiple sidewalls of the source / drain region; and forming a conductive core layer in contact with a top surface and multiple sidewalls of the source / drain region. In some embodiments, the void exists after the step of forming an interlayer dielectric. In some embodiments, the void extends from below a first height to a second height, the first height being flush with a bottom surface of a first semiconductor nanosheet channel of the stack closest to the semiconductor fin, and the second height being between a top surface of the first semiconductor nanosheet channel and an upper surface of a second semiconductor nanosheet channel of the stack above the first semiconductor nanosheet channel. In some embodiments, the step of forming a conductive core layer includes the step of: partially filling the void. In some embodiments, the conductive core layer is separated from a bottom surface of the source / drain region by an unfilled portion of the void. In some embodiments, a portion of the conductive core layer in contact with the bottom surface of the source / drain region has a thickness in a range of about 1 nanometer to about 5 nanometers. In some embodiments, the method further includes the step of: forming a backside via in contact with the conductive core layer.

[0152] According to at least one embodiment, a device includes: a semiconductor nanostructure stack; a source / drain region adjacent to the stack, the source / drain region having a top surface, a plurality of sidewalls, and a bottom surface; a bottom dielectric layer underlying the source / drain region; and a source / drain contact that contacts the top surface and the plurality of sidewalls of the source / drain region and is between an upper surface of the bottom dielectric layer and the source / drain contact. In some embodiments, the source / drain contact contacts the bottom surface of the source / drain region. In some embodiments, a thickness of a portion of the source / drain contact that contacts the bottom surface of the source / drain region is in a range of from about 1 nanometer to about 5 nanometers. In some embodiments, the source / drain contact and the bottom surface of the source / drain region are separated from each other by a void. In some embodiments, the source / drain contact includes: a liner layer and a conductive core layer on the liner layer, the liner layer being on the top surface, the sidewalls, and the bottom surface of the source / drain region. In some embodiments, the conductive core layer is separated from a portion of the liner layer on the bottom surface of the source / drain region by a void. In some embodiments, the device further includes an etch stop layer laterally adjacent to the bottom dielectric layer.

[0153] According to at least one embodiment, a semiconductor device includes a semiconductor nanostructure stack, a source / drain region adjacent to the semiconductor nanostructure stack, a bottom dielectric layer underlying the source / drain region, a liner layer, and a conductive core layer. The source / drain region has a top surface, a plurality of sidewalls, and a bottom surface. A void exists between the source / drain region and the bottom dielectric layer. The liner layer is located on the source / drain region. The conductive core layer is located on the liner layer, wherein the conductive core layer contacts the liner layer on the top surface, the sidewalls, and the bottom surface of the source / drain region. In some embodiments, the void has a width in a range of from about 10 nanometers to about 15 nanometers in a horizontal direction. In some embodiments, the void has a height in a vertical direction, the height being in a range of from 10 nanometers to half of the height of the source / drain region. In some embodiments, the semiconductor device further includes a dielectric layer located on the source / drain region, wherein the dielectric layer is a dielectric nitride layer.

[0154] According to at least one embodiment, a semiconductor device includes a semiconductor nanosheet channel stack, source / drain regions, a dielectric layer, an interlayer dielectric, and a conductive core layer. The semiconductor nanosheet channel stack is located on a semiconductor fin. The source / drain regions are adjacent to the semiconductor nanosheet channel stack, wherein voids exist between the source / drain regions and the semiconductor fin. The dielectric layer is on the source / drain regions and in the voids. The interlayer dielectric is on the source / drain regions and the dielectric layer. The conductive core layer contacts a top surface and a plurality of sidewalls of the source / drain regions. In some embodiments, the voids extend from below a first height to a second height, the first height being flush with a bottom surface of a first semiconductor nanosheet channel of the stack closest to the semiconductor fin, and the second height being between a top surface of the first semiconductor nanosheet channel and an upper surface of a second semiconductor nanosheet channel of the stack above the first semiconductor nanosheet channel. In some embodiments, the semiconductor device further includes a backside via that contacts the conductive core layer.

[0155] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be made herein without departing from the spirit and scope of the present disclosure by various changes, substitutions, and alterations.

Claims

1. A semiconductor device, characterized in that: Include: A semiconductor nanostructure stack; A source / drain region adjacent to the semiconductor nanostructure stack, wherein the source / drain region has a top surface, a plurality of sidewalls, and a bottom surface; a bottom dielectric layer underlying the source / drain region, wherein a void exists between the source / drain region and the bottom dielectric layer; a liner layer located on the source / drain region; and A conductive core layer is located on the liner layer, wherein the conductive core layer contacts the liner layer on the top surface, the plurality of sidewalls and the bottom surface of the source / drain region. 2 . The semiconductor device of claim 1 , wherein the aperture has a width in a horizontal direction in a range of 10 nm to 15 nm. 3 . The semiconductor device of claim 1 , wherein the aperture has a height in a vertical direction that is in a range from 10 nanometers to half the height of the source / drain region.

4. The semiconductor device according to claim 1, further comprising: A dielectric layer is located on the source / drain region, wherein the dielectric layer is a dielectric nitride layer.

5. A semiconductor device, characterized in that: Include: a semiconductor nanosheet channel stack located on a semiconductor fin; a source / drain region adjacent to the semiconductor nanosheet channel stack, wherein a void exists between the source / drain region and the semiconductor fin; a dielectric layer on the source / drain region and in the aperture; an interlayer dielectric on the source / drain region and the dielectric layer; and A conductive core layer contacts a top surface and a plurality of sidewalls of the source / drain region.

6. The semiconductor device of claim 5 , wherein the pore extends from below a first height to a second height, the first height being flush with a bottom surface of a first semiconductor nanosheet channel of the stack closest to the semiconductor fin, and the second height being between a top surface of the first semiconductor nanosheet channel and an upper surface of a second semiconductor nanosheet channel of the stack that is higher than the first semiconductor nanosheet channel.

7. The semiconductor device according to claim 5, further comprising: A back side through hole contacts the conductive core layer.

8. A semiconductor device, characterized in that: Include: A semiconductor nanostructure stack; A source / drain region adjacent to the semiconductor nanostructure stack, the source / drain region having a top surface, a plurality of sidewalls, and a bottom surface; a bottom dielectric layer underlying the source / drain region; and A source / drain contact contacts the top surface and the sidewalls of the source / drain region and is located between an upper surface of the bottom dielectric layer and the source / drain contact. 9 . The semiconductor device of claim 8 , wherein the source / drain contact contacts the bottom surface of the source / drain region. 10 . The semiconductor device of claim 8 , wherein a thickness of a portion of the source / drain contact in contact with the bottom surface of the source / drain region is in a range of 1 nm to 5 nm.

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