Sequential circuit, chip and electronic equipment
By introducing a delay branch in the timing circuit to delay the initial clock signal and increasing the duty cycle of the target clock signal, the problem of transmission delay pressure in the prior art is solved, and lower delay requirements and smaller design pressure are achieved.
Patent Information
- Application Number
- CN202421594184.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-05
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-07-05
AI Technical Summary
The existing timing circuits have pressure on transmission delay, making it difficult to reduce the delay requirement without increasing the circuit area and power consumption.
A timing circuit is designed, including a delay branch, an input branch and a clock generation module. Through the delay branch, the falling edge of the initial clock signal is delayed, thereby increasing the duty cycle of the target clock signal, thereby extending the allowable delay time.
By increasing the duty cycle of the target clock signal, the transmission delay requirement is reduced and the design pressure of related modules on the delay path is reduced.
Smart Images
Figure CN222916006U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technologies, and in particular, to a timing circuit, a chip, and an electronic device. Background Art
[0002] In the field of electronic technologies, clock signals are usually used in synchronous circuits to ensure the synchronous operation of relevant electronic components.
[0003] Common clock signals usually have a duty cycle of 50%, that is, the durations of the high level and the low level in the same cycle are the same. In some circuits, the rising edge of the clock signal can be used as the starting point of operation, and the input signal is processed and transmitted through relevant modules therein, and the processed signal is collected at the falling edge of the clock signal. For example, in the conversion path of an analog-to-digital conversion circuit, the input signal can be converted at the rising edge of the clock signal, and the output signal of the comparator can be collected at the falling edge of the clock signal. Therefore, it is necessary to ensure that the delay of the above relevant modules is less than half of the clock cycle (such as 12.5 nanoseconds), so as to ensure that the relevant modules complete their work before the falling edge of the clock signal arrives.
[0004] To reduce the transmission delay of relevant modules, it is usually possible to achieve this by increasing the area of electronic components and increasing the current. The larger the area of the electronic component, the faster the response speed, and the larger the current, the faster the transmission speed. Therefore, the delay can be reduced. However, the circuit area and power consumption also increase accordingly.
[0005] Therefore, there is an urgent need for a new timing circuit to form a new clock signal to reduce the requirement for transmission delay. Summary of the Utility Model
[0006] To solve the problems of the prior art, embodiments of this application provide a timing circuit, a chip, and an electronic device, which can reduce the requirement for transmission delay and reduce the design pressure of relevant modules on the delay path. The technical solutions are as follows:
[0007] According to one aspect of this application, a timing circuit is provided. The timing circuit includes a delay branch, an input branch, and a clock generation module;
[0008] The input end of the delay branch is used to receive an initial clock signal, and the output end of the delay branch is connected to the first input end of the clock generation module;
[0009] The input end of the input branch is used to receive the initial clock signal, and the output end of the input branch is connected to the second input end of the clock generation module;
[0010] The output end of the clock generation module is used to output a target clock signal;
[0011] Among them, the duty cycle of the target clock signal is greater than that of the initial clock signal.
[0012] According to another aspect of the present application, a chip is provided, including the above timing circuit.
[0013] According to another aspect of the present application, an electronic device is provided, including the above timing circuit.
[0014] In the present application, the timing circuit may include a delay branch, an input branch, and a clock generation module. Among them, the falling edge of the initial clock signal is delayed through the delay branch, so that the duty cycle of the target clock signal output by the clock generation module is increased, the allowable delay time is lengthened, the requirement for transmission delay is reduced, and thus the design pressure of the related modules on the delay path is reduced. Description of the Drawings
[0015] In the following description of the exemplary embodiments in conjunction with the drawings, more details, features, and advantages of the present application are disclosed. In the drawings:
[0016] Figure 1 A schematic diagram of a timing circuit provided according to an exemplary embodiment of the present application is shown;
[0017] Figure 2 A schematic diagram of a clock signal provided according to an exemplary embodiment of the present application is shown;
[0018] Figure 3 Another schematic diagram of a clock signal provided according to an exemplary embodiment of the present application is shown;
[0019] Figure 4 A schematic diagram of a first delay module provided according to an exemplary embodiment of the present application is shown;
[0020] Figure 5 A schematic diagram of the delay path of an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application is shown;
[0021] Figure 6 A schematic diagram of a timing circuit applied to an analog-to-digital conversion circuit provided according to an exemplary embodiment of the present application is shown;
[0022] Figure 7 A schematic diagram of a level conversion module provided according to an exemplary embodiment of the present application is shown;
[0023] Figure 8 A schematic diagram of a second delay module provided according to an exemplary embodiment of the present application is shown.
[0024] In the figure,
[0025] 1. Delay branch; 11. First delay module; 111. First delay sub-module; 12. Level conversion module; 13. Second delay module; 131. Second delay sub-module; 2. Input branch; 3. Clock generation module. Detailed implementation manners
[0026] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.
[0027] The term "including" and its variants used herein are open-ended, that is, "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts such as "first" and "second" mentioned in the present application are only used to distinguish different devices, modules or units, and are not used to limit the order of the functions executed by these devices, modules or units or their interdependent relationships.
[0028] It should be noted that the modifications of "one" and "multiple" mentioned in the present application are illustrative rather than restrictive. Those skilled in the art should understand that unless otherwise clearly stated in the context, it should be understood as "one or more".
[0029] The names of the messages or information exchanged between multiple devices in the embodiments of the present application are only for illustrative purposes and are not used to limit the scope of these messages or information.
[0030] An embodiment of the present application provides a timing circuit. The detection circuit provided in this embodiment can be integrated in a chip or disposed in an electronic device.
[0031] As Figure 1 shown in the schematic diagram of the timing circuit, the timing circuit may include a delay branch 1, an input branch 2, and a clock generation module 3.
[0032] The input end of the delay branch 1 can be used to receive an initial clock signal, and the output end of the delay branch 1 is connected to the first input end of the clock generation module 3;
[0033] The input end of the input branch 2 can be used to receive the above-mentioned initial clock signal, and the output end of the input branch 2 is connected to the second input end of the clock generation module 3;
[0034] The output terminal of the clock generation module 3 is used to output a target clock signal;
[0035] Among them, the duty cycle of the target clock signal is greater than that of the initial clock signal. The initial clock signal may refer to a general clock signal in a chip or an electronic device, and its duty cycle is usually 50%.
[0036] The implementation principle is as follows:
[0037] In a possible implementation manner, the initial clock signal can be input into the delay branch 1, and the falling edge in the initial clock signal is delayed by a certain duration (referred to as the first duration in this embodiment) through the delay branch 1 to output a first clock signal. As Figure 2 shown in the schematic diagram of the clock signal, the falling edge in the first clock signal is triggered at a new moment.
[0038] At the same time, the initial clock signal is connected to the input branch 2, and a second clock signal is output through the input branch 2. The rising edge of the second clock signal may be the same as the triggering moment of the rising edge in the initial clock signal, or the rising edge in the initial clock signal is delayed by a certain duration (referred to as the second duration in this embodiment) to trigger the rising edge at a new moment. Among them, the second duration is less than the above-mentioned first duration.
[0039] Furthermore, the clock generation module 3 can receive the above-mentioned first clock signal and second clock signal, combine the falling edge in the first clock signal and the rising edge in the second clock signal to form a new clock signal and output it, that is, the target clock signal. Among them, because the falling edge in the first clock signal is delayed for a long time, the duty cycle of the target clock signal is greater than that of the initial clock signal.
[0040] By increasing the duty cycle of the target clock signal, the allowed delay time is lengthened, the requirement for transmission delay is reduced, and thus the design pressure of the relevant modules on the delay path is reduced.
[0041] Optionally, the output terminal of the delay branch 1 can be used to output the delayed clock signal after delaying the initial clock signal, and the output terminal of the input branch 2 can be used to output the above-mentioned initial clock signal.
[0042] In a possible implementation manner, the delay branch 1 can delay the whole of the initial clock signal by a certain duration (i.e., the first duration) to output a delayed clock signal (i.e., a specific first clock signal), and the duty cycles of the delayed clock signal and the initial clock signal may be the same. It should be noted that the first duration at this time can be less than half of the clock period to ensure that the delayed falling edge is triggered before the rising edge before the delay in its next clock cycle (i.e., the rising edge in the next clock cycle of the initial clock signal), as Figure 3 shown.
[0043] The input branch 2 may directly output the initial clock signal (i.e., a specific second clock signal) without performing any processing on the initial clock signal.
[0044] Optionally, the clock generation module 3 may include an OR gate unit.
[0045] In a possible implementation, as Figure 3 shown in the schematic diagram of the clock signal, in the clock generation module 3, the first clock signal and the second clock signal may be ORed to output a target clock signal. When either of the two clock signals is at a high level, the clock generation module 3 may output a high-level voltage; when both are at a low level, the clock generation module 3 may output a low-level voltage. On this basis, taking one clock cycle of the initial clock signal as an example, the first triggered rising edge (i.e., the rising edge of the second clock signal of the input branch 2) and the last triggered falling edge (i.e., the falling edge of the first clock signal of the delay branch 1) may be retained, improving the duty cycle of the target clock signal.
[0046] Optionally, the target clock signal is used for a target circuit, and the target circuit may include at least one target delay module;
[0047] Referring to Figure 4 the schematic diagram of the first delay module shown, the delay branch 1 may include a first delay module 11, and the first delay module 11 includes at least one first delay sub-module 111, and the structure of the first delay sub-module 111 is the same as that of any target delay module.
[0048] In a possible implementation, the target delay module is a relevant module on the delay path in the target circuit. A first delay sub-module 111 with the same structure as the target delay module may be provided in the delay branch 1 as the first delay module 11, that is, the structure of the first delay sub-module 111 is the same as that of any target delay module. When there are multiple target delay modules in the target circuit, at least one target delay module may be copied to the delay branch 1, that is, the first delay module 11 may include at least one first delay sub-module 111.
[0049] When the first delay module 11 includes multiple first delay sub-modules 111, the multiple first delay sub-modules 111 may be connected in series.
[0050] Under the same PVT (Process, Voltage, Temperature) conditions, the delay of the first delay sub-module 111 and the target delay module with the same structure can generally be regarded as equal. Therefore, the first duration of the delay of delay branch 1 can be matched with the target delay module. The delay of the target delay module generally does not exceed half of the clock period, which can ensure that the first duration is less than half of the clock period. Moreover, when the delay of the target circuit changes with the change of PVT conditions, this first duration will also change with the change of PVT conditions in the same or similar trend, that is, a duty-cycle adaptive timing circuit is obtained.
[0051] Optionally, the target circuit may include an analog-to-digital conversion circuit, and the first delay sub-module 111 may include: a first level conversion delay sub-module, a second level conversion delay sub-module, and a digital domain logic delay sub-module;
[0052] Among them, the first level conversion delay module refers to the delay sub-module for converting from low level to high level, and the second level conversion delay module refers to the delay sub-module for converting from high level to low level.
[0053] As a specific example, referring to Figure 5 the schematic diagram of the delay path of the analog-to-digital conversion circuit shown, according to the execution timing sequence between modules, the delay path of the analog-to-digital conversion circuit may include a digital domain logic delay module in the 1.1V voltage domain, a first level conversion delay module for converting from 1.1V to 5V, a cdac switch array delay module and a cdac establishment delay module in the 5V domain, a comparator transmission delay module in the 3.3V domain, and a second level conversion delay module for converting from 3.3V to 1V.
[0054] Among them, the cdac switch array delay module and the cdac establishment delay module in the 5V domain are usually analog domain delay modules, and there is delay uncertainty in the circuit modules in the analog domain. If they are copied to delay branch 1, it may cause the falling edge after delay to be triggered after the rising edge before the delay in its next clock cycle (i.e., the rising edge in the next clock cycle of the initial clock signal), and the clock generation module 3 cannot form a correct target clock signal.
[0055] Therefore, the remaining digital domain delay modules can be copied to delay branch 1 as the first delay sub-module 111, that is, it includes a first level conversion delay sub-module (corresponding to the above first level conversion delay module for converting from 1.1V to 5V), a second level conversion delay sub-module (corresponding to the above second level conversion delay module for converting from 3.3V to 1V), and a digital domain logic delay sub-module (corresponding to the above digital domain logic delay module).
[0056] As a specific example, referring to Figure 6 FIG. A schematic diagram of a timing circuit applied to an analog-to-digital conversion circuit shown in can connect the digital domain logic delay sub-module and the first level conversion delay sub-module in series in delay branch 1, so that the falling edge of the first clock signal output by delay branch 1 (which is also the falling edge of the target clock signal) can adapt to the digital logic delay and level conversion delay under different PVT conditions, that is, this falling edge can be adaptively adjusted according to the actual situation of the analog-to-digital conversion circuit delay.
[0057] Optionally, referring to Figure 7 FIG. A schematic diagram of a level conversion module shown in, delay branch 1 may further include a level conversion module 12;
[0058] The input end of the first delay module 11 can be used to receive an initial clock signal;
[0059] The input end of the level conversion module 12 is connected to the output end of the first delay module 11, and the output end of the level conversion module 12 is connected to the first input end of the clock generation module 3.
[0060] In a possible implementation manner, if the output voltage of the first delay module 11 does not match the working voltage domain of the clock generation module 3, a level conversion module 12 can be set after the first delay module 11 to convert the output voltage of the first delay module 11 to the working voltage domain of the clock generation module 3. For example Figure 6 the output voltage of the first level conversion delay sub-module in is 5V domain. Assuming that the clock generation module 3 works in 1.1V domain, a level conversion module 12 that converts from 5V to 1.1V can be set after the first level conversion delay sub-module, so that the first clock signal output by delay branch 1 is in 1.1V domain.
[0061] Specifically, the level conversion module 12 may include an even number of inverters connected in series. The specific circuit of the level conversion module 12 is not limited in this embodiment.
[0062] Optionally, referring to Figure 8 FIG. A schematic diagram of a second delay module shown in, delay branch 1 may further include a second delay module 13. The second delay module 13 includes at least one second delay sub-module 131, and the second delay module 13 is different from the first delay module 11.
[0063] In a possible implementation manner, according to the actual needs of the circuit, a second delay module 13 can also be set in delay branch 1. The second delay module 13 can be independent of the delay path of the target circuit and is used to further extend the delay. When the second delay module 13 includes multiple second delay sub-modules 131, the multiple second delay sub-modules 131 can be connected in series.
[0064] Optionally, the second delay sub-module 131 may include a logic gate unit, which may include an AND gate, an OR gate, a NOT gate, etc. This embodiment does not limit the specific logic gate unit used.
[0065] Of course, the delay branch 1 may include a first delay module 11, a level conversion module 12, and a second delay module 13, and the first delay module 11, the level conversion module 12, and the second delay module 13 are connected in series. The level conversion module 12 may be disposed after the first delay module 11 and before the clock generation module 3. The second delay module 13 may be disposed at any position, such as before the first delay module 11, or after the level conversion module 12, or the logic gate units therein may be dispersedly disposed. This embodiment does not limit the specific setting manner of the second delay module 13.
[0066] The embodiments of the present application can achieve the following beneficial effects:
[0067] In the present application, the timing circuit may include a delay branch, an input branch, and a clock generation module. Among them, the falling edge of the initial clock signal is delayed through the delay branch, so that the duty cycle of the target clock signal output by the clock generation module is increased, the allowed delay time is lengthened, the requirement for transmission delay is reduced, and thus the design pressure on the relevant modules on the delay path is reduced.
[0068] An exemplary embodiment of the present application further provides a chip, including the timing circuit provided by the embodiments of the present application. The timing circuit may include a delay branch, an input branch, and a clock generation module. Among them, the falling edge of the initial clock signal is delayed through the delay branch, so that the duty cycle of the target clock signal output by the clock generation module is increased, the allowed delay time is lengthened, the requirement for transmission delay is reduced, and thus the design pressure on the relevant modules on the delay path of the chip is reduced.
[0069] An exemplary embodiment of the present application further provides an electronic device, including the timing circuit provided by the embodiments of the present application. The timing circuit may include a delay branch, an input branch, and a clock generation module. Among them, the falling edge of the initial clock signal is delayed through the delay branch, so that the duty cycle of the target clock signal output by the clock generation module is increased, the allowed delay time is lengthened, the requirement for transmission delay is reduced, and thus the design pressure on the relevant modules on the delay path of the electronic device is reduced.
Claims
1. A sequential circuit, characterized in that: The timing circuit includes a delay branch, an input branch and a clock generation module; The input end of the delay branch is used to receive the initial clock signal, and the output end of the delay branch is connected to the first input end of the clock generation module; The input end of the input branch is used to receive the initial clock signal, and the output end of the input branch is connected to the second input end of the clock generation module; The output end of the clock generation module is used to output the target clock signal; Wherein, the duty cycle of the target clock signal is greater than the duty cycle of the initial clock signal.
2. The sequential circuit according to claim 1, characterized in that: The output end of the delay branch is used to output a delayed clock signal after the initial clock signal is delayed, and the output end of the input branch is used to output the initial clock signal.
3. The sequential circuit according to claim 1, characterized in that: The target clock signal is used for a target circuit, and the target circuit includes at least one target delay module; The delay branch includes a first delay module, the first delay module includes at least one first delay submodule, and the structure of the first delay submodule is the same as that of any of the target delay modules.
4. The sequential circuit according to claim 3, characterized in that: The target circuit includes an analog-to-digital conversion circuit, and the first delay submodule includes: a first level conversion delay submodule, a second level conversion delay submodule, and a digital domain logic delay submodule; The first level conversion delay submodule refers to a delay submodule for converting from a low level to a high level, and the second level conversion delay submodule refers to a delay submodule for converting from a high level to a low level.
5. The sequential circuit according to claim 3, characterized in that: The delay branch also includes a level conversion module; The input end of the first delay module is used to receive the initial clock signal; The input end of the level conversion module is connected to the output end of the first delay module, and the output end of the level conversion module is connected to the first input end of the clock generation module.
6. The sequential circuit according to claim 3, characterized in that: The delay branch further includes a second delay module, the second delay module includes at least one second delay submodule, and the second delay module is different from the first delay module.
7. The sequential circuit according to claim 6, characterized in that: The second delay submodule includes a logic gate unit.
8. The sequential circuit according to claim 1, characterized in that: The clock generation module includes an OR gate unit.
9. A chip, characterized in that: The method comprises a sequential circuit as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that: The method comprises a sequential circuit as claimed in any one of claims 1 to 8.