Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a channel member. The semiconductor device includes a gate dielectric feature alongside the channel feature in a first cross-sectional side view. The first cross-sectional side view is defined by a vertical direction and a first horizontal direction. The semiconductor device includes a gate electrode member. In the first cross-sectional side view, the gate dielectric member surrounds a top surface of the gate electrode member, a bottom surface of the gate electrode member, a first side surface of the gate electrode member, and a second side surface of the gate electrode member opposite the first side surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a vertical gate-all-around (GAA) device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design of integrated circuits (ICs) have created generations of integrated circuits, each with smaller and more complex circuits than the previous generation. Over the course of integrated circuit evolution, functional density (e.g., the number of interconnected devices per unit chip area) has generally increased, accompanied by a reduction in geometry (meaning the size of the smallest component (or line) that can be formed using a process). Such a process of geometry reduction generally brings the benefits of increased production efficiency and reduced associated costs.

[0003] However, such geometric size reduction also increases the complexity of integrated circuit processing and manufacturing. For example, the reduction of integrated circuit devices may be limited by factors such as short channel effects, time-dependent dielectric breakdown, or parasitic resistance. As a result, the performance and / or yield of existing integrated circuit devices have not been optimized. Therefore, although existing integrated circuit devices and their manufacturing methods are generally adequate for their intended purposes, they are not completely satisfactory in all aspects. Summary of the invention

[0004] Some embodiments of the utility model provide a semiconductor device. The semiconductor device includes a channel component. The semiconductor device includes a gate dielectric component located next to the channel component in a first cross-sectional side view. The first cross-sectional side view is defined by a vertical direction and a first horizontal direction. The semiconductor device includes a gate electrode component. In the first cross-sectional side view, the gate dielectric component surrounds a top surface of the gate electrode component, a bottom surface of the gate electrode component, a first side surface of the gate electrode component, and a second side surface of the gate electrode component opposite to the first side surface.

[0005] In one embodiment, in the first cross-sectional side view, the gate dielectric component surrounds the gate electrode component 360 degrees; and

[0006] In a second cross-sectional side view defined by the vertical direction and a second horizontal direction perpendicular to the first horizontal direction, the gate electrode component is surrounded by the gate dielectric component at an angle less than 360 degrees.

[0007] In one embodiment, a gate contact is further included, wherein in the second cross-sectional side view:

[0008] The gate dielectric component is in direct contact with the top surface, the bottom surface, and the first side surface of the gate electrode component, but is not in direct contact with the second side surface of the gate electrode component; and

[0009] The gate contact is in direct contact with the second side surface of the gate electrode part.

[0010] In one embodiment, an interface layer is further included, and the interface layer is disposed between the channel component and the gate dielectric component in the first horizontal direction.

[0011] In one embodiment, it further includes:

[0012] a first source / drain component disposed above the channel component in the vertical direction in the first cross-sectional side view;

[0013] a second source / drain feature disposed below the channel feature in the vertical direction in the first cross-sectional side view;

[0014] a first spacer member disposed above the gate dielectric member in the vertical direction in the first cross-sectional side view; and

[0015] A second spacer feature is disposed below the gate dielectric feature in the vertical direction in the first cross-sectional side view.

[0016] In one embodiment, in the first cross-sectional side view, a side surface of the gate dielectric component protrudes beyond a side surface of the first spacer component or a side surface of the second spacer component in the first horizontal direction.

[0017] In one embodiment, it further includes:

[0018] a third spacer component disposed above the first spacer component in the vertical direction in the first cross-sectional side view;

[0019] a dummy material disposed below the second spacer component in the vertical direction in the first cross-sectional side view; and

[0020] a dielectric member directly contacting side surfaces of the first spacer member, the second spacer member, the third spacer member, the dummy material, and the gate dielectric member,

[0021] in:

[0022] The first source / drain component includes a first portion and a second portion;

[0023] The first portion is in direct contact with a side surface of the first spacer member; and

[0024] The second portion is in direct contact with a side surface of the third spacer member.

[0025] In one embodiment, wherein:

[0026] The semiconductor device includes a vertical gate all around (GAA) transistor;

[0027] The channel feature includes a nanostructure channel of the vertical gate all around (GAA) transistor; and

[0028] The channel feature has a larger dimension in the vertical direction than a combination of the gate electrode feature and the gate dielectric feature.

[0029] Some embodiments of the present invention further provide a semiconductor device. The semiconductor device includes a channel component. The semiconductor device includes a first source / drain component, and in a first cross-sectional side view defined by a vertical direction and a first horizontal direction, the first source / drain component is arranged above the channel component. The semiconductor device includes a second source / drain component, which is arranged below the channel component in the first cross-sectional side view. The semiconductor device includes a gate structure, which is arranged next to the channel component in the first cross-sectional side view, wherein the gate structure includes a gate dielectric component and a metal-containing gate electrode component. In the first cross-sectional side view, the metal-containing gate electrode component is surrounded 360 degrees by the gate dielectric component.

[0030] In one embodiment, wherein in a second cross-sectional side view defined by the vertical direction and a second horizontal direction perpendicular to the first horizontal direction, the metal-containing gate electrode component is surrounded by the gate dielectric component in a manner less than 360 degrees; or

[0031] The gate structure further includes an interface layer, and in the first cross-sectional side view, the interface layer is disposed between the gate dielectric component and the channel component, and the semiconductor device further includes:

[0032] A first spacer is disposed above the gate structure in the first cross-sectional side view; and

[0033] A second spacer is disposed below the gate structure in the first cross-sectional side view;

[0034] The gate structure protrudes laterally beyond the first spacer or the second spacer in the first horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The content of the embodiments of the present invention can be better understood through the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0036] Figure 1A-4A , Figure 5-14 , Figures 15A-17A , Figure 18-Figure 25 A series of three-dimensional perspective views of an integrated circuit (IC) device at various stages of fabrication are shown in accordance with an embodiment of the present disclosure.

[0037] Figure 1B-4B and Figures 15B-17B A series of cross-sectional side views of an integrated circuit (IC) device at various stages of fabrication are shown in accordance with an embodiment of the present disclosure.

[0038] Fig.26 and Fig. 27 Different cross-sectional side views of portions of integrated circuit (IC) devices are shown according to various aspects of embodiments of the present disclosure.

[0039] Fig.28 A flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0040] Fig.29 An integrated circuit manufacturing system according to various aspects of the present disclosure is shown.

[0041] Description of reference numerals:

[0042] 100: Integrated Circuit (IC) Devices

[0043] 100A, 100B: vertical stacking

[0044] 110: Base

[0045] 110A: Active area

[0046] 120,140: Semiconductor layer

[0047] 125,135,145,215,216: thickness

[0048] 130: Channel layer

[0049] 150: Patterning process

[0050] 160,450: Hard mask

[0051] 170: Spacer

[0052] 180,320,410: Open

[0053] 200: Spacer formation process

[0054] 210: Top spacer

[0055] 211: Bottom spacer

[0056] 230: Channel finishing process

[0057] 240,241,330,331,350,490,510,810: Grooves

[0058] 245: vertical size

[0059] 250: Virtual material formation process

[0060] 260: Void Materials

[0061] 280: STI and Helmet Forming Process

[0062] 290,390: STI structure

[0063] 300: Helmet structure

[0064] 310: End cutting process

[0065] 325,340: End recessing process

[0066] 360: End spacer formation process

[0067] 370: end spacers

[0068] 380: Liner and STI formation process

[0069] 385: Lining

[0070] 400: Etching process

[0071] 430: Source / drain formation process

[0072] 440,840: Source / Drain components

[0073] 440A, 840A: Lightly doped source / drain section (component)

[0074] 440B, 840B: Heavily doped source / drain parts (components)

[0075] 460: STI recess process

[0076] 470: STI groove

[0077] 480: Channel finishing process

[0078] 500: Virtual material removal process

[0079] 530: Gate Formation Process

[0080] 540: Gate structure

[0081] 550: Gate dielectric layer

[0082] 560: Gate electrode

[0083] 560A: Top surface of gate electrode

[0084] 560B: Bottom surface of gate electrode

[0085] 570: Interface layer

[0086] 590: Contact Etch Stop Layer and Interlayer Dielectric Formation Process

[0087] 600: Contact Etch Stop Layer

[0088] 610,630,760,761: Interlayer dielectric

[0089] 620: Gate contact opening formation process

[0090] 640: Gate contact opening

[0091] 650: Contact Etch Stop Layer Trimming Process

[0092] 670: Gate contact formation process

[0093] 680: Gate contact

[0094] 700: Source / drain pad formation process

[0095] 710,850 Silicide layer

[0096] 720,860: Source / drain pads

[0097] 740: Metallization process

[0098] 750,751: Etch stop layer

[0099] 770: Source / Drain Contacts

[0100] 780: Source / Drain Vias

[0101] 790: Gate vias

[0102] 800: De-platforming technology

[0103] 820: Source / drain formation process

[0104] 880: Surface

[0105] 890: Side surface

[0106] 900,930: Distance

[0107] 910: Horizontal size

[0108] 920: vertical size

[0109] A-A', B-B': tangent

[0110] 1000: Methods

[0111] 1010,1020,1030,1040,1050: Step 1100: Manufacturing system

[0112] 1102,1104,1106,1108,1110,1112,1114,1116,N: Entity

[0113] 1118: Communication Network DETAILED DESCRIPTION

[0114] The following content provides many different embodiments or examples for implementing different components of the embodiments of the utility model. Specific examples of components and configurations are described below to simplify the embodiments of the utility model. Of course, these are merely examples and are not intended to limit the embodiments of the utility model. For example, if the description mentions that a first component is formed on or located on a second component, it may include an embodiment in which the first and second components are in direct contact, and it may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the utility model may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0115] In addition, spatially relative terms such as "under," "below," "lower," "above," "upper," and other similar terms may be used herein to describe the relationship between an element or component as shown in the figure and other elements or components. Such spatially relative terms include not only the orientation shown in the drawings, but also different orientations of the device in use or operation. The device can be rotated arbitrarily (e.g., rotated 90 degrees or to other orientations), and the spatially relative descriptions used herein can also be interpreted based on the rotated orientation.

[0116] Furthermore, when "about", "approximately", or similar terms are used to describe a number or a numerical range, unless otherwise specified, as can be understood by those skilled in the art, such terms are used to indicate a numerical range that includes such numerical value and a difference of ±10% from such numerical value. For example, the term "about 5 nanometers" includes a size range of 4.5 nanometers to 5.5 nanometers.

[0117] The present disclosure generally relates to forming a vertical gate-all-around (GAA) device. More specifically, a GAA device is a multi-channel transistor device in which the channels are implemented by extended nanostructures, such as nano-bars, nano-sheets, nano-tubes, or nanowires. GAA devices have various performance enhancements compared to conventional planar transistors, or compared to other forms of three-dimensional transistors such as FinFETs having semiconductor fins protruding vertically from a substrate. As a result, GAA devices have become increasingly common in recent years.

[0118] However, GAA devices and / or their manufacturing may also encounter various challenges. For example, in a horizontal type of GAA device (hereinafter referred to as a horizontal GAA), the reduction in the size of integrated circuit (IC) components may be limited by factors such as short channel effects, gate-to-contact time-dependent dielectric breakdown (TDDB) and / or parasitic contact resistance. A vertical type of GAA device (hereinafter referred to as a vertical GAA) can improve some of the problems associated with horizontal GAA devices. However, vertical GAA devices may be affected by inappropriate variations in spacer thickness and / or gate length. This is because the spacer thickness and gate length are defined by the combined results of deposition and etch-back processes, which may be difficult to control accurately, especially as the size of integrated circuit (IC) devices continues to shrink.

[0119] In order to solve the above problems, the utility model relates to a vertical all-around gate (GAA) device, wherein the thickness of the top spacer and the bottom spacer and the gate length are controlled by the channel epitaxial deposition of silicon / silicon germanium and the subsequent silicon germanium recess and spacer deposition process. These processes can more accurately control the thickness of the top spacer and the bottom spacer and the gate length of the vertical all-around gate (GAA) device of the present invention, thereby improving the performance and / or yield of the vertical all-around gate (GAA) device of the present invention.

[0120] Figure 1A-Figure 25 A series of three-dimensional perspective views of an integrated circuit (IC) device 100 (herein a vertical all-around gate (GAA) device as an example) at various stages of manufacture according to an embodiment of the present disclosure are shown. To provide further clarity, Figure 1B-4B and Figures 15B-17B It also shows the corresponding Figure 1A-4A and Figures 15A-17A A series of cross-sectional side views of an integrated circuit (IC) device 100 at various stages of manufacture. Figure 1B-4B and Figures 15B-17B It is a horizontal span Figure 1A-4A and Figures 15A-17A A cross-sectional side view taken along a line A-A' in the X direction. Therefore, Figure 1A-4A and Figures 15A-17A Can also be viewed as X-cut views.

[0121] Now refer to Figure 1A and 1B, the integrated circuit (IC) device 100 includes a substrate 110. The substrate 110 may include an element (single element) semiconductor, such as silicon (Si) in the illustrated embodiment. In some other embodiments, the substrate 110 may include other semiconductor materials such as germanium, and / or compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials. In other embodiments, the substrate 110 may include an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. In the illustrated embodiment, the substrate 110 includes a single layer of material having a uniform composition. Alternatively, the substrate 110 may include a plurality of material layers having similar or different compositions suitable for use in the manufacture of integrated circuit (IC) devices. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed above a silicon oxide layer. In another example, the substrate 110 may further include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination of the foregoing layers.

[0122] A semiconductor layer 120 is formed above the substrate 110. In some embodiments, the semiconductor layer 120 has a different material composition than the substrate 110. For example, in an embodiment where the substrate 110 has a silicon material composition, the semiconductor layer 120 has a silicon germanium (SiGe) material composition. In some embodiments, the semiconductor layer 120 is formed by a deposition process, such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or a combination of the foregoing processes. The deposition process parameters can be adjusted to ensure that the thickness 125 (measured in the vertical Z direction) of the semiconductor layer 120 can achieve a specific range of values. In some embodiments, the thickness 125 is in a range between about 3 nanometers (nm) and about 15 nanometers (nm). As will be discussed in more detail below, the value of the thickness 125 is specifically configured herein to define the thickness of the bottom spacer to be formed later.

[0123] The channel layer 130 is formed over the semiconductor layer 120. In some embodiments, the channel layer 130 has a different material composition than the semiconductor layer 120, but it may have the same material composition as the substrate 110. For example, in an embodiment where the substrate 110 has a silicon material composition and the semiconductor layer 120 has a silicon germanium (SiGe) material composition, the channel layer 130 has a silicon material composition. In some embodiments, the channel layer 130 is formed by a deposition process, such as ALD, CVD, PVD, or a combination thereof. The deposition process parameters may be adjusted to ensure that the thickness 135 (measured in the vertical Z direction) of the channel layer 130 may achieve a specific range of values. In some embodiments, the thickness 135 is in a range between about 5 nm and about 15 nm. The value of the thickness 135 is configured to be large enough to provide sufficient spacing between the semiconductor layer 120 and the semiconductor layer 140 so that a metal-containing gate structure may be formed therebetween in a subsequent manufacturing step. At the same time, the value of the thickness 135 is also configured to be small enough to avoid excessively increasing the size of the integrated circuit (IC) device 100.

[0124] The semiconductor layer 140 is formed above the channel layer 130. In some embodiments, the semiconductor layer 140 has a different material composition than the channel layer 130, but may have the same material composition as the semiconductor layer 120. For example, in an embodiment where the channel layer 130 has a Si material composition and the semiconductor layer 120 has a SiGe material composition, the semiconductor layer 140 also has a SiGe material composition. In some embodiments, the semiconductor layer 140 is formed by a deposition process, such as ALD, CVD, PVD, or a combination thereof. The deposition process parameters may be adjusted to ensure that the thickness 145 (measured in the vertical Z direction) of the semiconductor layer 140 can achieve a specific range of values. In some embodiments, the thickness 145 is in a range between about 3 nm and about 15 nm. As will be discussed in more detail below, the value of the thickness 145 is specifically configured herein to define the thickness of the top spacer to be formed later.

[0125] Now refer to Figure 2A and Figure 2B, a patterning process 150 is performed on the integrated circuit (IC) device 100 to pattern the integrated circuit (IC) device into a plurality of vertically protruding structures. As part of the patterning process 150, a plurality of hard masks 160 and spacers 170 are formed above the semiconductor layer 140. The spacers 170 are formed on the sidewalls of the hard masks 160. The hard masks 160 and the spacers 170 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. However, it should be understood that the material compositions of the hard masks 160 and the spacers 170 may be different from each other.

[0126] Using the hard mask 160 and the spacer 170 as a protective etching mask, one or more etching processes can be performed to etch the semiconductor layer 140, the channel layer 130, the semiconductor layer 120 and a portion of the substrate 110. Portions of the semiconductor layer 140, the channel layer 130, the semiconductor layer 120 and the substrate 110 that are not protected by the hard mask 160 and the spacer 170 are etched away. The remaining portions form vertical protruding structures separated by openings 180. The openings 180 extend vertically downward in the Z direction and extend horizontally in the Y direction. Note that the portions of the substrate 110 separated by the openings 180 can be considered as active regions 110A. In other words, the active regions 110A are portions of the substrate 110 that protrude vertically out of the substrate 110 along the Z direction.

[0127] Now refer to Figure 3A and Figure 3B , a spacer formation process 200 is performed on the integrated circuit (IC) device 100 to form a plurality of top spacers 210 and a plurality of bottom spacers 211. In more detail, the spacer formation process 200 includes one or more etching processes, such as a wet etching process or a dry etching process. The etching process is configured to have sufficient etching selectivity to etch away a portion of the semiconductor layer 140 and a portion of the semiconductor layer 120 laterally (e.g., along the X direction) without substantially affecting the spacer 170 or the hard mask 160, so that lateral recesses can be formed in the semiconductor layer 140 and the semiconductor layer 120. A portion of the semiconductor layer 140 and a portion of the semiconductor layer 120 are still retained after the etching process.

[0128] Note that due to the similar material composition between the channel layer 130 and the semiconductor layer 140 and the semiconductor layer 120 (e.g., Si and SiGe), the etching selectivity between them may be low. In this way, the etching process may also partially remove the channel layer 130 near the portion of the semiconductor layer 140 and the semiconductor layer 120. In other words, the lateral groove formed in the semiconductor layer 140 and the semiconductor layer 120 may have a slightly larger vertical dimension in the Z direction than the semiconductor layer 140 and the semiconductor layer 120 itself. Alternatively, the relatively low etching selectivity between the channel layer 130 and the semiconductor layer 140 and the semiconductor layer 120 may result in incomplete removal of the semiconductor layer 140 and the semiconductor layer 120, so that the lateral groove formed in the semiconductor layer 140 and the semiconductor layer 120 may actually have a shorter vertical dimension in the Z direction than the semiconductor layer 140 and the semiconductor layer 120.

[0129] Regardless of how the lateral grooves are etched, the spacer formation process 200 also includes one or more deposition processes to deposit a dielectric material (e.g., SiN, SiCN, SiOC, or SiOCN) to fill the subsequent lateral grooves in the semiconductor layer 120 and the semiconductor layer 140. Therefore, the top spacer 210 is formed by the dielectric material filling the lateral groove in the semiconductor layer 140, and the bottom spacer 211 is formed by the dielectric material filling the lateral groove in the semiconductor layer 120. The top spacer 210 is also disposed above the channel layer 130, and the bottom spacer 211 is also disposed below the channel layer 130.

[0130] like Figure 3A and Figure 3B As shown, each top spacer 210 is formed to have a thickness 215 measured in the vertical Z direction, and each bottom spacer 211 is formed to have a thickness 216 measured in the vertical Z direction. According to various aspects of the present disclosure, the thickness 215 is equal to the thickness 145 of the semiconductor layer 140 (see Figure 1A-1B ) is related to (or is set in part by) the thickness 145 of the semiconductor layer 140, and the thickness 216 is related to the thickness 125 of the semiconductor layer 120 (see Figure 1A-1B), (or set in part by the thickness 125 of the semiconductor layer 120). This is because the thickness 215 and the thickness 216 (of the top spacer 210 and the bottom spacer 211) directly correspond to the vertical dimension of the lateral recess etched into the semiconductor layer 140 and the semiconductor layer 120. Therefore, the larger the thickness 145 and 125 initially configured for the semiconductor layer 140 and the semiconductor layer 120, the larger the vertical dimension of the lateral recess etched into the semiconductor layer 140 and the semiconductor layer 120, and the larger the thickness 215 of the top spacer 210 and the thickness 216 of the bottom spacer 211. Conversely, the smaller the thickness 145 and 125 initially configured for the semiconductor layer 140 and the semiconductor layer 120, the smaller the vertical dimension of the lateral recess etched into the semiconductor layer 140 and the semiconductor layer 120, and the smaller the thickness 215 of the top spacer and the thickness 216 of the bottom spacer 211. The fact that the thickness 215 and the thickness 216 are indirectly set by the thickness 145 of the semiconductor layer 140 and the thickness 125 of the semiconductor layer 120 is one of the distinguishing aspects of the present disclosure, and is an inherent result of the unique process flow herein. The top spacer 210 and the bottom spacer 211 can achieve a higher precision of the thickness 215 and the thickness 216 compared to other embodiments of a vertical gate-all-around (GAA) device, which can improve device performance, such as, but not limited to, uniformity between multiple devices.

[0131] Note that although thickness 215 and thickness 216 are indirectly determined by thickness 145 of semiconductor layer 140 and thickness 125 of semiconductor layer 120, they may be different from each other. For example, since the lateral etching process may partially remove portions of channel layer 130, the resulting lateral groove may be slightly longer than thickness 145 and thickness 125 in the vertical Z direction (e.g., the lateral groove in the illustrated embodiment). Therefore, in some embodiments, thickness 215 and thickness 216 may be slightly greater than thickness 145 and thickness 125. Alternatively, the lateral etching process may not completely remove portions of semiconductor layer 140 and semiconductor layer 120, which means that the resulting lateral groove may be slightly shorter than thickness 145 and thickness 125 in the vertical Z direction. In some embodiments, a difference between thickness 215 and thickness 145 can be in a range between about +0.5 nanometers and about -0.5 nanometers, a ratio between thickness 215 and thickness 145 can be in a range between about 1 and about 2, a difference between thickness 216 and thickness 125 can be in a range between about +0.5 nanometers and about -0.5 nanometers, and a ratio between thickness 216 and thickness 125 can be in a range between about 1 and about 2.

[0132] Regardless of the specific values ​​of the above ratio ranges, the fact is that they are still close to 1:1, which means that the thickness 215 of the top spacer 210 and the thickness 216 of the bottom spacer 211 are still mostly the same. It is set by the thickness 145 of the semiconductor layer 140 and the thickness 125 of the semiconductor layer 120. Since the values ​​of the thickness 145 of the semiconductor layer 140 and the thickness 125 of the semiconductor layer 120 can be finely controlled, the values ​​of the thickness 215 of the top spacer 210 and the thickness 216 of the bottom spacer 211 can also be finely controlled.

[0133] Now refer to Figure 4A and Figure 4B , a channel trimming process 230 is performed on the integrated circuit (IC) device 100 to form a plurality of recesses 240. In more detail, the channel trimming process 230 includes one or more etching processes to partially remove the channel layer 130 and the active area 110A. The etching process is configured to have sufficient etching selectivity between the channel layer 130 and the active area 110A and the spacer 170, the top spacer 210, and the bottom spacer 211. In other words, the channel layer 130 and the active area 110A are etched at a significantly faster etching rate, while the spacer 170, the top spacer 210, and the bottom spacer 211 are etched at a significantly slower etching rate. As a result, a plurality of recesses 240 may be formed, wherein the sidewalls of the channel layer 130 define the side surfaces of each recess 240, and the bottom surface of the top spacer 210 and the top surface of the bottom spacer 211 define the top surface and the bottom surface of each recess 240. Note that the etching process also forms a groove 241 below the groove 240. Each groove 240 and groove 241 extends laterally in the X direction toward the channel layer 130 (or toward the active area 110A). The grooves 240 and grooves 241 also extend in the Y direction.

[0134] like Figure 4A and Figure 4B As shown, each of the grooves 240 has a vertical dimension 245 measured along the Z direction. The vertical dimension 245 is proportional to the thickness 135 of the channel layer 130 (see Figure 1A and Figure 1B ). In other words, the larger the thickness 135, the larger the vertical dimension 245, and vice versa. In some embodiments, the ratio between the vertical dimension 245 and the thickness 135 can be in the range between about 0.6 and about 1. As will be discussed in more detail below, a metal-containing gate structure will be formed in each recess 240. Therefore, it can be said that the present disclosure is based on the previous Figure 1A and Figure 1BThe thickness 135 of the channel layer 130 is carefully configured during the deposition process performed in order to define the dimensions of the gate structure (eg, gate height). This is another unique aspect of the flow of the manufacturing process according to the present disclosure.

[0135] Now refer to Figure 5 , a dummy material formation process 250 is performed on the integrated circuit (IC) device 100 to form a dummy material 260 to fill the groove 240 and the groove 241. For example, one or more deposition processes may be performed to deposit the dummy material 260. The dummy material 260 may be a material that is easily removed and / or a material that is configured to have an etching selectivity with other components of the integrated circuit (IC) device 100. In some embodiments, the dummy material 260 may be a dielectric material, such as a nitride material. In other embodiments, the dummy material 260 may be a semiconductor material, such as a SiGe material.

[0136] Now refer to Figure 6 , an STI and helmet formation process 280 may be performed to form STI structures 290 and helmet structures 300. The STI structure 290 may be formed by depositing a dielectric material, such as silicon oxide, to fill the opening 180. The dielectric material is also deposited on the sidewalls of the spacer 170, the top spacer 210, the dummy material 260, and the bottom spacer 211. The helmet structure 300 may be formed by partially etching the STI structure 290 to form grooves, and then filling these grooves with another type of dielectric material that is more etch-resistant than the STI structure 290. In some embodiments, the helmet structure 300 may include silicon nitride. It should be understood that the STI and helmet formation process 280 may also include a planarization process (e.g., a chemical mechanical planarization (CMP) process) to planarize the upper surfaces of the helmet structure 300, the spacer 170, and the hard mask 160.

[0137] Now refer to Figure 7 , an end cutting process 310 is performed on the integrated circuit (IC) device 100 to form an opening 320. For example, the end cutting process 310 may include one or more patterning and etching processes to selectively remove material from various components of the integrated circuit (IC) device 100 until the substrate 110 is reached. The formed opening 320 extends vertically downward in the Z direction and horizontally in the X direction. The opening 320 separates the integrated circuit (IC) device 100 into two vertical stacks 100A and 100B.

[0138] Now refer to Figure 8, an end recess process 325 is performed on the integrated circuit (IC) device 100 to form a plurality of lateral recesses 330 and lateral recesses 331. In more detail, the end recess process 325 may include one or more etching processes to selectively remove a portion of the semiconductor layer 140 and a portion of the semiconductor layer 120. The etching process is configured to have sufficient etching selectivity between the materials of the semiconductor layer 140 and the semiconductor layer 120 and other components of the integrated circuit (IC) device 100. For example, the etching rate of the materials of the semiconductor layer 140 and the semiconductor layer 120 (e.g., SiGe) is significantly faster than the etching rate of the active area 110A, the channel layer 130, the top spacer 210, the bottom spacer 211, the hard mask 160, the spacer 170, and the STI structure 290. Therefore, the lateral recess 330 is formed at the location of the partially removed semiconductor layer 140, and the lateral recess 331 is formed at the location of the partially removed semiconductor layer 120.

[0139] Note that the lateral grooves 330 and 331 extend horizontally in the Y direction from the opening 320 into the vertical stacks 100A and 100B. Figure 8 The three-dimensional perspective view is shown in such a way that the transverse grooves 330 and 331 in the vertical stack 100B can be clearly shown, but the corresponding transverse grooves 330 and 331 in the vertical stack 100A are not shown. Figure 8 is not directly visible.

[0140] Now refer to Fig. 9 , an end recessing process 340 is performed on the integrated circuit (IC) device 100 to form a plurality of lateral grooves 350. In more detail, the end recessing process 340 may include one or more etching processes to selectively remove portions of the hard mask 160. The etching process is configured to have sufficient etching selectivity between the material of the hard mask 160 and other components of the integrated circuit (IC) device 100. For example, the material of the hard mask 160 is etched away at a much faster rate than the remaining components of the integrated circuit (IC) device 100. Therefore, lateral grooves 350 are formed at locations where the hard mask 160 is partially removed. Each lateral groove 350 extends vertically in the Z direction and horizontally in the Y direction. The lateral grooves 350 are also connected to the previously formed lateral grooves 330.

[0141] Now refer to Fig.10, an end spacer formation process 360 is performed on the integrated circuit (IC) device 100 to form end spacers 370 in the lateral grooves 330, 331 and 350. For example, the end spacer formation process 360 includes one or more deposition processes, in which a dielectric material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) is deposited into the lateral grooves 330, 331 and 350 to form the end spacers 370.

[0142] Now refer to Fig.11 , a liner and STI formation process 380 is performed on the integrated circuit (IC) device 100 to form a liner 385 and another STI structure 390. In more detail, a deposition process can be performed as part of the liner and STI formation process 380 to deposit a liner in the opening 320. The liner 385 is formed on the upper surface of the substrate 110 and the side surfaces of the STI structure 290, the helmet structure 300, and the end spacer 370. In some embodiments, the liner 385 includes a nitride material, such as silicon nitride. Thereafter, another deposition process can be performed as part of the liner and STI formation process 380 to deposit a dielectric material in the opening 320. The deposited material completely fills the opening 320. In some embodiments, the STI structure 390 can have the same material composition as the STI structure 290 (e.g., silicon oxide). It should be understood that a planarization process, such as a CMP process, may be performed to planarize the upper surfaces of the liner 385 and the STI structure 390 with the remaining components of the integrated circuit (IC) device 100 .

[0143] Now refer to Fig.12, an etching process 400 is performed on the integrated circuit (IC) device 100 to form a plurality of openings 410. The etching process 400 is configured to have sufficient etching selectivity between the material of the hard mask 160 and the material of other components of the integrated circuit (IC) device 100 so that the hard mask 160 is removed at a significantly faster etching rate. After performing the etching process 400, a plurality of openings 410 are formed at the locations of the removed hard mask 160. It should be understood that source / drain components will be formed in a later manufacturing process to fill these openings 410, and therefore, these openings 410 may also be interchangeably referred to as source / drain openings. It should also be understood that in the context of the present disclosure, a source / drain component (or a source / drain region) may be considered individually or collectively as a source or a drain of a transistor, depending on the context. For example, in some embodiments, a drain component may be formed to partially fill each opening 410.

[0144] Now refer to Fig.13 , a source / drain formation process 430 is performed on the integrated circuit (IC) device 100 to form a source / drain feature 440 in each opening 410. The source / drain formation process 430 includes a plurality of steps. As a first step of the source / drain formation process 430, the semiconductor layer 140 is removed, for example, by an etching process. The removal of the semiconductor layer 140 effectively extends the opening 410 further vertically downward in the Z direction. Thereafter, a lightly-doped source / drain (LDD) portion 440A of the source / drain feature 440 is formed to fill the opening created by removing each semiconductor layer 140. In other words, the LDD portion 440A effectively replaces each semiconductor layer 140. Then, a heavily doped source / drain portion 440B (e.g., more heavily doped than the LDD portion 440A) of the source / drain feature 440 is formed over the LDD portion 440A to partially fill each opening 410. It should be understood that the formation of the LDD portion 440A and / or the formation of the heavily doped portion 440B of the source / drain feature 440 may each include one or more epitaxial growth and / or doping processes.

[0145] In any case, the LDD portion 440A and the heavily doped portion 440B may collectively serve as the source / drain feature 440 (e.g., as a drain feature). After forming the source / drain feature 440, one or more deposition processes may be performed to form a hard mask 450 to completely fill each opening 410. In other words, the hard mask 450 is formed directly over the heavily doped portion 440B of the source / drain feature 440 in each opening 410.

[0146] Now refer to Fig.14 , an STI recess process 460 is performed on the integrated circuit (IC) device 100 to form an STI recess 470. The STI recess process 460 may include one or more etching processes for partially removing the liner 385. Therefore, the STI recess 470 is formed, wherein the STI recess 470 extends vertically downward in the Z direction and extends horizontally in the X direction. Therefore, the integrated circuit (IC) device 100 is divided again into two vertical stacks 100A and 100B by the STI recess 470.

[0147] For the corresponding Figures 15A-17A The manufacturing stages (to be discussed below) and their corresponding cross-sectional side views are also shown as follows: Figures 15B-17B , in order to provide further clarity of details of various aspects of the present disclosure. Among them, Figures 15B-17B The cross-sectional side views are each taken along a line A-A' horizontally spanning in the X direction, so Figures 15B-17B May also be referred to as X-cut views.

[0148] Now refer to Figures 15A-15B , a channel trimming process 480 is performed on the integrated circuit (IC) device 100 to form a plurality of lateral grooves 490. In more detail, the channel trimming process 480 may include one or more etching processes having an etching selectivity between the material of the channel layer 130 (e.g., silicon) and the material of the remaining components of the integrated circuit (IC) device 100. In this way, the channel layer 130 is etched away at a faster rate and substantially does not affect the components of the integrated circuit (IC) device 100 around the channel layer 130. It is understood that the lateral grooves 490 will be filled with a metal-containing gate structure in a subsequent manufacturing process.

[0149] It should be understood that the transverse groove 490 is formed in Fig.15A Although the transverse recess 490 formed in the vertical stack 100B is directly visible, the transverse recess 490 formed in the vertical stack 100A is not visible due to the Fig.15A The orientation of the three-dimensional perspective view is not directly visible. It is also noted that the removal of the channel layer 130 is not complete: a portion of the channel layer 130 still remains in the vertical stacks 100A and 100B. This aspect is also Fig. 15B The cross-sectional side view of FIG. 1 is clearly shown, wherein the cross-sectional cutting is performed in such a way that the channel layer 130 is Fig. 15B , but the transverse groove 490 is Fig. 15B Not directly visible.

[0150] Now refer to Figures 16A-16B , a dummy material removal process 500 is performed on the integrated circuit (IC) device 100 to remove some of the dummy material 260. The dummy material removal process 500 may include one or more etching processes with sufficient etching selectivity between the dummy material 260 and the remaining components of the integrated circuit (IC) device 100. It is noted that the etching process is configured to selectively remove the dummy material, because the dummy material 260 between the top spacer 210 and the bottom spacer 211 is removed, but the dummy material 260 between the bottom spacer 211 and the substrate 110 is substantially unaffected.

[0151] As a result of the selective removal of the dummy material 260, a plurality of grooves 510 may be formed at the locations of the selectively removed dummy material 260. In other words, the grooves 510 are located between the top spacer 210 and the bottom spacer 211. One of the unique physical features of the present disclosure is that the grooves 510 each extend beyond the outer sidewalls of the spacer 210 and the spacer 211. This is Fig.16A shown in Fig. 16B In other words, the sidewalls of each recess 510 protrude further toward the STI structure 290 in the X direction than the sidewalls of the top spacer 210 above the recess 510 or the sidewalls of the bottom spacer 211 below the recess 510. The selective removal of the dummy material 260 also effectively widens or expands the lateral recess 490, such as Fig.16A The recess 510 together with the lateral recess 490 will be filled with a metal-containing gate structure in a later manufacturing process.

[0152] Now refer to Figures 17A-17B, a gate formation process 530 is performed on the integrated circuit (IC) device 100 to form a gate structure 540 in the recess 490 and the recess 510. The gate formation process 530 may include a plurality of deposition processes. For example, a deposition process (e.g., ALD, CVD, PVD, etc.) may be performed to form a gate dielectric layer 550 to partially fill the recess 490 and the recess 510. Fig.17A As shown, portions of gate dielectric layer 550 may be formed over spacer 170, helmet structure 300, hard mask 450, STI structure 390, and liner 385. In other words, in addition to filling recess 490 and recess 510, portions of gate dielectric layer 550 may be formed to partially fill STI recess 470. However, these portions of gate dielectric layer 550 may be partially removed in subsequent processes.

[0153] In some embodiments, the gate dielectric layer 550 includes a high-k dielectric material, which refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (e.g., about 3.9). Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or a combination thereof.

[0154] As another step of the gate formation process 530, one or more deposition processes may be performed to form a gate electrode 560 in the recess 490 and the recess 510. The gate electrode 560 may be a metal-containing gate electrode. For example, the gate electrode 560 may include one or more work function (WF) metal layers and a fill metal layer. The work function metal layer may be configured to adjust a work function of the corresponding transistor. Example materials for the work function metal layer may include titanium nitride (TiN), titanium aluminide (TiAl), tantalum nitride (TaN), titanium carbide (Tic), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), titanium aluminum nitride (TiAlN), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or a combination of the foregoing. The fill metal layer may serve as the main conductive portion of the metal-containing gate electrode. In some embodiments, the fill metal layer may include cobalt, tungsten, copper, aluminum, or alloys thereof, or a combination of the foregoing materials. For the sake of simplicity, the work function metal layer and the filling metal layer are not shown or labeled separately here.

[0155] One of the unique features of the present disclosure is the relative arrangement between the gate dielectric layer 550 and the gate electrode 560. Specifically, the gate electrode 560 is circumferentially surrounded by the gate dielectric layer 550. For example, in Fig. 17B In the cross-sectional side view shown, the gate electrode 560 is surrounded 360 degrees by the gate dielectric layer 550. That is, all sides (e.g., top side, bottom side, left side, and right side) of the gate electrode 560 are in direct contact with the gate dielectric layer 550. In contrast, integrated circuit (IC) devices manufactured according to other process flows typically have a gate electrode that is only partially surrounded by a gate dielectric layer (e.g., the gate electrode is surrounded on the bottom side but not on the top side).

[0156] This unique physical configuration between the gate electrode 560 and the gate dielectric layer 550 herein is an inherent result of the unique manufacturing process flow of the present disclosure. For example, this is an inherent result of the formation of the recess 490 and the recess 510 (which is filled by the gate dielectric layer 550 and the gate electrode 560), wherein the recess 510 is at least partially defined by the top spacers 210 and 210. The bottom spacer 211 is defined by the lateral etching of the semiconductor layer 140 and the semiconductor layer 120, respectively. If the formation of the gate structure 540 is not limited (on the top side) by the top spacer 210, the gate dielectric layer 550 will not be formed on the bottom-facing surface of the top spacer 210, and the top surface of the gate electrode 560 will therefore not be in direct contact with the gate dielectric layer 550.

[0157] Another unique feature of the gate structure 540 of the present disclosure is that it protrudes laterally outward in the X direction. Fig. 17B , where the side surfaces of the gate dielectric layer 550 protrude further into the STI structure 290 than the side surfaces of the top spacer 210 and the bottom spacer 211. The lateral protrusion may also be an inherent result of the unique manufacturing process flow of the present disclosure. For example, the existing gate formation process flow may not involve filling the lateral groove (e.g., Figures 16A-16B The gate structure 540 of the present disclosure is formed by filling such a lateral groove 510. Therefore, when the lateral groove 510 is etched to protrude slightly into the nearby STI structure 290, it will also inherently cause the gate structure 540 to protrude laterally in the X direction.

[0158] It should be understood that each gate structure 540 may also include additional layers, such as interfacial layers, capping layers, diffusion / barrier layers, or other suitable layers. For example, an interfacial layer 570 may be selectively formed between the gate dielectric layer 550 and the channel layer 130 in the X direction. In some embodiments, the interfacial layer 570 may be formed at least in part by spontaneously reacting an oxide layer and a metal oxide layer at a relatively low temperature, such as less than about 100° C. (e.g., at a temperature between about 0° C. and about 50° C.). In some embodiments, the interfacial layer 570 may include a metal germanium oxide (MGO). x Ge y O z ), a metal silicon oxide (M x Si y O z ) or a metal germanium silicon oxide (M x Ge y Si z O 1 ). It should be understood that x, y, z, and l in the above chemical formulas can be positive integers, and their values ​​can be different in various cases. In some embodiments, the metal (M) in the interface layer 570 can include Al, Y, Ga, Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. In some other embodiments, the interface layer 570 is made of a ternary compound. For the sake of simplicity, the other layers of the gate structure 540 are not specifically shown here.

[0159] Now refer to Fig.18 , a portion of the gate dielectric layer 550 formed on the upper surface of the vertical stack 100A and the vertical stack 100B is removed, and then a contact etching stop layer (CESL) and interlayer dielectric (ILD) forming process 590 is performed on the integrated circuit (IC) device 100 to form a contact etching stop layer (CESL) 600 and an interlayer dielectric (ILD) 610. The contact etching stop layer (CESL) 600 and the interlayer dielectric (ILD) 610 are both formed in the STI groove 470. The contact etching stop layer (CESL) 600 is directly formed on the gate dielectric layer 550, and the interlayer dielectric (ILD) 610 is directly formed on the contact etching stop layer (CESL) 600. In some embodiments, the contact etching stop layer (CESL) 600 and the interlayer dielectric (ILD) 610 may include different types of dielectric materials.

[0160] Now refer to Fig.19 , a gate contact opening formation process 620 is performed on the integrated circuit (IC) device 100. First, an interlayer dielectric 630 is formed above the integrated circuit (IC) device 100 (including above the interlayer dielectric 610) by a deposition process. Thereafter, a patterning process can be performed to define a plurality of openings in the interlayer dielectric 630. Then, the openings are extended downward along the Z direction by one or more etching processes. The portions of the interlayer dielectric 610 exposed by the openings are etched away. This process continues until the contact etch stop layer (CESL) 600 is reached. At this point, gate contact openings 640 are formed.

[0161] Now refer to Fig. 20 , a CESL trimming process 650 is performed on the integrated circuit (IC) device 100. The CESL trimming process 650 may include one or more etching processes to remove a portion of the CESL 600 within the gate contact opening 640. Removing the CESL 600 exposes a portion of the gate structure 540, such as a side surface of the gate electrode 560 within the gate contact opening 640.

[0162] Now refer to Fig.21 , a gate contact formation process 670 is performed on the integrated circuit (IC) device 100 to form a plurality of gate contacts 680 in the gate contact opening 640. The gate contacts 680 may be formed by one or more deposition processes to deposit one or more conductive materials (e.g., aluminum, copper, tungsten, cobalt, etc.) into the gate contact opening 640, and thereafter a planarization process (e.g., a CMP process) is performed on the deposited conductive materials. The gate contacts 680 are electrically connected to the gate structure 540 and thus provide electrical connections to the gate structure 540. Note that the interlayer dielectric (ILD) 630 is removed after (or before) forming the gate contacts 680.

[0163] Now refer to Fig. 22A source / drain pad formation process 700 is performed on the integrated circuit (IC) device 100 to form a plurality of source / drain pads 720. As a first part of the source / drain pad formation process 700, the hard mask 450 may be removed by, for example, one or more etching processes. The removal of the hard mask 450 may leave source / drain pad openings above the heavily doped source / drain components 440B. As a second part of the source / drain pad formation process 700, a silicide layer 710 is formed on each of the heavily doped source / drain components 440B, and then a source / drain pad 720 is formed on each of the silicide layers 710. The source / drain pads 720 may be formed by one or more deposition processes to deposit one or more conductive materials (e.g., aluminum, copper, tungsten, cobalt, titanium, or a combination thereof) into the source / drain pad openings (e.g., to completely fill the source / drain pad openings), and then perform a planarization process (e.g., a CMP process) on the deposited conductive materials. These source / drain pads 720 are electrically coupled to the source / drain components 440 and thus may provide electrical connections to the source / drain components 440.

[0164] Note that since the source / drain feature 440 is a drain feature in the illustrated embodiment, the source / drain pad 720 may be interchangeably referred to as the drain pad 720. Note also that the helmet structure 300 may be removed after (or before) forming the source / drain pad 720, such that the upper surface of the source / drain pad 720 may be substantially coplanar with the upper surface of the STI structure 290.

[0165] Now refer to Fig.23, multiple metallization processes 740 are performed on the integrated circuit (IC) device 100 to form multiple metallization features. First, an etch stop layer 750 is formed above the integrated circuit (IC) device 100, including above the source / drain pads 720. Then, an interlayer dielectric (ILD) 760 is formed above the etch stop layer 750. The interlayer dielectric (ILD) 760 and the etch stop layer 750 may include different types of dielectric materials. Thereafter, a patterning process is performed to form a plurality of source / drain contact openings, each source / drain contact opening extending vertically through the interlayer dielectric (ILD) 760 and the etch stop layer 750. The source / drain contact openings at least partially expose Fig.23 Then, the source / drain contact openings are filled with a conductive material (e.g., aluminum, copper, tungsten, cobalt, titanium, or a combination thereof) to form source / drain contacts 770 (one of which is at Fig.23 The source / drain contacts 770 are electrically coupled to the source / drain components 440 , for example, through the source / drain pads 720 .

[0166] Subsequently, an etch stop layer 751 is formed over the source / drain contacts 770 and over the interlayer dielectric (ILD) 760. Then, an interlayer dielectric (ILD) 761 is formed over the etch stop layer 751. The interlayer dielectric (ILD) 761 and the etch stop layer 751 may include different types of dielectric materials. Thereafter, a patterning process is performed to form a plurality of via openings, each of which vertically extends through the interlayer dielectric (ILD) 761 and the etch stop layer 751. For example, the plurality of source / drain via openings at least partially expose the source / drain contacts 770, and the plurality of gate via openings at least partially expose the gate contacts 680 (see Fig. 22 ). The openings are then filled with a conductive material (e.g., aluminum, copper, tungsten, cobalt, titanium, or a combination thereof) to form a plurality of source / drain vias 780 and a plurality of gate vias 790. The source / drain vias 780 are electrically coupled to the source / drain components 440, for example, through the source / drain pads 720 and the source / drain contacts 770, and the gate vias 790 are electrically coupled to the gate structure 540, for example, through the gate contacts 680.

[0167] Now refer to Fig.24, a de-mesa process 800 is performed on the integrated circuit (IC) device 100 from the bottom side. The de-mesa process 800 includes one or more etching processes that etch away the substrate 110 and the active area 110A until the bottom-facing surface of the semiconductor layer 120 is exposed. As a result, a plurality of grooves 810 are formed in the integrated circuit (IC) device 100, wherein each groove 810 is defined by the bottom-facing surface of the semiconductor layer 120 and the sidewalls of the dummy material 260.

[0168] Now refer to Fig.25 , a source / drain formation process 820 is performed on the integrated circuit (IC) device 100 to form a plurality of source / drain components 840 in each recess 810. The aforementioned source / drain formation process 820 includes a plurality of steps. As a first step of the source / drain formation process 820, the semiconductor layer 120 is removed, for example, by an etching process. The removal of the semiconductor layer 120 effectively extends the recess 810 further vertically upward in the Z direction. Thereafter, a lightly doped source / drain (LDD) portion 840A of the source / drain component 840 is formed to fill the opening created by removing each semiconductor layer 120. In other words, the lightly doped source / drain (LDD) portion 840A effectively replaces each semiconductor layer 120.

[0169] Then, a heavily doped source / drain portion 840B of the source / drain feature 840 is formed over the lightly doped source / drain (LDD) portion 840A (e.g., more heavily doped than the lightly doped source / drain (LDD) portion 840A) to partially fill each recess 810. It should be understood that the formation of the lightly doped source / drain (LDD) portion 840A and / or the formation of the heavily doped source / drain portion 840B of the source / drain feature 840 may each include one or more epitaxial growth and / or doping processes. In any case, the lightly doped source / drain (LDD) portion 840A and the heavily doped source / drain portion 840B may collectively serve as a source / drain feature 840 (e.g., as a source feature).

[0170] After forming the source / drain features 840, a silicide layer 850 is formed on the bottom-facing surface of each heavily doped source / drain feature 840B, and then a source / drain pad 860 is formed on each heavily doped source / drain feature 840B. The source / drain pad 860 can be formed by depositing one or more conductive materials (e.g., aluminum, copper, tungsten, cobalt, titanium, or a combination thereof) into the recess 810 (e.g., completely filling the recess 810) through one or more deposition processes, and then performing a planarization process (e.g., a CMP process) on the deposited conductive material.

[0171] The source / drain pad 860 is electrically coupled to the source / drain feature 840 and thus provides an electrical connection to the source / drain feature 840. Note that since the source / drain feature 840 is a source feature in the illustrated embodiment, the source / drain pad 860 may be interchangeably referred to as a source pad 860. Note that the formation of the source feature 840 after the drain feature 440 is another unique aspect of the present disclosure. In many other embodiments of the gate-all-around (GAA) device, unlike the present disclosure, the source feature and the drain feature are typically formed simultaneously.

[0172] It should be understood that additional manufacturing processes may be performed to subsequently manufacture the integrated circuit (IC) device 100, such as forming source vias or other metallization components, packaging processes, testing processes, etc. To simplify the description, these additional manufacturing processes are not discussed in detail herein.

[0173] Fig.26 and Fig. 27 1 are different cross-sectional side views of portions of an integrated circuit (IC) device 100 illustrating various aspects of the present disclosure in greater detail. Specifically, Fig.26 1 shows a cross-sectional side view of an integrated circuit (IC) device 100 at a plane defined by an X direction and a Z direction (eg, a cross-sectional view taken along an X line). Fig. 27 1 shows a cross-sectional side view of an integrated circuit (IC) device 100 at a plane defined by the Y direction and the Z direction (eg, a cross-sectional view taken along a Y line). Fig.26 is along Fig.25 The tangent line A-A' shown is intercepted. Fig. 27 is along Fig.25 The section is cut by a BB' line as shown.

[0174] Now refer to Fig.26In the cross-sectional view taken along X, one of the unique features of the integrated circuit (IC) device 100 is that the gate electrode 560 is surrounded by the gate dielectric layer 550 on all sides. For example, the gate dielectric layer 550 is in direct physical contact with the top surface 560A, the bottom surface 560B, the side surface 560C (facing the STI structure 290), and the side surface 560D (facing the channel layer 130) of the gate electrode 560. Fig.26 In the cross-sectional view taken at X of , the gate dielectric layer 550 surrounds the gate electrode 560 circumferentially at 360 degrees. As described above, the gate electrode 560 is surrounded circumferentially by the gate dielectric layer 550, which is one of the inherent results of the unique manufacturing process flow of the present disclosure and can be evidence of the above-mentioned unique manufacturing process flow. For example, the top surface 560A and the bottom surface 560B of the gate electrode 560 are in direct physical contact with the gate dielectric layer 550, which is an inherent result of the gate structure 540 being formed within (or confined by) the top spacer 210 and the bottom spacer 211.

[0175] Note that in Fig. 27 In the Y-section cross-sectional view of FIG. 5 , the gate electrode 560 is not surrounded by the gate dielectric layer 550 on all sides. On the contrary, in the Y-section cross-sectional view, although the side surface 560D, the top surface 560A, and the bottom surface 560B of the gate electrode 560 are in direct physical contact with the gate dielectric layer 550, a side surface 560E of the gate electrode 560 is in direct physical contact with the gate contact 680. In other words, in FIG. Fig. 27 In the Y-section cross-sectional view, the gate dielectric layer 550 surrounds the gate electrode 560 by less than 360 degrees. However, the profile cross-sectional side view of the gate structure 540 in the Y-section cross-sectional view is also unique because the gate structure in a conventional all-around gate (GAA) device may not have both the top and bottom surfaces of its gate electrode directly in contact with the gate dielectric layer.

[0176] Furthermore, as discussed above, another unique feature of the gate structure 540 is that Fig.26 The gate structure 540 protrudes laterally outward in the cross-sectional view taken in the X direction. For example, a surface 880 of the gate structure 540 (which corresponds to a side surface of the gate dielectric layer 550) extends beyond the side surface 890 of the top spacer 210 in the X direction by a distance 900. In some embodiments, the distance 900 is greater than 0 and is in the range between about 0.01 nanometers and about 10 nanometers. The lateral protrusion of the gate structure 540 is also one of the inherent results of the unique manufacturing process flow of the present invention.

[0177] Still refer to Fig.26 , the gate electrode 560 has a horizontal dimension 910 (measured in the X direction, see Fig.26), and the gate structure 540 generally has a vertical dimension 920 (measured in the Z direction, see Fig.26 ). In some embodiments, the horizontal dimension 910 is in a range between about 4 nanometers and about 15 nanometers, and the vertical dimension 920 is in a range between about 8 nanometers and about 25 nanometers. The vertical dimension 920 may also be referred to as a gate length. The gate length (i.e., the vertical dimension 920) may also be precisely controlled according to various aspects of the present disclosure because it is directly related to (or determined by) the thickness 135 of the channel layer 130 (see Figure 1A-1B ), which can be finely controlled during the deposition of the channel layer 130.

[0178] Another unique aspect of the present disclosure is that the dimensions of the top spacer 210 and the bottom spacer 211 can be more precisely controlled. This is because the thickness 215 of the top spacer 210 and the thickness 216 of the bottom spacer 211 (see Figure 3A-3B ) at least partially through the semiconductor layer 140 and the semiconductor layer 120 (see Figure 1A-1B ), which can be finely controlled (e.g., using ALD). Precise control of the thickness 215 of the top spacer 210 and the thickness 216 of the bottom spacer 211 reduces undesirable spacer size variations from device to device, thereby improving the uniformity and / or performance of the device. In some embodiments, the thickness 215 and the thickness 216 are each in a range between about 4 nanometers and about 15 nanometers. The top spacers 210 are separated from each other by a distance 930 (measured in the X direction), which also corresponds to a lateral dimension of the channel layer 130. In some embodiments, this distance 930 is in a range between about 3 nanometers and about 15 nanometers. It should be understood that the bottom spacers 211 may also be separated from each other and separated from each other by a distance similar to the distance 930.

[0179] Fig.28 1 is a flow chart showing a method 1000 for manufacturing a semiconductor device. The method 1000 includes a step 1010 of forming a vertical protrusion structure. The vertical protrusion structure includes a substrate, a first semiconductor layer disposed above the substrate, a channel layer disposed above the first semiconductor layer, and a second semiconductor layer disposed above the channel layer. The first semiconductor layer and the second semiconductor layer each include a first type of semiconductor material. The channel layer includes a second type of semiconductor material different from the first type. In some embodiments, forming the vertical protrusion structure includes: depositing the first semiconductor layer above the substrate; and depositing the channel layer above the first semiconductor layer; depositing the second semiconductor layer above the channel layer; and patterning the second semiconductor layer, the channel layer, the first semiconductor layer, and the substrate into a plurality of vertical protrusion structures.

[0180] The method 1000 includes step 1020 of forming first recesses in the first semiconductor layer and the second semiconductor layer. Each first recess protrudes laterally inward.

[0181] The method 1000 includes step 1030 of filling the first recess with a dielectric spacer.

[0182] The method 1000 includes step 1040 of laterally trimming the channel layer and the substrate. The remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward.

[0183] Method 1000 includes step 1050 to form a gate structure in the second recesses. In some embodiments, forming the gate structure includes: forming a dummy material in each second recess; replacing the second semiconductor layer with a portion of the first source / drain component; and then replacing the dummy material in each second recess with a metal-containing gate structure. In some embodiments, the metal-containing gate structure in each second recess is formed to protrude laterally beyond the dielectric spacer in a cross-sectional side view. In some embodiments, forming the metal-containing gate structure includes: forming a gate dielectric layer in each second recess as a portion of the metal-containing gate structure; forming a metal-containing gate electrode in each second recess, wherein the metal-containing gate electrode is surrounded 360 degrees by the gate dielectric layer in a cross-sectional side view.

[0184] It should be understood that additional steps may be performed before, during, or after steps 1010-1050. For example, in some embodiments, method 1000 may further include the following steps: after forming a metal-containing gate structure in each second recess, replacing the first semiconductor layer with a portion of a second source / drain component. As another example, method 1000 may further include the following steps: after forming the first source / drain component but before forming the second source / drain component, forming a conductive gate contact next to the gate structure, wherein the conductive gate contact is in direct contact with the side surface of the gate structure. As yet another example, method 1000 may include the following steps: before forming the second source / drain component, forming a conductive source / drain pad above the first source / drain component. Other steps may include packaging and testing steps. For simplicity, these additional processes are not discussed in detail herein.

[0185] Fig.29An integrated circuit manufacturing system 1100 according to an embodiment of the present disclosure is shown. The manufacturing system 1100 includes a plurality of entities 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116 ..., N connected by a communications network 1118. The communications network 1118 may be a single network or may be a plurality of different networks, such as an intranet and an internetwork, and may include wired and wireless communication channels.

[0186] In one embodiment, entity 1102 represents a service system for manufacturing collaboration; entity 1104 represents a user, such as a product engineer who monitors a product of interest; entity 1106 represents an engineer, such as a process engineer who controls a process and related recipes, or an equipment engineer who monitors or adjusts the conditions and settings of a process tool; entity 1108 represents a metrology tool for IC testing and measurement; entity 1110 represents a semiconductor process tool, such as a process tool that performs the various deposition processes described above; entity 1112 represents a virtual metrology module associated with process tool 1110; entity 1114 represents an advanced process control module associated with a process tool such as entity 1110 and other process tools; entity 1116 represents a sampling module associated with process tool 1110.

[0187] Each entity may interact with other entities and may provide integrated circuit manufacturing, process control, and / or computing capabilities to other entities and / or receive capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the advanced processing control module of entity 1114 may include a plurality of computer hardware having software instructions encoded therein. The computer hardware may include a hard disk, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

[0188] The integrated circuit manufacturing system 1100 enables interaction between entities for integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In one embodiment, advanced process control includes adjusting process conditions, settings and / or recipes of a process tool applied to an associated wafer based on metrology results.

[0189] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0190] One of the functions provided by the IC manufacturing system 1100 can enable collaboration and information access in areas such as design, engineering and process, metrology, and advanced process control. Another function provided by the IC manufacturing system 1100 can integrate systems between devices, such as systems between metrology tools and process tools. This integration enables the devices to coordinate their activities. For example, integrating metrology tools and process tools can enable manufacturing information to be more effectively incorporated into the manufacturing process or APC module, and wafer data from online or field measurements can be implemented using metrology tools integrated into the relevant process.

[0191] Based on the above discussion, it can be seen that the present disclosure implements a unique vertical GAA manufacturing process flow. According to such a process flow, multiple semiconductor layers and channel layers with precisely controlled thicknesses can be formed. Then, these semiconductor layers are laterally etched to form grooves, and then these grooves are filled with dielectric top spacers and bottom spacers. Then, multiple additional processes are performed to form a gate structure between each group of top spacers and bottom spacers.

[0192] The unique manufacturing process flow and the resulting integrated circuit (IC) device structure disclosed herein provide advantages over conventional devices. However, it should be understood that embodiments do not require specific advantages, other embodiments may provide different advantages, and not all advantages must be disclosed herein. One of the advantages is the improvement of device uniformity. For example, by more accurately controlling the thickness of the semiconductor layer, the top spacer and bottom spacer formed subsequently can also achieve a precise thickness. Furthermore, by more accurately controlling the thickness of the channel layer, the gate structure formed subsequently can also achieve a precise gate length. Therefore, undesirable dimensional variations between multiple devices can be reduced, and device performance and / or yield can be improved. Other advantages include ease of manufacturing and compatibility with existing manufacturing processes.

[0193] The advanced lithography processes, methods, and materials described above can be used in many applications, including integrated circuit (IC) devices using GAA transistors and other three-dimensional devices, such as fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, a feature that is well suited for the above disclosure. In addition, spacers (also known as mandrels) used to form the fins of FinFETs can be processed according to the above disclosure. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion may equally apply to all-around gate (GAA) devices, and vice versa.

[0194] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a channel component. The semiconductor device includes a gate dielectric component located next to the channel component in a first cross-sectional side view. The first cross-sectional side view is defined by a vertical direction and a first horizontal direction. The semiconductor device includes a gate electrode component. In the first cross-sectional side view, the gate dielectric component surrounds a top surface of the gate electrode component, a bottom surface of the gate electrode component, a first side surface of the gate electrode component, and a second side surface of the gate electrode component opposite to the first side surface.

[0195] In some embodiments, according to the above-mentioned semiconductor device, in the aforementioned first cross-sectional side view, the aforementioned gate dielectric component surrounds the aforementioned gate electrode component 360 degrees; and in a second cross-sectional side view defined by the aforementioned vertical direction and a second horizontal direction perpendicular to the aforementioned first horizontal direction, the aforementioned gate electrode component is surrounded by the aforementioned gate dielectric component at an angle less than 360 degrees.

[0196] In some embodiments, according to the above-mentioned semiconductor device, it also includes a gate contact, wherein in the aforementioned second cross-sectional side view: the aforementioned gate dielectric component is in direct contact with the aforementioned top surface, the aforementioned bottom surface and the aforementioned first side surface of the aforementioned gate electrode component, but is not in direct contact with the aforementioned second side surface of the aforementioned gate electrode component; and the aforementioned gate contact is in direct contact with the aforementioned second side surface of the aforementioned gate electrode component.

[0197] In some embodiments, according to the above-mentioned semiconductor device, it also includes an interface layer, which is arranged between the aforementioned channel component and the aforementioned gate dielectric component in the aforementioned first horizontal direction, wherein the aforementioned interface layer includes a metal germanium oxide, a metal silicon oxide or a metal germanium silicon oxide.

[0198] In some embodiments, according to the above-mentioned semiconductor device, it also includes: a first source / drain component, which is arranged above the aforementioned channel component in the aforementioned vertical direction in the aforementioned first cross-sectional side view; a second source / drain component, which is arranged below the aforementioned channel component in the aforementioned vertical direction in the aforementioned first cross-sectional side view; a first spacer component, which is arranged above the aforementioned gate dielectric component in the aforementioned vertical direction in the aforementioned first cross-sectional side view; and a second spacer component, which is arranged below the aforementioned gate dielectric component in the aforementioned vertical direction in the aforementioned first cross-sectional side view.

[0199] In some embodiments, according to the semiconductor device, in the first cross-sectional side view, a side surface of the gate dielectric component protrudes beyond a side surface of the first spacer component or a side surface of the second spacer component in the first horizontal direction.

[0200] In some embodiments, according to the above-mentioned semiconductor device, it also includes: a third spacer component, which is arranged above the aforementioned first spacer component in the aforementioned vertical direction in the aforementioned first cross-sectional side view; a dummy material, which is arranged below the aforementioned second spacer component in the aforementioned vertical direction in the aforementioned first cross-sectional side view; and a dielectric component, which is in direct contact with the side surfaces of the aforementioned first spacer component, the aforementioned second spacer component, the aforementioned third spacer component, the aforementioned dummy material and the aforementioned gate dielectric component.

[0201] In some embodiments, according to the above-mentioned semiconductor device, the first source / drain component includes a first portion and a second portion; the second portion is more heavily doped than the first portion; the first portion is in direct contact with a side surface of the first spacer component; and the second portion is in direct contact with a side surface of the third spacer component.

[0202] In some embodiments, according to the above-mentioned semiconductor device, the aforementioned semiconductor device includes a vertical all-around gate (GAA) transistor; the aforementioned channel component includes a nanostructure channel of the aforementioned vertical all-around gate (GAA) transistor; and the aforementioned channel component has a larger dimension in the aforementioned vertical direction than the combination of the aforementioned gate electrode component and the aforementioned gate dielectric component.

[0203] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a channel component. The semiconductor device includes a first source / drain component, and in a first cross-sectional side view defined by a vertical direction and a first horizontal direction, the first source / drain component is disposed above the channel component. The semiconductor device includes a second source / drain component, which is disposed below the channel component in the first cross-sectional side view. The semiconductor device includes a gate structure, which is disposed next to the channel component in the first cross-sectional side view, wherein the gate structure includes a gate dielectric component and a metal-containing gate electrode component. In the first cross-sectional side view, the metal-containing gate electrode component is surrounded 360 degrees by the gate dielectric component.

[0204] In some embodiments, according to the above-mentioned semiconductor device, in a second cross-sectional side view defined by the aforementioned vertical direction and a second horizontal direction perpendicular to the aforementioned first horizontal direction, the aforementioned metal gate electrode component is surrounded by the aforementioned gate dielectric component in a manner of less than 360 degrees.

[0205] In some embodiments, according to the above-mentioned semiconductor device, the gate structure further includes an interface layer, and in the first cross-sectional side view, the interface layer is arranged between the gate dielectric component and the channel component, and the interface layer includes a metal germanium oxide, a metal silicon oxide, or a metal germanium silicon oxide, wherein the semiconductor device further includes: a first spacer arranged above the gate structure in the first cross-sectional side view; and a second spacer arranged below the gate structure in the first cross-sectional side view; wherein the gate structure laterally protrudes beyond the first spacer or the second spacer in the first horizontal direction.

[0206] The above summarizes the components of several embodiments so that technicians in the technical field to which the utility model belongs can better understand the viewpoints of the embodiments of the utility model. It should be understood by technicians in the technical field to which the utility model belongs that they can easily design or modify other processes and structures based on the embodiments of the utility model to achieve the same purpose and / or advantages as the embodiments introduced herein. It should also be understood by technicians in the technical field to which the utility model belongs that such equivalent structures do not deviate from the concept and scope of the utility model, and they can make various changes, substitutions and replacements without violating the concept and scope of the utility model. Therefore, the scope of protection of the utility model shall be defined as defined by the claims.

Claims

1. A semiconductor device, characterized in that: a channel member; a gate dielectric feature positioned adjacent to the channel feature in a first cross-sectional side view, wherein the first cross-sectional side view is defined by a vertical direction and a first horizontal direction; and A gate electrode component, wherein in the first cross-sectional side view, the gate dielectric component surrounds a top surface of the gate electrode component, a bottom surface of the gate electrode component, a first side surface of the gate electrode component, and a second side surface of the gate electrode component opposite to the first side surface.

2. The semiconductor device according to claim 1, wherein: In the first cross-sectional side view, the gate dielectric member surrounds the gate electrode member 360 degrees; and In a second cross-sectional side view defined by the vertical direction and a second horizontal direction perpendicular to the first horizontal direction, the gate electrode component is surrounded by the gate dielectric component at an angle less than 360 degrees.

3. The semiconductor device according to claim 2, wherein: Also included is a gate contact, wherein in the second cross-sectional side view: The gate dielectric component is in direct contact with the top surface, the bottom surface, and the first side surface of the gate electrode component, but is not in direct contact with the second side surface of the gate electrode component; and The gate contact is in direct contact with the second side surface of the gate electrode part.

4. The semiconductor device according to claim 1 or 2, wherein: Also included is an interface layer disposed between the channel component and the gate dielectric component in the first horizontal direction.

5. The semiconductor device according to claim 1 or 2, wherein: Also includes: a first source / drain component disposed above the channel component in the vertical direction in the first cross-sectional side view; a second source / drain feature disposed below the channel feature in the vertical direction in the first cross-sectional side view; a first spacer member disposed above the gate dielectric member in the vertical direction in the first cross-sectional side view; as well as A second spacer feature is disposed below the gate dielectric feature in the vertical direction in the first cross-sectional side view.

6. The semiconductor device according to claim 5, wherein: In the first cross-sectional side view, a side surface of the gate dielectric component protrudes beyond a side surface of the first spacer component or a side surface of the second spacer component in the first horizontal direction.

7. The semiconductor device according to claim 5, wherein: Also includes: a third spacer component disposed above the first spacer component in the vertical direction in the first cross-sectional side view; a dummy material disposed below the second spacer component in the vertical direction in the first cross-sectional side view; and a dielectric member directly contacting side surfaces of the first spacer member, the second spacer member, the third spacer member, the dummy material, and the gate dielectric member, in: The first source / drain component includes a first portion and a second portion; The first portion is in direct contact with a side surface of the first spacer member; and The second portion is in direct contact with a side surface of the third spacer member.

8. The semiconductor device according to claim 1 or 2, wherein: in: The semiconductor device includes a vertical gate all around (GAA) transistor; The channel feature includes a nanostructure channel of the vertical gate all around (GAA) transistor; and The channel feature has a larger dimension in the vertical direction than a combination of the gate electrode feature and the gate dielectric feature.

9. A semiconductor device, characterized in that: a channel member; a first source / drain feature disposed above the channel feature in a first cross-sectional side view defined by a vertical direction and a first horizontal direction; a second source / drain feature disposed below the channel feature in the first cross-sectional side view; and A gate structure is disposed adjacent to the channel feature in the first cross-sectional side view, wherein the gate structure includes a gate dielectric feature and a metal-containing gate electrode feature, and wherein in the first cross-sectional side view, the metal-containing gate electrode feature is surrounded 360 degrees by the gate dielectric feature.

10. The semiconductor device according to claim 9, wherein: wherein in a second cross-sectional side view defined by the vertical direction and a second horizontal direction perpendicular to the first horizontal direction, the metal-containing gate electrode component is surrounded by the gate dielectric component by less than 360 degrees; or The gate structure further includes an interface layer, and in the first cross-sectional side view, the interface layer is disposed between the gate dielectric component and the channel component, and the semiconductor device further includes: A first spacer is disposed above the gate structure in the first cross-sectional side view; and A second spacer is disposed below the gate structure in the first cross-sectional side view; The gate structure protrudes laterally beyond the first spacer or the second spacer in the first horizontal direction.

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