Back contact photovoltaic cell and cell assembly thereof

Abstract

The utility model belongs to the technical field of photovoltaic cells, and particularly relates to a back contact photovoltaic cell and a cell assembly thereof, which comprise a silicon substrate, an intrinsic amorphous silicon layer arranged on the backlight surface of the silicon substrate, N-type doped layers and P-type doped layers which are alternately arranged on the outer surface of the intrinsic amorphous silicon layer, and co-doped layers arranged between the N-type doped layers and the P-type doped layers. Conductive film layers and metal electrodes are sequentially arranged on the outer surfaces of the N-type doping layer and the P-type doping layer, and doping sources of the co-doping layer are a doping source of the N-type doping layer and a doping source of the P-type doping layer. The conductivity between the N-type doping layer and the P-type doping layer can be remarkably reduced, and transverse leakage current is avoided, so that the transverse insulativity of the back contact photovoltaic cell is improved, the cell performance such as the cell efficiency and the cell stability is improved, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of photovoltaic cells, and in particular relates to a back-contact photovoltaic cell and a cell assembly thereof. Background Art

[0002] Back-contact photovoltaic cells have important applications in the photovoltaic field due to their high efficiency and low light decay characteristics. However, the poor lateral insulation between the N-type doped region and the P-type doped region is a key issue affecting the performance of back-contact photovoltaic cells. In the prior art, US7468485B1 proposed the use of a tunneling oxide layer as a passivation layer, but this method is difficult to effectively control the lateral leakage current between the NP regions in practical applications, thereby affecting the battery performance.

[0003] In addition, optional insulation methods are to etch and isolate the spacer between the N-type doped region and the P-type doped region, or to use materials such as intrinsic amorphous silicon, polycrystalline silicon or silicon nitride for isolation. Although these methods can achieve isolation between the N-type doped region and the P-type doped region to a certain extent, there are problems such as complex preparation process, high cost, and unstable insulation effect. For example, the etching isolation method requires precise control of the etching depth and width, otherwise it is easy to cause battery performance to decline; while the use of material isolation method requires additional raw materials and process window selection, which increases the preparation cost and time. Therefore, the prior art still has a lot of room for improvement in improving the lateral insulation between the N-type doped region and the P-type doped region of the back contact photovoltaic cell.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Utility Model Content

[0005] The purpose of the utility model is to overcome the defects of the prior art that the back-contact photovoltaic cell cannot effectively control the lateral insulation between the NP regions, the stability of the insulation effect and the low cost, and to provide a back-contact photovoltaic cell and a battery component thereof, which can significantly reduce the conductivity between the N-type doped layer and the P-type doped layer, avoid lateral leakage current, thereby improving the lateral insulation of the back-contact photovoltaic cell, improving the battery performance such as battery efficiency and battery stability, and reducing the manufacturing cost.

[0006] In order to achieve the above-mentioned objectives, in a first aspect, the utility model provides a back-contact photovoltaic cell, comprising a silicon substrate, an intrinsic amorphous silicon layer is arranged on the backlight surface of the silicon substrate, an outer surface of the intrinsic amorphous silicon layer is arranged with alternatingly arranged N-type doping layers and P-type doping layers, a co-doping layer is arranged between the N-type doping layer and the P-type doping layer, and a conductive film layer and a metal electrode are sequentially arranged on the outer surfaces of the N-type doping layer and the P-type doping layer, and the doping source of the co-doping layer is the doping source of the N-type doping layer and the doping source of the P-type doping layer.

[0007] In some preferred embodiments of the present utility model, the thickness of the co-doped layer is 5-30 nm, and / or the ratio of the thickness of the co-doped layer to the thickness of the N-type doped layer or the P-type doped layer is 0.5-1.4:1, preferably 0.8-1.2:1.

[0008] In some preferred embodiments of the present utility model, the ratio of the width of the co-doped layer to the width of the N-type doped layer or the P-type doped layer is 0.01-0.5:1, and the width of the co-doped layer is 5-150 μm.

[0009] In some preferred embodiments of the present utility model, the thickness of the N-type doped layer is 8-20 nm, and the thickness of the P-type doped layer is 8-20 nm.

[0010] In some preferred embodiments of the present utility model, the width of the N-type doped layer is 100-600 μm, and the width of the P-type doped layer is 100-600 μm.

[0011] In some preferred embodiments of the present utility model, the thickness of the intrinsic amorphous silicon layer is 5-15 nm.

[0012] In some preferred embodiments of the present utility model, the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the N-type doped layer is 0.5-2:1, and the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the P-type doped layer is 0.5-2:1.

[0013] In some preferred embodiments of the present utility model, the thickness of the conductive film layer is 30-100 nm, more preferably 50-100 nm.

[0014] In some preferred embodiments of the present utility model, in the width direction, the N-type doped layer and the co-doped layer, and the co-doped layer and the P-type doped layer are in contact with each other and are continuously distributed as a whole.

[0015] In some preferred embodiments of the present utility model, the N-type doped layer is an N-type amorphous silicon layer or an N-type microcrystalline silicon layer, and the P-type doped layer is a P-type amorphous silicon layer or a P-type microcrystalline silicon layer.

[0016] In some preferred embodiments of the present utility model, an isolation groove is formed between the conductive film layer provided on the outer surface of the N-type doped layer and the conductive film layer provided on the outer surface of the P-type doped layer, and at least part of the isolation groove is located on the outer surface of the co-doped layer.

[0017] In some preferred embodiments of the present utility model, the conductive film layer is a transparent conductive film layer.

[0018] In some preferred embodiments of the present utility model, the back-contact photovoltaic cell further includes a light-receiving surface passivation and antireflection layer provided on the light-receiving surface of the silicon substrate.

[0019] In some preferred embodiments of the present utility model, the light-receiving surface of the silicon substrate is a textured surface, and the backlight surface is a polished surface.

[0020] In a second aspect, the present utility model provides a battery assembly, which includes the back-contact photovoltaic cell described in the first aspect.

[0021] Beneficial effects:

[0022] Through the above technical solutions, especially by setting the passivation structure of intrinsic amorphous silicon and alternately arranged N-type doped layers and P-type doped layers, and cooperating with the setting of a co-doped layer between the N-type doped layer and the P-type doped layer, the present utility model can utilize the double-ion effect of the co-doped layer (i.e., simultaneously doping N-type doping ions and P-type doping ions) to effectively insulate and isolate the N-type doped layer and the P-type doped layer, can significantly reduce the conductivity between the N-type doped layer and the P-type doped layer, avoid lateral leakage current, thereby improving the lateral insulation of the back-contact photovoltaic cell, and enhancing battery performance such as battery efficiency and battery stability, meeting the market demand for high-efficiency solar cells. The present utility model can significantly reduce the conductivity between the N-type doped layer and the P-type doped layer (in a specific embodiment, the applicant unexpectedly found that, compared with the single-doped (i.e., only N-type doping or P-type doping) film layer under the same conditions, when co-doping with N-type doping ions and P-type doping ions, the resistivity can rise from 1e3 Ω·cm to 1e5 Ω·cm to 1e7 Ω·cm to 1e10 Ω·cm, and the conductivity can drop from 1e-3 S / cm to 1e-5 S / cm to 1e-7 S / cm to 1e-10 S / cm). The possible speculative principles include that the difference in the sizes of the two ions causes local structural distortion, destroying the channels suitable for the migration of single electrons or holes; the two ions create different local environments resulting in site energy mismatch; and due to the need for the two ions to compete for the migratable sites in the doped substrate, and the doped substrate makes the distribution of the potential barrier complex due to the doping of multiple ions, and multiple adverse factors lead to a decrease in the carrier concentration and the overall mobility by an order of magnitude, and finally significant insulation is obtained.

[0023] Among them, compared with tunneling oxide passivation (the tunneling oxide generally needs to be annealed at high temperature to form pores in order to improve the tunneling ability of carriers. High-temperature annealing treatment will crystallize amorphous silicon, and the conductivity of the crystallized layer will increase significantly), the present utility model uses intrinsic amorphous silicon to passivate the N-type doped layer and the P-type doped layer. Using intrinsic amorphous silicon does not require high-temperature annealing treatment, so it can effectively control the conductivity, and the passivation effect is better, which is beneficial to controlling the conductivity of the N-type doped layer and the P-type doped layer, thereby effectively controlling the lateral leakage current between the N-type doped layer and the P-type doped layer, and is conducive to improving the battery efficiency. The present utility model also cooperates with the setting of a conductive film layer, which greatly improves the carrier collection ability of the N-type doped layer and the P-type doped layer, and further improves the battery efficiency.

[0024] Moreover, the structure of the back-contact photovoltaic cell of the present utility model is beneficial to reducing the NP junction interface on the silicon wafer surface and improving the passivation effect compared with using materials such as intrinsic amorphous silicon, polycrystalline silicon or silicon nitride for partitioning. And the battery structure of the present utility model enables the manufacturing process of patterned N-type doped layer, P-type doped layer, and co-doped layer to be formed by conventional processes such as the mask method or the diffusion method, which is convenient for simplifying the battery preparation process, reducing the production cost, improving the battery stability, and prolonging the service life of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of a specific embodiment of the back-contact photovoltaic cell of the present utility model.

[0027] DESCRIPTION OF THE REFERENCE NUMERALS

[0028] 1, silicon substrate; 2, intrinsic amorphous silicon layer; 3, N-type doped layer; 4, P-type doped layer; 5, co-doped layer; 6, conductive film layer; 7, metal electrode; 8, textured surface. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] In the present utility model, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

[0030] In the present utility model, the side close to the silicon substrate is defined as the inner side, and the side far from the silicon substrate is defined as the outer side.

[0031] In a first aspect, the present utility model provides a back-contact photovoltaic cell, as Figure 1 shown, which includes a silicon substrate 1. An intrinsic amorphous silicon layer 2 is provided on the backlight side of the silicon substrate 1. An N-type doped layer 3 and a P-type doped layer 4 are alternately arranged on the outer surface of the intrinsic amorphous silicon layer 2. A co-doped layer 5 is provided between the N-type doped layer 3 and the P-type doped layer 4. A conductive film layer 6 and a metal electrode 7 are sequentially provided on the outer surfaces of both the N-type doped layer 3 and the P-type doped layer 4. The doping source of the co-doped layer 5 is the doping source of the N-type doped layer 3 and the doping source of the P-type doped layer 4. It can be understood that the co-doped layer 5 is doped with both phosphorus and boron at the same time. The co-doped layer 5 is located outside the intrinsic amorphous silicon layer 2 and is embedded between the N-type doped layer 3 and the P-type doped layer 4, and is used to isolate the N-type doped layer 3 and the P-type doped layer 4 to achieve an insulating effect and effectively avoid leakage current.

[0032] In the present utility model, the statement that a conductive film layer 6 and a metal electrode 7 are sequentially provided on the outer surfaces of both the N-type doped layer 3 and the P-type doped layer 4 means that a conductive film layer 6 and a metal electrode 7 are sequentially provided on the outer surface of the N-type doped layer 3, and a conductive film layer 6 and a metal electrode 7 are sequentially provided on the outer surface of the P-type doped layer 4.

[0033] The back-contact photovoltaic cell of the present utility model can be formed by existing methods. Exemplarily, conventional processes such as a mask method or a diffusion method can be used to form the manufacturing processes of the patterned N-type doped layer 3, P-type doped layer 4, and co-doped layer 5, which is convenient for simplifying the battery preparation process, reducing the production cost, improving the battery stability at the same time, and extending the service life of the battery. Among them, in the mask method, a dry or wet mask method can be used, including the steps of in-situ growth of a dry mask and removal of the mask, as well as the steps of deposition, etching, and removal of the mask layer in the wet mask method. In the diffusion method, the intrinsic amorphous silicon layer 2 can be deposited first, and then the required doping source is coated and heated for diffusion to form the steps of patterned doping regions. Among them, in order to obtain the target doped layer, the gas of the target doping source is introduced during the preparation to reach the target doping concentration, which is prior art and will not be elaborated here.

[0034] In some preferred embodiments of the present utility model, an isolation groove is formed between the conductive film layers 6 provided on the outer surfaces of the N-type doped layer 3 and the P-type doped layer 4, and at least a part of the isolation groove is located on the outer surface of the co-doped layer 5. The isolation groove is used to isolate the leakage current between the N-type doped layer 3 and the P-type doped layer 4. The isolation groove can be formed by etching or by reserving a spacing when depositing the film layer.

[0035] In some preferred embodiments of the present utility model, the thickness of the co-doped layer 5 is 5 - 30 nm. By disposing the co-doped layer 5 with an appropriate thickness between the N-type doped layer 3 and the P-type doped layer 4, it is more conducive to controlling the conductivity of the co-doped layer 5, thereby reducing the leakage current.

[0036] In some preferred embodiments of the present utility model, the ratio of the thickness of the co-doped layer 5 to the thickness of the N-type doped layer 3 or the P-type doped layer 4 is 0.5 - 1.4:1, preferably 0.8 - 1.2:1. The battery structure of the present utility model with a co-doped layer 5 having a specific thickness ratio is more conducive to controlling the conductivity of the co-doped layer 5, thereby reducing the leakage current.

[0037] In some preferred embodiments of the present utility model, the ratio of the width of the co-doped layer 5 to the width of the N-type doped layer 3 or the P-type doped layer 4 is 0.01 - 0.5:1, which is more conducive to reducing the leakage current between the N-type doped layer 3 and the P-type doped layer 4.

[0038] Preferably, in the present utility model, the width of the co-doped layer 5 is 5 - 150 μm.

[0039] In some preferred embodiments of the present utility model, the width of the N-type doped layer 3 is 100 - 600 μm, and the width of the P-type doped layer 4 is 100 - 600 μm. The widths of the N-type doped layer 3 and the P-type doped layer 4 can be the same or different, and can be selected according to actual needs.

[0040] In some preferred embodiments of the present utility model, the thickness of the N-type doped layer 3 is 8 - 20 nm, preferably 10 - 20 nm, and the thickness of the P-type doped layer 4 is 8 - 20 nm, preferably 10 - 20 nm. The thicknesses of the N-type doped layer 3 and the P-type doped layer 4 can be the same or different, and can be selected according to actual needs. When the thicknesses of the N-type doped layer 3 and the P-type doped layer 4 are different, they can be prepared by the mask method, and when the thicknesses are the same, they can be prepared by the diffusion method.

[0041] In some preferred embodiments of the present utility model, the thickness of the intrinsic amorphous silicon layer 2 is 5 - 15 nm. Using an intrinsic amorphous silicon layer 2 with an appropriate thickness is more conducive to improving the battery efficiency.

[0042] In some preferred embodiments of the present utility model, the ratio of the thickness of the intrinsic amorphous silicon layer 2 to the thickness of the N-type doped layer 3 is 0.5 - 2:1, and the ratio of the thickness of the intrinsic amorphous silicon layer 2 to the thickness of the P-type doped layer 4 is 0.5 - 2:1. For the battery structure with this thickness ratio range of the present utility model, it is more conducive to improving the battery efficiency.

[0043] In some preferred embodiments of the present utility model, the thickness of the conductive film layer 6 is 30 - 100 nm.

[0044] In some preferred embodiments of the present utility model, the conductive film layer 6 is a transparent conductive film layer 6.

[0045] In some preferred embodiments of the present utility model, in the width direction, the N-type doped layer 3 and the co-doped layer 5 are in contact with each other and the co-doped layer 5 and the P-type doped layer 4 are in contact with each other and are continuously distributed as a whole. Such a structure enables the N-type doped layer 3, the co-doped layer 5, and the P-type doped layer 4 to adopt a process of first depositing a film as a whole and then patterning and doping, which simplifies the manufacturing process, reduces the manufacturing cost, and at the same time further improves the isolation and insulation effect between the N-type doped layer 3 and the P-type doped layer 4, and further improves the battery stability.

[0046] In some preferred embodiments of the present utility model, the N-type doped layer 3 is an N-type amorphous silicon layer or an N-type microcrystalline silicon layer, and the P-type doped layer 4 is a P-type amorphous silicon layer or a P-type microcrystalline silicon layer. The N-type doped layer 3 and the P-type doped layer 4 with an amorphous structure, in combination with the intrinsic amorphous silicon layer 2, form an amorphous passivation structure, which is more conducive to controlling the leakage current between the N-type doped layer and the P-type doped layer.

[0047] The back-contact photovoltaic cell of the present utility model may further include other conventional film layer structures. For example, in some preferred embodiments of the present utility model, the back-contact photovoltaic cell further includes a light-receiving surface passivation and antireflection layer provided on the light-receiving surface of the silicon substrate 1. The present utility model has no limitation on the structure of the light-receiving surface passivation and antireflection layer. Exemplarily, for example, it may be a stack of a passivation layer and an antireflection layer provided in sequence. The structure of the light-receiving surface passivation and antireflection layer may be deposited, for example, before forming the intrinsic amorphous silicon layer 2.

[0048] In some preferred embodiments of the present utility model, the light-receiving surface of the silicon substrate 1 is a textured surface 8, and the backlight surface is a polished surface. The textured surface 8 may be formed by performing steps such as texturing cleaning and polishing on the silicon substrate 1 before depositing each film layer. The silicon substrate 1 may be, for example, an N-type single crystal silicon, and the size may be, for example, 156 mm × 156 mm.

[0049] In a second aspect, the present utility model provides a battery module, which includes the back-contact photovoltaic cell described in the first aspect.

[0050] Embodiments of the present utility model will be described in detail below. They are exemplary and are only used to explain the present utility model, and should not be construed as a limitation to the present utility model.

[0051] Example 1

[0052] A back-contact photovoltaic cell as shown in Figure 1 is formed by means of dry masking, and specifically includes the following steps:

[0053] S1. Provide a single-crystal silicon substrate 1;

[0054] S2. Deposit an intrinsic amorphous silicon layer 2 on the backlight side by PECVD method, and the thickness of the intrinsic amorphous silicon layer 2 is 8 nm;

[0055] S3. Use dry method in the masking method to form a patterned N-type doped layer 3 (which is amorphous silicon, and the doping ion is phosphorus), a P-type doped layer 4 (which is amorphous silicon, and the doping ion is boron), and a co-doped layer 5. Specifically, a polymer masking layer is pasted on the non-N-type doped layer 3 region, and an N-type doped amorphous silicon layer is grown in-situ, and then the polymer masking layer is torn off. Then, a polymer masking layer is pasted on the non-P-type doped layer 4 region, and a P-type doped amorphous silicon layer is grown in-situ, and then the polymer masking layer is torn off. Subsequently, a polymer masking layer is pasted on the N-type doped layer 3 and the P-type doped layer 4 again, and a co-doped layer 5 doped with both phosphorus and boron is grown. The thicknesses of the N-type doped layer 3, the P-type doped layer 4, and the co-doped layer 5 are 15 nm, 15 nm, and 8 nm respectively, the widths are 400 μm, 500 μm, and 50 μm respectively, and the phosphorus doping concentration in the co-doped layer 5 is 5e18 cm -3 , and the boron doping concentration is 5e18 cm -3 . The phosphorus doping concentration of the N-type doped layer 3 is 1e20 cm -3 , and the boron doping concentration of the P-type doped layer 4 is 1e19 cm -3 ;

[0056] S4. Then deposit a transparent conductive film layer 6, i.e., an ITO layer, on the N-type doped layer 3 and the P-type doped layer 4, and the thickness of the ITO layer is 80 nm; and an isolation groove is formed by opening on the conductive film layer 6 corresponding between the N-type doped layer 3 and the P-type doped layer 4;

[0057] S5. Then, metal electrodes 7 (silver paste electrodes) are respectively arranged on the corresponding outer surfaces of the N-type doped layer 3 and the P-type doped layer 4.

[0058] The cell efficiency of the back-contact photovoltaic cell obtained in Example 1 is 26.7%, and the reverse leakage current is 0.10 A.

[0059] Example 2

[0060] It is carried out with reference to Embodiment 1, except that in S3, the N-type doping layer 3, P-type doping layer 4, and co-doping layer 5 are formed by diffusion method, with the size and doping concentration remaining unchanged. Specifically, the process is as follows: First, deposit an intrinsic amorphous silicon layer 2, and then coat the corresponding target doping sources on the preset regions corresponding to the N-type doping layer 3, P-type doping layer 4, and co-doping layer 5 respectively. The preset region corresponding to the N-type doping layer 3 is coated with a phosphorus doping source, the preset region corresponding to the P-type doping layer 4 is coated with a boron doping source, and the preset region corresponding to the co-doping layer 5 is coated with both phosphorus and boron doping sources simultaneously; then heat to diffuse the doping sources into the intrinsic amorphous silicon layer 2 to form patterned doped film layers. The cell efficiency of the back-contact photovoltaic cell obtained in Embodiment 2 is 26.5%, and the reverse leakage current is 0.10 A.

[0061] Comparative Example 1

[0062] It is carried out with reference to Embodiment 1, except that when forming the co-doping layer 5 between the N-type doping layer 3 and P-type doping layer 4, no doping gas is introduced to form an undoped intrinsic amorphous silicon layer. The cell efficiency of the back-contact photovoltaic cell obtained in Comparative Example 1 is 26.4%, and the reverse leakage current is 0.15 A.

[0063] The back-contact photovoltaic cell structure of the present invention can effectively insulate and isolate the N-type doping layer and P-type doping layer, significantly reduce the conductivity between the N-type doping layer and P-type doping layer, avoid lateral leakage current, thereby improving the lateral insulation of the back-contact photovoltaic cell, and enhancing cell performance such as cell efficiency and cell stability, meeting the market demand for high-efficiency solar cells. Moreover, the cell structure of the present invention enables the manufacturing process of forming patterned N-type doping layer, P-type doping layer, and co-doping layer by conventional processes such as mask method or diffusion method, facilitating the simplification of the cell preparation process, reducing the production cost, improving the cell stability, and extending the service life of the cell.

[0064] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solutions of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A back contact photovoltaic cell, characterized in that: The invention comprises a silicon substrate, an intrinsic amorphous silicon layer is arranged on the backlight surface of the silicon substrate, an outer surface of the intrinsic amorphous silicon layer is arranged with N-type doping layers and P-type doping layers arranged alternately, a co-doping layer is arranged between the N-type doping layer and the P-type doping layer, and a conductive film layer and a metal electrode are sequentially arranged on the outer surfaces of the N-type doping layer and the P-type doping layer, and the doping source of the co-doping layer is the doping source of the N-type doping layer and the doping source of the P-type doping layer.

2. The back contact photovoltaic cell according to claim 1, characterized in that: The thickness of the co-doped layer is 5-30 nm, and / or the ratio of the thickness of the co-doped layer to the thickness of the N-type doped layer or the P-type doped layer is 0.5-1.4:

1.

3. The back contact photovoltaic cell according to claim 1, characterized in that: The ratio of the width of the co-doped layer to the width of the N-type doped layer or the P-type doped layer is 0.01-0.5:1, and the width of the co-doped layer is 5-150 μm.

4. The back-contact photovoltaic cell according to any one of claims 1 to 3, characterized in that: The thickness of the N-type doping layer is 8-20 nm, and the thickness of the P-type doping layer is 8-20 nm.

5. The back-contact photovoltaic cell according to any one of claims 1 to 3, characterized in that: The width of the N-type doped layer is 100-600 μm, and the width of the P-type doped layer is 100-600 μm.

6. The back-contact photovoltaic cell according to any one of claims 1 to 3, characterized in that: The thickness of the intrinsic amorphous silicon layer is 5-15 nm; and / or, The ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the N-type doped layer is 0.5-2:1, and the ratio of the thickness of the intrinsic amorphous silicon layer to the thickness of the P-type doped layer is 0.5-2:1; and / or, The thickness of the conductive film layer is 30-100 nm.

7. The back contact photovoltaic cell according to claim 1, characterized in that: In the width direction, the N-type doped layer and the co-doped layer, and the co-doped layer and the P-type doped layer are in contact with each other and are continuously distributed as a whole; and / or, The N-type doped layer is an N-type amorphous silicon layer or an N-type microcrystalline silicon layer, and the P-type doped layer is a P-type amorphous silicon layer or a P-type microcrystalline silicon layer.

8. The back contact photovoltaic cell according to claim 1, characterized in that: An isolation groove is provided between the conductive film layer disposed on the outer surface of the N-type doped layer and the conductive film layer disposed on the outer surface of the P-type doped layer, and at least a portion of the isolation groove is located on the outer surface of the co-doped layer; and / or, The conductive film layer is a transparent conductive film layer.

9. The back contact photovoltaic cell according to claim 1, characterized in that: The back contact photovoltaic cell further comprises a light-receiving surface passivation anti-reflection layer disposed on the light-receiving surface of the silicon substrate; and / or, The light-receiving side of the silicon substrate is a textured surface, and the backlight side is a polished surface.

10. A battery assembly, characterized in that: It comprises a back-contact photovoltaic cell as claimed in any one of claims 1 to 9.

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