Chip three-dimensional stacking structure

Abstract

The utility model discloses a chip three-dimensional stacking structure, which relates to the technical field of semiconductor chip packaging and comprises a device body, a chip shell is fixedly mounted on the surface of the device body, a sealing plate is fixedly mounted at the bottom of the chip shell, a chip packaging mechanism is arranged at the bottom of the chip shell, and the chip packaging mechanism is arranged on the surface of the device body. And a sealing mechanism is arranged in the chip shell. According to the utility model, through the design of the first chip groove and the second chip groove, accurate positioning and rapid installation of the first chip and the second chip are realized, the modular design not only simplifies the alignment and fixing steps in the packaging process, but also improves the packaging accuracy and efficiency, and through the introduction of the silicon intermediate plate, the packaging efficiency is improved. According to the invention, a plurality of chips can be interconnected in a more compact space to form a hierarchical packaging structure, which not only reduces the size and weight of the packaging, but also improves the integration level and performance of the packaging, and improves the economic benefit.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor chip packaging, and particularly relates to a three-dimensional chip stacking structure. Background Art

[0002] In the traditional three-dimensional chip stacking process, two chips are joined together and electrical connections are formed between the contact pads on each chip and the substrate. For example, two chips are stacked and joined to each other. Then the stacked chips are joined to a carrier substrate and the contact pads on each chip are electrically connected to the contact pads on the carrier substrate by wire bonding. However, this requires the carrier substrate to be larger than the chips for wire bonding, and the package includes the thickness of the carrier. As people's requirements for the electrical performance and miniaturization of electronic products are getting higher and higher, the traditional three-dimensional chip stacking process can no longer meet the requirements of thin and small structures and excellent electrical performance.

[0003] Chinese Patent Publication No. CN214848586U, a three-dimensional stacking package structure for semiconductor chip integration, the technical solution provided by this patent document is: including a substrate, two groups of semiconductor chips, an upper plastic encapsulation layer, a lower plastic encapsulation layer, an upper pressing cover, a lower pressing cover, four groups of fixing bolts and two groups of pressing plates. Adhesives are coated on the bottom ends of the two groups of semiconductor chips, and the two groups of semiconductor chips are fixedly pasted on the top and bottom ends of the substrate through the adhesives. Welding wires are welded on the left and right ends of the two groups of semiconductor chips. Multiple groups of springs are arranged inside the upper pressing cover and the lower pressing cover. The two groups of pressing plates are respectively fixedly installed inside the upper pressing cover and the lower pressing cover through connections with the springs, and the bottom end of one group of pressing plates is in close contact with the top end of the upper plastic encapsulation layer, and the top end of the other group of pressing plates is in close contact with the bottom end of the lower plastic encapsulation layer.

[0004] In order to solve the problem that the mismatch of the thermal expansion coefficients of the materials of the existing device makes it easy to warp after plastic encapsulation, affecting the normal use of the product and resulting in a high limitation in use, the prior art is to use the method that during assembly, the semiconductor chips are adhered to both end faces of the substrate through adhesives, and the electrical connection with the substrate is completed through welding wires, and then the plastic encapsulation protection is completed through the upper plastic encapsulation layer and the lower plastic encapsulation layer, and finally the upper pressing cover and the lower pressing cover are firmly installed so that the pressing plates are in close contact with the upper plastic encapsulation layer and the lower plastic encapsulation layer. However, there will still be a situation where the volume and weight of the original structure package are relatively large, which in turn leads to the problem of low economic efficiency. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a three-dimensional chip stacking structure to solve the problems raised in the above background art.

[0006] To solve the above technical problems, the technical solution adopted by the utility model is:

[0007] A three-dimensional stacked chip structure, including a device body, on the surface of the device body, a chip housing is fixedly installed, and at the bottom of the chip housing, a sealing plate is fixedly installed.

[0008] At the bottom of the chip housing, a chip packaging mechanism is provided, and inside the chip housing, a sealing mechanism is provided.

[0009] The chip packaging mechanism includes a first chip slot, which is opened on one side of the bottom of the chip housing. Inside the first chip slot, a first chip is fixedly installed. On the other side of the bottom of the chip housing, a second chip slot is opened. Inside the second chip slot, a second chip is fixedly installed. At the bottom of the second chip, a convex block is fixedly installed.

[0010] A further improvement of the technical solution of the present utility model is that: the main component materials of the chip housing are alumina ceramic and silicon nitride ceramic. The chip housing is used to package the chip, and alumina ceramic and silicon nitride ceramic endow the chip housing with good heat resistance, corrosion resistance, insulation performance and mechanical properties.

[0011] A further improvement of the technical solution of the present utility model is that: at the bottom of the first chip, a convex block is also fixedly installed. The bottom of the convex block is fixedly connected to a silicon interposer. The convex block technology changes the wire connection of the traditional package into a point connection, significantly improves the pin density, and helps to reduce the package volume.

[0012] A further improvement of the technical solution of the present utility model is that: on the surface of the silicon interposer, conductive vias adapted to the convex blocks are opened. At the bottom of the silicon interposer, metal bumps are fixedly installed. Through the conductive vias, the silicon interposer can achieve high-speed and low-latency electrical connections between different chips.

[0013] A further improvement of the technical solution of the present utility model is that: at the bottom of the silicon interposer, a wire carrier board is fixedly installed. At the bottom of the wire carrier board, metal balls are fixedly installed. The wire carrier board provides stable mechanical support for the chip, prevents the chip from being physically damaged during packaging and use, and by using the wire carrier board, the packaging process of the chip can be simplified, and the packaging difficulty and cost can be reduced.

[0014] A further improvement of the technical solution of the present utility model is that: on the surface of the sealing plate, an installation groove is opened, and the wire carrier board is fixedly installed in the installation groove opened on the sealing plate. The wire carrier board is installed on the surface of the sealing plate through the installation groove.

[0015] A further improvement of the technical solution of the present utility model is that: the sealing mechanism includes a sealing block, which is fixedly installed on the bottom surface of the chip housing. On the surface of the sealing plate, a sealing groove is opened, and the sealing groove is adapted to the sealing block. The cooperation of the sealing block and the sealing groove improves the sealing performance at the connection between the chip housing and the sealing plate.

[0016] Due to the adoption of the above technical solution, the technical progress achieved by the present utility model compared with the prior art is as follows:

[0017] 1. The present utility model provides a three-dimensional stacked chip structure. Through the design of setting chip slot 1 and chip slot 2, the precise positioning and rapid installation of chip 1 and chip 2 are realized. This modular design not only simplifies the alignment and fixing steps during encapsulation but also improves the accuracy and efficiency of encapsulation. Furthermore, through the cooperation of bumps and silicon interposer, high-density and high-reliability electrical connections are achieved. Compared with the traditional wire bonding method, bump connection has lower resistance, inductance, and capacitance, thereby improving the speed and quality of signal transmission. Additionally, through the introduction of the silicon interposer, multiple chips can be interconnected within a more compact space, forming a hierarchical packaging structure. This structure not only reduces the volume and weight of the package but also improves the integration and performance of the package, while enhancing the economic benefits.

[0018] 2. The present utility model provides a three-dimensional stacked chip structure. By setting the chip housing and the sealing block in cooperation with the sealing plate and the sealing groove, the sealing performance of the device body is better, enhancing the practicality of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is the front view structural schematic diagram of the present utility model;

[0020] Figure 2 is the cross-sectional view structural schematic diagram of the chip housing of the present utility model;

[0021] Figure 3 is the partial structural schematic diagram of the chip packaging mechanism of the present utility model;

[0022] Figure 4 is the cross-sectional view structural schematic diagram of the sealing plate of the present utility model.

[0023] In the figure: 1. Device body; 11. Chip housing; 12. Sealing plate; 2. Chip packaging mechanism; 21. Chip slot 1; 22. Chip 1; 23. Chip slot 2; 24. Chip 2; 25. Bump; 26. Silicon interposer; 27. Lead frame; 28. Metal ball; 3. Sealing mechanism; 31. Sealing block; 32. Sealing groove. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following further describes the present utility model in detail with reference to the embodiments:

[0025] Embodiment 1

[0026] As Figures 1 - 4As shown in the figure, this embodiment provides a three-dimensional stacked chip structure, including a device body 1. A chip housing 11 is fixedly installed on the surface of the device body 1. A sealing plate 12 is fixedly installed at the bottom of the chip housing 11. A chip encapsulation mechanism 2 is arranged at the bottom of the chip housing 11. A sealing mechanism 3 is arranged inside the chip housing 11. The chip encapsulation mechanism 2 includes a first chip slot 21. The first chip slot 21 is opened on one side of the bottom of the chip housing 11. A first chip 22 is fixedly installed inside the first chip slot 21. A second chip slot 23 is opened on the other side of the bottom of the chip housing 11. A second chip 24 is fixedly installed inside the second chip slot 23. A bump 25 is fixedly installed at the bottom of the second chip 24. The main constituent materials of the chip housing 11 are alumina ceramic and silicon nitride ceramic. A bump 25 is also fixedly installed at the bottom of the first chip 22. The bottom of the bump 25 is fixedly connected to a silicon interposer 26. The bump 25 technology changes the wire connection of traditional packaging into a point connection, significantly improving the pin density and helping to reduce the packaging volume. Conductive vias adapted to the bumps 25 are opened on the surface of the silicon interposer 26. Metal bumps are fixedly installed at the bottom of the silicon interposer 26. Through the conductive vias, the silicon interposer 26 can achieve high-speed and low-latency electrical connections between different chips. A wire carrier 27 is fixedly installed at the bottom of the silicon interposer 26. Metal balls 28 are fixedly installed at the bottom of the wire carrier 27. The wire carrier 27 provides stable mechanical support for the chip, preventing the chip from being physically damaged during packaging and use. Moreover, by using the wire carrier 27, the packaging process of the chip can be simplified, and the packaging difficulty and cost can be reduced. Installation slots are opened on the surface of the sealing plate 12. The wire carrier 27 is fixedly installed in the installation slots opened on the sealing plate 12. The wire carrier 27 is installed on the surface of the sealing plate 12 through the installation slots. Through the design of setting the first chip slot 21 and the second chip slot 23, precise positioning and rapid installation of the first chip 22 and the second chip 24 are achieved. This modular design not only simplifies the alignment and fixing steps during packaging but also improves the accuracy and efficiency of packaging. Then, through the cooperation of the bumps 25 and the silicon interposer 26, high-density and high-reliability electrical connections are achieved. Compared with the traditional wire bonding method, the bump connection has lower resistance, inductance, and capacitance, thus improving the speed and quality of signal transmission. Then, through the introduction of the silicon interposer 26, multiple chips can be interconnected in a more compact space, forming a hierarchical packaging structure. This structure not only reduces the volume and weight of the packaging but also improves the integration and performance of the packaging, while enhancing the economic benefits.

[0027] Embodiment 2

[0028] As Figures 1 - 4As shown, on the basis of Embodiment 1, the present utility model provides a technical solution: Preferably, the sealing mechanism 3 includes a sealing block 31, the sealing block 31 is fixedly installed on the bottom surface of the chip housing 11, a sealing groove 32 is formed on the surface of the sealing plate 12, the sealing groove 32 is adapted to the sealing block 31, and the sealing plate cooperates with the sealing groove 32, improving the sealing performance at the connection between the chip housing 11 and the sealing plate 12 and enhancing the practicability of the device.

[0029] Next, the working principle of the three-dimensional stacked chip structure will be specifically described.

[0030] As Figures 1 - 4 shown, when using the device, first open the chip housing 11 and the sealing plate 12. Through the designs of the chip slot one 21 and the chip slot two 23, precise positioning and rapid installation of the chip one 22 and the chip two 24 are achieved. This modular design not only simplifies the alignment and fixing steps during packaging but also improves the accuracy and efficiency of packaging. Then, through the cooperation of the bumps 25 and the silicon interposer 26, high-density and high-reliability electrical connections are realized. Compared with the traditional wire bonding method, the bump connection has lower resistance, inductance, and capacitance, thereby improving the speed and quality of signal transmission. Furthermore, through the introduction of the silicon interposer 26, multiple chips can be interconnected in a more compact space, forming a hierarchical packaging structure. This structure not only reduces the volume and weight of the package but also improves the integration and performance of the package, while enhancing the economic benefits. Through the cooperation of the chip housing 11 and the sealing block 31 with the sealing plate 12 and the sealing groove 32, the sealing performance of the device body 1 is better, enhancing the practicability of the device.

[0031] The above has generally described the present utility model in detail. However, based on the present utility model, some modifications or improvements can be made, which are obvious to those of ordinary skill in the art. Therefore, modifications or improvements made without departing from the spirit and concept of the present utility model are within the protection scope of the present utility model.

Claims

1. A three-dimensional chip stacking structure, comprising a device body (1), characterized in that: A chip housing (11) is fixedly mounted on the surface of the device body (1), and a sealing plate (12) is fixedly mounted on the bottom of the chip housing (11); A chip packaging mechanism (2) is provided at the bottom of the chip housing (11), and a sealing mechanism (3) is provided inside the chip housing (11); The chip packaging mechanism (2) comprises a chip slot (21) which is provided on one side of the bottom of a chip housing (11), a chip (22) being fixedly mounted inside the chip slot (21), a chip slot (23) being provided on the other side of the bottom of the chip housing (11), a chip (24) being fixedly mounted inside the chip slot (23), and a bump (25) being fixedly mounted on the bottom of the chip (24).

2. The three-dimensional chip stacking structure according to claim 1, characterized in that: The main constituent materials of the chip housing (11) are alumina ceramics and silicon nitride ceramics.

3. The three-dimensional chip stacking structure according to claim 1, characterized in that: A bump (25) is also fixedly mounted on the bottom of the chip 1 (22), and a silicon intermediate board (26) is fixedly connected to the bottom of the bump (25).

4. The three-dimensional chip stacking structure according to claim 3, characterized in that: The surface of the silicon intermediate board (26) is provided with a conductive through hole matched with the bump (25), and the bottom of the silicon intermediate board (26) is fixedly mounted with a metal bump.

5. The three-dimensional chip stacking structure according to claim 4, characterized in that: A wire carrier (27) is fixedly mounted on the bottom of the silicon intermediate board (26), and a metal ball (28) is fixedly mounted on the bottom of the wire carrier (27).

6. The three-dimensional chip stacking structure according to claim 5, characterized in that: The surface of the sealing plate (12) is provided with a mounting groove, and the wire carrier plate (27) is fixedly installed in the mounting groove provided in the sealing plate (12).

7. The three-dimensional chip stacking structure according to claim 6, characterized in that: The sealing mechanism (3) comprises a sealing block (31), the sealing block (31) being fixedly mounted on the bottom surface of the chip housing (11), and a sealing groove (32) being provided on the surface of the sealing plate (12), the sealing groove (32) being adapted to the sealing block (31).

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