Chip unit, semiconductor packaging device and power electronic equipment

Abstract

The utility model provides a chip unit, a semiconductor packaging device and power electronic equipment, and relates to the technical field of semiconductors. In the chip unit, the heat-conducting and current-conducting plate is provided with a first surface and a second surface which are oppositely arranged, the lining plate comprises an insulating substrate layer and a first metal layer connected with the insulating substrate layer, the first surface of the heat-conducting and current-conducting plate is connected with the chip, and the second surface of the heat-conducting and current-conducting plate is connected with the first metal layer. On the basis of guaranteeing the conductive connection requirement of the chip and the first metal layer, the heat-conducting and conductive plate and the first metal layer of the lining plate are utilized to jointly form a heat-conducting structure from the chip to the insulating substrate layer of the lining plate, and the heat-conducting structure is relatively thick, so that a relatively good heat-conducting and soaking effect can be achieved. The possibility of local overheating of the chip unit at the chip can be reduced, the situation that local thermal stress is caused at the chip to affect the service life of the lining plate and further affect the service life of the chip unit is avoided, and the situation that local temperature rise of the chip unit at the chip position is high to affect the working performance of the chip can also be avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and more specifically, to a chip unit, a semiconductor packaging device and a power electronic device. Background Art

[0002] In semiconductor technology, such as in power modules, chips are usually connected to the upper metal layer of a substrate. For example, currently, chips are generally soldered to the upper copper layer of a DBC substrate, and the chips are cooled by the DBC substrate during subsequent use.

[0003] However, the thickness of the upper metal layer of the substrate is usually relatively thin. For example, the thickness of the upper copper layer of a DBC substrate is generally 0.3 mm, and the thickest is only 0.4 mm. It is difficult for the heat of the chip to be evenly diffused to the substrate, resulting in a situation where the local temperature at the connection between the substrate and the chip is too high, which will cause local thermal stress on the substrate and increase the risk of the hot spot effect. This not only affects the overall heat dissipation efficiency of the semiconductor device, but also may cause the chip to overheat and be damaged. Summary of the Utility Model

[0004] The utility model aims to solve to a certain extent the problem in related technologies of how to improve the reliability and performance of a chip unit caused by excessive local temperature at the chip connection position.

[0005] To solve at least one aspect of the above problems to at least a certain extent, in a first aspect, the utility model provides a chip unit, which includes a chip, a substrate and a thermally conductive and electrically conductive plate; the thermally conductive and electrically conductive plate has a first surface and a second surface arranged opposite to each other, the substrate includes an insulating substrate layer and a first metal layer connected to the insulating substrate layer, the first surface of the thermally conductive and electrically conductive plate is connected to the chip, and the second surface of the thermally conductive and electrically conductive plate is connected to the first metal layer.

[0006] Optionally, the first metal layer has at least one conductive region;

[0007] At least one of the at least one conductive region includes at least one set conductive region, and the thermally conductive and electrically conductive plate is correspondingly arranged for each set conductive region, and the thermally conductive and electrically conductive plate is connected to one or more of the chips.

[0008] Optionally, when the number of conductive regions is greater than the number of set conductive regions, at least one of the conductive regions other than the set conductive regions is correspondingly arranged with the thermally conductive and electrically conductive plate.

[0009] Optionally, the projections of all the chips corresponding to at least one of the heat-conducting and electrically-conducting plates on the insulating substrate layer fall within the area covered by the projection of the heat-conducting and electrically-conducting plate on the insulating substrate layer; the projection of at least one of the heat-conducting and electrically-conducting plates on the insulating substrate layer falls within the area covered by the projection of the set conductive area corresponding to the heat-conducting and electrically-conducting plate on the insulating substrate layer.

[0010] Optionally, when the number of the heat-conducting and electrically-conducting plates is multiple, the thicknesses of the heat-conducting and electrically-conducting plates are consistent, and the thickness of the heat-conducting and electrically-conducting plate is the distance between the first surface and the second surface.

[0011] Optionally, when the number of the heat-conducting and electrically-conducting plates is multiple, the heat-conducting and electrically-conducting plates are connected by an insulating structure.

[0012] Optionally, the heat-conducting and electrically-conducting plate is any one of a solid metal plate, a two-phase liquid flow heat pipe, and a solid heat pipe.

[0013] Optionally, the two-phase liquid flow heat pipe includes any one of a columnar heat pipe and a channel heat pipe;

[0014] A column structure is arranged in the hollow closed cavity of the columnar heat pipe, and the column structure is provided with microchannels or capillary structures for the phase change cycle of the working medium;

[0015] The channel heat pipe has a fine channel structure inside.

[0016] Optionally, the solid heat pipe includes a heat-conducting and electrically-conducting shell and a solid heat-conducting structure, the heat-conducting and electrically-conducting shell forms a first cavity, and the solid heat-conducting structure is arranged in the first cavity.

[0017] Optionally, positioning columns are arranged in the first cavity, and the solid heat-conducting structure is provided with positioning holes for positioning connection with the positioning columns;

[0018] And / or, the solid heat-conducting structure includes a plurality of heat-conducting plates, and the plurality of heat-conducting plates are stacked and arranged in the first cavity.

[0019] Optionally, the chip unit further includes a heat dissipation substrate, the liner further includes a second metal layer, the second metal layer and the first metal layer are respectively connected to different sides of the insulating substrate layer; the insulating substrate layer is connected to the heat dissipation substrate through the second metal layer.

[0020] In a second aspect, the present utility model provides a semiconductor packaging device, including a packaging structure and the chip unit according to any one of the first aspects above, the packaging structure forms a packaging cavity, and the packaging cavity is at least used for accommodating the chips, the heat-conducting and electrically-conducting plates, and the first metal layer of the chip unit.

[0021] In a third aspect, the present utility model provides a power electronic device, including the semiconductor packaging device described in the second aspect above; and / or including the chip unit described in any one of the first aspects above.

[0022] Compared with the related prior art, in the chip unit, semiconductor packaging device and power electronic device of the present utility model, a heat-conducting and electrically-conducting plate is added between the chip and the substrate. The heat-conducting and electrically-conducting plate has a first surface and a second surface arranged opposite to each other. The first surface of the heat-conducting and electrically-conducting plate is used to connect with the chip, and the second surface of the heat-conducting and electrically-conducting plate is used to connect with the first metal layer of the substrate, so that the chip is connected to the first metal layer of the substrate through the heat-conducting and electrically-conducting plate. On the basis of ensuring the electrical connection requirement between the chip and the first metal layer, a heat-conducting structure from the chip to the insulating substrate layer of the substrate is jointly formed by the heat-conducting and electrically-conducting plate and the first metal layer of the substrate. This heat-conducting structure has a relatively large thickness, can achieve a good heat-conducting and heat-averaging effect, can reduce the possibility of local overheating of the chip unit at the chip, avoid causing local thermal stress at the chip and affecting the service life of the substrate, and further affect the service life of the chip unit. It can also avoid the local temperature rise of the chip unit at the chip position being relatively high and affecting the working performance of the chip. In addition, the heat-conducting and electrically-conducting plate has a plate structure, which can not only improve the heat-conducting and heat-averaging effect, but also facilitate the setting of its structure, such as facilitating the connection with the chip and the first metal layer. The structure is simple and has strong practicability. Description of the Drawings

[0023] Figure 1 Schematic structural diagram of the chip unit in the first embodiment of the present utility model;

[0024] Figure 2 is Figure 1 Schematic cross-sectional view at the A-A section in

[0025] Figure 3 Exploded schematic diagram of the chip unit in the first embodiment of the present utility model;

[0026] Figure 4 Schematic structural diagram of the chip unit in the second embodiment of the present utility model;

[0027] Figure 5 Another schematic structural diagram of the chip unit in the second embodiment of the present utility model;

[0028] Figure 6 Another schematic structural diagram of the chip unit in the second embodiment of the present utility model;

[0029] Figure 7 Schematic structural diagram of the heat-conducting and electrically-conducting plate in the third embodiment of the present utility model;

[0030] Figure 8 is Figure 7Schematic cross-sectional view at section B-B;

[0031] Figure 9 Structural schematic diagram of the heat-conducting and electrically-conducting plate in the fourth embodiment of the present invention;

[0032] Figure 10 Structural schematic diagram of the heat-conducting and electrically-conducting plate in the fifth embodiment of the present invention;

[0033] Figure 11 Another structural schematic diagram of the heat-conducting and electrically-conducting plate in the fifth embodiment of the present invention.

[0034] Explanation of reference numerals in the drawings:

[0035] 1 - Chip; 1a - First chip; 1b - Second chip; 1c - Third chip; 2 - Substrate; 21 - Insulating substrate layer; 22 - First metal layer; 221 - Conductive region; 2211 - Set conductive region; 221a - First conductive region; 221b - Second conductive region; 221c - Third conductive region; 221d - Fourth conductive region; 221e - Fifth conductive region; 23 - Second metal layer; 3 - Heat-conducting and electrically-conducting plate; 301 - First surface; 302 - Second surface; 303 - Top plate; 304 - Bottom plate; 31 - Liquid two-phase flow heat spreader; 31A - Columnar heat spreader; 311 - Column structure; 31B - Channel-type heat spreader; 312 - Channel structure; 32 - Solid heat spreader; 321 - Heat-conducting and electrically-conducting housing; 3211 - Locating post; 322 - Solid heat-conducting structure; 3221 - Heat-conducting plate; 3222 - Locating hole; 3a - First heat-conducting and electrically-conducting plate; 3b - Second heat-conducting and electrically-conducting plate; 3c - Third heat-conducting and electrically-conducting plate; 3d - Fourth heat-conducting and electrically-conducting plate; 3e - Fifth heat-conducting and electrically-conducting plate; 4 - Heat dissipation substrate; 5 - Encapsulation structure; 61 - First welding connection layer; 62 - Second welding connection layer; 63 - Third welding connection layer; 7 - Pin. Detailed implementation manners

[0036] To make the above objects, features and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the drawings.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, the terms "installation", "connection" and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0038] In the description of this specification, the descriptions referring to terms such as "embodiment", "one embodiment", "some embodiments", "exemplarily", and "one embodiment" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or embodiment are included in at least one embodiment or embodiment of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or embodiment. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or embodiments.

[0039] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of such features.

[0040] In the drawings, the Z-axis represents the vertical direction, that is, the up-and-down position, and the positive direction of the Z-axis (that is, the direction pointed by the arrow of the Z-axis) represents up, and the negative direction of the Z-axis represents down; in the drawings, the X-axis represents the front-back position, and the positive direction of the X-axis (that is, the direction pointed by the arrow of the X-axis) represents the front side, and the negative direction of the X-axis represents the rear side; in the drawings, the Y-axis represents the horizontal direction and is designated as the left-right position, and the positive direction of the Y-axis (that is, the direction pointed by the arrow of the Y-axis) represents the right side, and the negative direction of the Y-axis represents the left side; at the same time, it should be noted that the above-mentioned meanings represented by the Z-axis, Y-axis, and X-axis are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model.

[0041] As Figures 1 to 3 shown, in a first aspect, the present utility model provides a chip unit, which includes a chip 1, a substrate 2, and a thermally conductive and electrically conductive plate 3; the thermally conductive and electrically conductive plate 3 has a first surface 301 and a second surface 302 arranged opposite to each other, the substrate 2 includes an insulating substrate layer 21 and a first metal layer 22 connected to the insulating substrate layer 21, the first surface 301 of the thermally conductive and electrically conductive plate 3 is connected to the chip 1, and the second surface 302 of the thermally conductive and electrically conductive plate 3 is connected to the first metal layer 22.

[0042] In this embodiment, taking the substrate 2 as a DBC substrate as an example to illustrate the content of the present utility model, but it should be understood that it is not limited thereto, and it can be other structures with similar functions.

[0043] As Figure 2 shown, exemplarily, the chip 1 is welded to the thermally conductive and electrically conductive plate 3, and the two are welded to form a first welded connection layer 61; the thermally conductive and electrically conductive plate 3 is welded to the first metal layer 22, and the two are welded to form a second welded connection layer 62, thereby realizing the relative position fixation of the chip 1 and the substrate 2.

[0044] It should be understood that in other embodiments, the chip 1 and the heat-conducting and electrically-conducting plate 3, and the heat-conducting and electrically-conducting plate 3 and the first metal layer 22 can be in contact by pressing, so as to fix the relative positions of the chip 1 and the substrate 2. Relevant existing technologies can be adopted and will not be described in detail herein.

[0045] The heat-conducting and electrically-conducting plate 3 is a plate-like structure that can both conduct heat and electricity. On this basis, its internal composition is not limited. It can realize the heat conduction and electrical connection from the chip 1 to the first metal layer 22. The setting of the heat-conducting and electrically-conducting plate 3 does not affect the existing electrical connection requirements between the chip 1 and the first metal layer 22. However, it can enhance the heat conduction and heat transfer uniformity from the chip 1 to the insulating substrate layer 21.

[0046] It should be understood that other structures can also be provided for the chip unit as needed, such as the pin 7 described later. Other structures can adopt relevant technologies, and exemplary descriptions will be given in the subsequent part of this specification.

[0047] Thus, a heat-conducting and electrically-conducting plate 3 is added between the chip 1 and the substrate 2. The heat-conducting and electrically-conducting plate 3 has a first surface 301 and a second surface 302 arranged oppositely. The first surface 301 of the heat-conducting and electrically-conducting plate 3 is used to connect with the chip 1, and the second surface 302 of the heat-conducting and electrically-conducting plate 3 is used to connect with the first metal layer 22 of the substrate 2. Thus, the chip 1 is connected to the first metal layer 22 of the substrate 2 through the heat-conducting and electrically-conducting plate 3. On the basis of ensuring the electrical connection requirements between the chip 1 and the first metal layer 22, the heat-conducting and electrically-conducting plate 3 and the first metal layer 22 of the substrate 2 jointly form a heat conduction structure from the chip 1 to the insulating substrate layer 21 of the substrate 2. This heat conduction structure has a relatively large thickness, can achieve a better heat conduction and heat equalization effect, can reduce the possibility of local overheating of the chip unit at the chip 1, avoid causing local thermal stress at the chip 1 and affecting the service life of the substrate 2, and further affect the service life of the chip unit. It can also avoid the local temperature rise of the chip unit at the chip 1 position being relatively high and affecting the working performance of the chip 1. In addition, the heat-conducting and electrically-conducting plate 3 is in a plate structure, which can not only improve the heat conduction and heat equalization effect, but also facilitate the setting of its structure, such as facilitating the connection with the chip 1 and the first metal layer 22. The structure is simple and has strong practicability.

[0048] In the above embodiment, optionally, the first metal layer 22 has at least one conductive region 221 ( Figure 3 marked).

[0049] As Figure 3 shown, optionally, when the first metal layer 22 has only one conductive region 221, the conductive region 221 is a set conductive region 2211 ( Figure 6 marked), and the set conductive region 2211 is connected to one or more chips 1 through the same heat-conducting and electrically-conducting plate 3.

[0050] Specifically, the set conductive region 2211 is the conductive region 221 of the chip 1 connected through the heat-conducting and electrically-conducting plate 3. The arrangement of the heat-conducting and electrically-conducting plate 3 is beneficial to improving the temperature uniformity at various positions within the set conductive region 2211.

[0051] As Figures 1 to 3 shown, when the first metal layer 22 has only one conductive region 221 and is connected to two chips 1.

[0052] When the number of chips 1 is multiple, the types of the multiple chips 1 can be different, which can be determined according to actual needs. At this time, after the heat-conducting and electrically-conducting plate 3 and the first metal layer 22 are connected, they can serve as a common electrode for the multiple chips 1. The common electrode is connected to the lower ends of the respective chips 1, and the connection between the upper ends of the respective chips 1 can adopt related technologies, such as wire bonding, which will not be elaborated here.

[0053] As Figures 4 to 6 shown, optionally, when the first metal layer 22 has multiple conductive regions 221, at least one of the multiple conductive regions 221 is the set conductive region 2211, and a heat-conducting and electrically-conducting plate 3 is provided corresponding to each set conductive region 2211 one by one, and the heat-conducting and electrically-conducting plate 3 is connected to one or more chips 1.

[0054] Specifically, the set conductive region 2211 is the conductive region 221 of the chip 1 connected through the heat-conducting and electrically-conducting plate 3. There can be multiple set conductive regions 2211, which are determined according to the chip 1 layout requirements of the chip unit.

[0055] It should be understood that the respective conductive regions 221 of the first metal layer 22 of the lining plate 2 are insulated from each other, and the respective heat-conducting and electrically-conducting plates 3 are insulated from each other. The conductive region 221 can be formed by technologies such as copper cladding technology, which will not be elaborated here.

[0056] As Figure 6 shown, optionally, when the number of conductive regions 221 is greater than the number of set conductive regions 2211, at least one conductive region 221 outside the set conductive regions 2211 is provided with a heat-conducting and electrically-conducting plate 3.

[0057] It should be understood that in some cases, the number of conductive regions 221 can be greater than the number of set conductive regions 2211. For example, some conductive regions 221 are not designed to mount the chip 1 but are designed to be connected to the pin 7. Such conductive regions 221 (such as the fifth conductive region 221 of the power electronic device) are usually connected to the corresponding electrodes of the chip 1 through, for example, bonding wires, such as connected to the top electrode of the chip 1, and then form an external connection terminal through the pin 7 electrically connected by this conductive region 221. Such a conductive region 221 can be configured with a heat-conducting conductive plate 3. When the heat-conducting conductive plate 3 is configured, this conductive region 221 is connected to the corresponding bonding wire and the pin 7 through this heat-conducting conductive plate 3, which is beneficial to improving the temperature consistency at various places within the set conductive region 2211.

[0058] As Figure 6 shown, exemplarily, the first metal layer 22 is divided into five conductive regions 221, namely the first conductive region 221a, the second conductive region 221b, the third conductive region 221c, the fourth conductive region 221d, and the fifth conductive region 221e. Among them, only the first conductive region 221a, the second conductive region 221b, the third conductive region 221c, and the fourth conductive region 221d are the set conductive regions 2211. The first conductive region 221a, the second conductive region 221b, the third conductive region 221c, the fourth conductive region 221d, and the fifth conductive region 221e are respectively welded with the first heat-conducting conductive plate 3a, the second heat-conducting conductive plate 3b, the third heat-conducting conductive plate 3c, the fourth heat-conducting conductive plate 3d, and the fifth heat-conducting conductive plate 3e. The first heat-conducting conductive plate 3a, the second heat-conducting conductive plate 3b, the third heat-conducting conductive plate 3c, and the fourth heat-conducting conductive plate 3d are respectively welded with the chip 1. For example, the first heat-conducting conductive plate 3a is welded with the first chip 1a, and the second heat-conducting conductive plate 3b is welded with the second chip 1b and the third chip 1c.

[0059] Of course, it should be understood that the conductive regions 221 not designed to mount the chip 1 may not be configured with the heat-conducting conductive plate 3, which will not be elaborated here in detail.

[0060] Of course, it should be understood that in some embodiments, some pins 7 can be electrically connected to the corresponding set conductive regions 2211 through the heat-conducting conductive plates 3, which will not be elaborated here in detail.

[0061] In the above embodiments, optionally, when the number of the heat-conducting conductive plates 3 is multiple, the thicknesses of the heat-conducting conductive plates 3 are the same. The thickness of the heat-conducting conductive plate 3 is the distance between the first surface 301 and the second surface 302.

[0062] Specifically, the first surface 301 and the second surface 302 are oppositely arranged in the Z-axis direction in the figure, and the distance between the two is the thickness of the heat-conducting conductive plate 3.

[0063] In this way, it is beneficial to the manufacturing and forming of the heat-conducting and electrically-conducting plate 3. For example, the heat-conducting and electrically-conducting plate 3 can be supported by a solid metal plate with a uniform thickness, and moreover, the differences caused by inconsistent thicknesses of the heat-conducting and electrically-conducting plates 3 can be avoided.

[0064] In the above embodiments, optionally, when the number of the heat-conducting and electrically-conducting plates 3 is multiple, the heat-conducting and electrically-conducting plates 3 are connected by an insulating structure.

[0065] Exemplarily, the insulating structure is made of an insulating material such as plastic. The insulating structure is in a frame structure, and each heat-conducting and electrically-conducting plate 3 is mounted on the frame structure. For example, each heat-conducting and electrically-conducting plate 3 and the frame structure are integrally connected by a connection method such as welding. However, it should be understood that the setting of the frame structure should not affect the contact connection between each heat-conducting and electrically-conducting plate 3 and the corresponding conductive region 221. This solution is not shown in the figure.

[0066] In this way, the heat-conducting and electrically-conducting plates 3 are connected into a whole through the insulating structure, which is convenient for subsequent positioning of the relative positions between the heat-conducting and electrically-conducting plates 3 and the corresponding conductive regions 221 and connection operations, and can improve the assembly efficiency of assembling multiple heat-conducting and electrically-conducting plates 3.

[0067] In the above embodiments, optionally, the projection of all the chips 1 corresponding to at least one heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21 falls within the area covered by the projection of the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21.

[0068] As Figure 6 shown, exemplarily, among the chips 1 connected to any heat-conducting and electrically-conducting plate 3, the projections of the chips 1 on the insulating substrate layer 21 respectively fall within the area covered by the projection of the corresponding heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21.

[0069] In this way, a relatively large contact area can be obtained between the bottom of the chip 1 and the first surface 301 of the corresponding heat-conducting and electrically-conducting plate 3, thereby ensuring the heat-conducting performance between the chip 1 and the heat-conducting and electrically-conducting plate 3.

[0070] In the above embodiments, optionally, the projection of at least one heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21 falls within the area covered by the projection of the set conductive region 2211 corresponding to the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21.

[0071] As Figure 6 shown, exemplarily, the projections of any heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21 respectively fall within the area covered by the projection of the corresponding conductive region 221, such as the set conductive region 2211, on the insulating substrate layer 21.

[0072] As a result, the second surface 302 of the heat-conducting and electrically-conducting plate 3 can obtain a relatively large contact area with the corresponding electrically-conducting region 221, thereby ensuring the heat-conducting performance between the heat-conducting and electrically-conducting plate 3 and the corresponding electrically-conducting region 221.

[0073] Furthermore, the projections of all the chips 1 corresponding to the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21 fall within the area covered by the projection of the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21; and the projection of the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21 falls within the area covered by the projection of the set electrically-conducting region 2211 corresponding to the heat-conducting and electrically-conducting plate 3 on the insulating substrate layer 21. Thus, it can be ensured that the heat-conducting and electrically-conducting plate 3 can achieve a good heat-conducting and electrically-conducting effect between the chip 1 and the set electrically-conducting region 2211, and a good temperature equalization effect can be achieved.

[0074] In the above embodiments, optionally, the heat-conducting and electrically-conducting plate 3 is any one of a solid metal plate, a liquid two-phase flow heat pipe 31 (refer to Figures 7 to 9 ) and a solid heat pipe 32 (refer to Figures 10 to 11 ).

[0075] Specifically, the solid metal plate is a flat object made of metal (such as steel, aluminum, copper, iron, etc.), without a hollow sealed cavity or internal filler. It has good mechanical properties, electrical conductivity, and heat conductivity. The material is simple to obtain, and it is sturdy and durable.

[0076] The liquid two-phase flow heat pipe 31 is usually made of high heat-conducting materials such as copper or aluminum, and contains a series of fine micro-channels or capillary structures inside. For example, the heat-conducting and electrically-conducting plate 3 includes a top plate 303 and a bottom plate 304. The top plate 303 and the top plate 303 are connected and enclose a hollow sealed cavity, and the hollow sealed cavity is used to form micro-channels or capillary structures, and these structures are responsible for accommodating and promoting the circulation of the working fluid (usually water or other low-boiling-point liquids).

[0077] The working process of the circulation of the working fluid in the liquid two-phase flow heat pipe 31 is as follows:

[0078] Evaporation stage: When a heat source (such as the heat generated by the chip 1) heats the liquid two-phase flow heat pipe, the working fluid absorbs heat in the area where the chip 1 is located and changes from a liquid state to a gaseous state (evaporation process), and this phase change process can efficiently absorb a large amount of heat.

[0079] Flow stage: The gaseous working fluid then flows naturally to the cold end of the liquid two-phase flow heat pipe through the micro-channels or capillary structures by using capillary force. During this process, the gas carries heat and transfers it inside the liquid two-phase flow heat pipe.

[0080] Condensation stage: After reaching the cold end, the gaseous working fluid releases heat when it meets the cold and re-condenses into a liquid state, and then returns to the evaporation area under the action of gravity or capillary force, completing a cycle.

[0081] The liquid two-phase flow heat pipe 31 has good thermal conductivity and lightweight characteristics, and can meet the heat conduction and heat dissipation requirements.

[0082] Furthermore, the liquid two-phase flow heat pipe 31 includes any one of a columnar heat pipe 31A and a channel heat pipe 31B.

[0083] As Figure 9 shown, furthermore, a column structure 311 is provided in the hollow sealed cavity surrounded by the top plate 303 and the bottom plate 304 of the columnar heat pipe 31A. The column structure 311 has microchannels or capillary structures for the phase change cycle of the working fluid.

[0084] The column structure 311 can be arranged vertically or obliquely. The column structure 311 can also have microchannels or capillary structures inside to promote the phase change cycle of the working fluid. Such a design can increase the heat exchange area and improve the heat dissipation capacity per unit volume. The column structure 311 not only provides a channel for the phase change heat transfer of the working fluid, but also serves as a medium for heat conduction, quickly transferring heat from the heat source to the surface of the column structure 311 and dissipating heat through the top plate 303 or the bottom plate 304.

[0085] As Figure 7 and Figure 8 shown, the channel heat pipe 31B has fine channel structures 312 inside. These channels can be linear, serpentine or other complex shapes to maximize the flow path of the internal working fluid (usually water or other coolants), thereby increasing the heat exchange area.

[0086] The solid heat pipe 32, also known as a solid heat sink, can achieve efficient heat conduction without the phase change of the internal working fluid. Different from the liquid two-phase flow heat pipe 31, the solid heat pipe 32 does not rely on the evaporation and condensation processes of the liquid to transfer heat, but evenly distributes the thermal energy through the high thermal conductivity of its material itself.

[0087] As Figure 10 and Figure 11 shown, optionally, the solid heat pipe 32 includes a thermally conductive and electrically conductive housing 321 and a solid thermal conductive structure 322. The thermally conductive and electrically conductive housing 321 forms a first cavity, and the solid thermal conductive structure 322 is disposed in the first cavity.

[0088] Similarly, the thermally conductive and electrically conductive housing 321 can be composed of the above-mentioned top plate 303 and bottom plate 304, which will not be elaborated here. The solid thermal conductive structure 322 is made of a solid material with a high thermal conductivity coefficient, such as graphite, copper, aluminum or their composite materials (such as graphite-aluminum composite materials).

[0089] In this way, the solid heat pipe 32 has no liquid working fluid and no leakage risk, and has high reliability and stability on the basis of meeting the corresponding heat conduction requirements.

[0090] As shown Figure 10 in FIG. 3, further, the solid-state heat conduction structure 322 includes a plurality of heat conduction plates 3221, and the plurality of heat conduction plates 3221 are stacked in the first cavity.

[0091] In this way, the corresponding number of layers of heat conduction plates 3221 can be set according to the thickness requirement of the solid-state heat spreader 32. Of course, in another embodiment, the solid-state heat conduction structure 322 may also have only one layer, that is, an integral structure.

[0092] Further, positioning posts 3211 are arranged in the first cavity, and the solid-state heat conduction structure 322 is provided with positioning holes 3222 that are positioned and connected to the positioning posts 3211.

[0093] Exemplarily, positioning holes 3222 are arranged on each heat conduction plate 3221, and the positioning holes 3222 are positioned and connected to the positioning posts 3211.

[0094] As shown Figure 2 in FIGS. 3 5 and 6, in the above embodiment, optionally, the lining plate 2 further includes a second metal layer 23, and the second metal layer 23 and the first metal layer 22 are respectively connected to different sides of the insulating substrate layer 21.

[0095] In this way, the second metal layer 23 can be used to connect to other components, such as welding, and the second metal layer 23 has good heat transfer and conduction performance, which is beneficial to the rapid heat dissipation of the insulating substrate layer 21.

[0096] As shown Figure 4 in FIGS. 5 5 and 6, further, the chip unit further includes a heat dissipation substrate 4, and the insulating substrate layer 21 is connected to the heat dissipation substrate 4 through the second metal layer 23.

[0097] Specifically, the second metal layer 23 is welded to the heat dissipation substrate 4, and the third welding connection layer 63 formed by their welding connection can be referred to Figure 6 .

[0098] In this way, the heat dissipation substrate 4 can further enhance the overall structural stiffness of the chip unit, reduce the possibility of deformation of the chip unit, and can also be used as a connection basis for the subsequent connection of the chip unit to an external structure, and can also be used as a packaging board for subsequent packaging of the chip unit.

[0099] As shown Figure 1 in FIG. 7, in a second aspect, another embodiment of the present invention provides a semiconductor packaging device, which includes a packaging structure 5 and the chip unit as described in the above embodiment. The packaging structure 5 forms a packaging cavity, and the packaging cavity is at least used to accommodate the chip 1, the heat conduction and conductive plate 3, and the first metal layer 22 of the chip unit.

[0100] Reference Figure 1 As shown, optionally, the liner 2 has a second metal layer 23. The chip 1, the heat-conducting and electrically-conductive plate 3 and the liner 2 are encapsulated in the encapsulation cavity, but the second metal layer 23 of the liner 2 is exposed.

[0101] Reference Figures 4 to 6 As shown, optionally, the chip unit has a heat dissipation substrate 4, and the encapsulation structure 5 and the heat dissipation substrate 4 together enclose an encapsulation cavity. It should be understood that Figures 4 to 6 in [the figure], for ease of understanding, the top cover of the encapsulation structure 5 is not shown.

[0102] The semiconductor encapsulation device can be a power device, etc., and one or more power chips 1 are encapsulated therein. For example, the semiconductor power device can be a single-chip 1 device, or can also be a multi-chip 1 device. For example, it is a power device with a half-bridge or full-bridge function.

[0103] In a second aspect, another embodiment of the present invention provides a power module, which includes the semiconductor encapsulation device of the above embodiment. The power module can be a module including a half-bridge or full-bridge circuit.

[0104] In a third aspect, another embodiment of the present invention provides a power electronic device, and the power electronic device has the power module of the above embodiment. For example, the power electronic device is an inverter, an inverter, etc.

[0105] In a fourth aspect, another embodiment of the present invention provides a power system, which includes the power electronic device of the above embodiment. For example, the power system is a photovoltaic system.

[0106] It should be understood that the above power module, power electronic device and power system have all the beneficial effects of the chip unit, and will not be described in detail here.

[0107] Although the present invention is disclosed as above, the protection scope of the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and these changes and modifications will all fall within the protection scope of the present invention.

Claims

1. A chip unit, characterized in that: The chip unit comprises a chip (1), a backing plate (2) and a heat-conducting and electrically conductive plate (3); the heat-conducting and electrically conductive plate (3) comprises a first surface (301) and a second surface (302) arranged opposite to each other; the backing plate (2) comprises an insulating substrate layer (21) and a first metal layer (22) connected to the insulating substrate layer (21); the first surface (301) of the heat-conducting and electrically conductive plate (3) is connected to the chip (1), and the second surface (302) of the heat-conducting and electrically conductive plate (3) is connected to the first metal layer (22).

2. The chip unit according to claim 1, characterized in that: The first metal layer (22) has at least one conductive region (221); The at least one conductive region (221) comprises at least one set conductive region (2211), the set conductive regions (2211) being provided with the thermally conductive and electrically conductive plates (3) in a one-to-one correspondence, and the thermally conductive and electrically conductive plates (3) are connected to one or more chips (1).

3. The chip unit according to claim 2, characterized in that: When the number of the conductive areas (221) is greater than the number of the set conductive areas (2211), at least one of the conductive areas (221) outside the set conductive areas (2211) is correspondingly provided with the thermally conductive plate (3).

4. The chip unit according to claim 2, characterized in that: The projections of all the chips (1) corresponding to at least one of the thermally conductive and electrically conductive plates (3) on the insulating substrate layer (21) fall within the area covered by the projection of the thermally conductive and electrically conductive plate (3) on the insulating substrate layer (21); the projection of at least one of the thermally conductive and electrically conductive plates (3) on the insulating substrate layer (21) falls within the area covered by the projection of the set conductive area (2211) corresponding to the thermally conductive and electrically conductive plate (3) on the insulating substrate layer (21).

5. The chip unit according to any one of claims 1 to 4, characterized in that: When there are multiple thermally conductive plates (3), the thickness of each thermally conductive plate (3) is consistent, and the thickness of the thermally conductive plate (3) is the distance between the first surface (301) and the second surface (302).

6. The chip unit according to any one of claims 1 to 4, characterized in that: When there are multiple thermally conductive and electrically conducting plates (3), each of the thermally conductive and electrically conducting plates (3) is connected via an insulating structure.

7. The chip unit according to any one of claims 1 to 4, characterized in that: The heat-conducting and electrically-conductive plate (3) is any one of a solid metal plate, a liquid two-phase flow temperature-averaging plate (31) and a solid temperature-averaging plate (32) (32).

8. The chip unit according to claim 7, characterized in that: The liquid two-phase flow temperature averaging plate (31) comprises any one of a column-type temperature averaging plate (31A) and a channel-type temperature averaging plate (31B); A column structure (311) is arranged in the hollow sealed cavity of the column-type temperature equalizing plate (31A), and the column structure (311) has a microchannel or a capillary structure for phase change circulation of a working medium; The channel-type temperature-averaging plate (31B) has a fine channel structure (312) inside.

9. The chip unit according to claim 7, characterized in that: The solid-state temperature homogenizing plate (32) (32) comprises a heat-conducting and electrically conductive shell (321) and a solid-state heat-conducting structure (322); the heat-conducting and electrically conductive shell (321) forms a first cavity; and the solid-state heat-conducting structure (322) is disposed in the first cavity.

10. The chip unit according to claim 9, characterized in that: A positioning column (3211) is provided in the first cavity, and a positioning hole (3222) is provided in the solid heat-conducting structure (322) which is positioned and connected to the positioning column (3211); And / or, the solid heat-conducting structure (322) comprises a plurality of heat-conducting plates (3221), and the plurality of heat-conducting plates (3221) are stacked and arranged in the first cavity.

11. The chip unit according to any one of claims 1 to 4, characterized in that: The chip unit further comprises a heat dissipation substrate (4), the backing plate (2) further comprises a second metal layer (23), the second metal layer (23) and the first metal layer (22) are respectively connected to different sides of the insulating substrate layer (21); the insulating substrate layer (21) is connected to the heat dissipation substrate (4) via the second metal layer (23).

12. A semiconductor packaging device, characterized in that: It comprises a packaging structure (5) and a chip unit as claimed in any one of claims 1 to 11, wherein the packaging structure (5) is formed with a packaging cavity, and the packaging cavity is used to accommodate at least a chip (1), a heat-conducting and electrically-conducting plate (3) and a first metal layer (22) of the chip unit.

13. A power electronic device, characterized in that: Comprising the semiconductor package device as claimed in claim 12; and / or comprising the chip unit as claimed in any one of claims 1 to 11.

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