Chip packaging structure and memory
By using the electrical connection between the chipset and the conductive bump in a multi-chip package, the problems of reduced power supply flow capacity and signal quality caused by the long distance of the chip interconnection lines on the substrate in the prior art are solved, and the effects of simplifying the packaging steps, shortening the interconnect length, reducing resistance and improving signal quality are achieved.
Patent Information
- Application Number
- CN202421932236.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-08-09
AI Technical Summary
In existing multi-chip packages, when the chip interconnection lines on the substrate are far away, bonded wire interconnection problems such as long wire length and thin wire diameter, resulting in reduced power supply flow capacity and reduced signal quality.
A chip packaging structure is adopted, which includes at least one chip set, each chip set consisting of a first chip and a second chip, both of which each have a wiring layer and are electrically connected by a plurality of spaced conductive bumps, simplifying the packaging steps of the chip, shortening the interconnection length between the chips, and reducing interconnection resistance.
Through this chip packaging structure, the connection of multiple chip parts is completed without the need to be connected by lead interconnection, which simplifies the packaging steps, improves the transmission quality of signal lines, and reduces costs.
Smart Images
Figure CN222927488U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of chip packaging, and particularly to a chip packaging structure and a memory. Background Art
[0002] Currently, the interconnection between two chips in multi-chip packaging is generally achieved through substrate lines or bonding wires. When the interconnection lines between chips on the substrate are relatively far apart, the bonding wire interconnection method between the two chips has the disadvantages of long bonding wires, long wire lengths, and thin wire diameters, resulting in a decrease in the power conduction capacity of the circuit and a decline in the quality of transmitted signals. Summary of the Utility Model
[0003] In view of this, this application provides a chip packaging structure and a memory, aiming to solve one of the technical problems in the prior art.
[0004] To achieve the above object, the technical solution adopted in this application is as follows:
[0005] In a first aspect, an embodiment of this application provides a chip packaging structure, including:
[0006] At least one chip group, each chip group includes a first chip and at least one second chip, the first chip has a first wiring layer, the second chip has a second wiring layer, the first wiring layer and the second wiring layer are relatively spaced apart, the first wiring layer has a plurality of first conductive bumps spaced apart, the second wiring layer has a plurality of second conductive bumps spaced apart, and the first conductive bumps and the second conductive bumps are arranged in one-to-one correspondence and electrically connected;
[0007] A substrate, and a plurality of the chip groups are spaced apart on the substrate and are respectively electrically connected to the substrate.
[0008] In one of the embodiments of the first aspect, the first chip is disposed on the substrate, the first wiring layer faces away from the substrate, the second chip is flip-chip mounted on the first chip, or at least one of the second chips is disposed on the substrate, the second wiring layer faces away from the substrate, and the first chip is flip-chip mounted on the second chip.
[0009] In one of the embodiments of the first aspect, the first conductive bumps and the second conductive bumps are welded.
[0010] In one of the embodiments of the first aspect, the first conductive bumps and the second conductive bumps are solder bumps.
[0011] In one of the embodiments of the first aspect, the first conductive bumps and the second conductive bumps are copper pillar bumps.
[0012] In one embodiment of the first aspect, a plurality of spaced-apart encapsulation regions are provided on the surface of the substrate, and one of the chip groups is correspondingly provided in each of the encapsulation regions.
[0013] In one embodiment of the first aspect, the encapsulation region includes a placement area and a bonding area. The placement area is received in the bonding area, and the chip group is disposed in the placement area so that the bonding area surrounds the outside of the chip group.
[0014] In one embodiment of the first aspect, in the bonding area, the first chip and / or the second chip are connected to the substrate by bonding wires.
[0015] In one embodiment of the first aspect, the chip packaging structure further includes a glue part, and the glue part seals the entire encapsulation region and seals the chip group and the bonding wires.
[0016] In a second aspect, an embodiment of the present application further provides a memory, including the chip packaging structure in any of the above embodiments, and the chip packaging structure is disposed on a main board.
[0017] Compared with the prior art, the beneficial effect of the present application is that the present application proposes a chip packaging structure, including at least one chip group and a substrate. A plurality of chip groups are spaced apart and disposed on the substrate and are respectively electrically connected to the substrate; each chip group includes a first chip and at least one second chip. The first chip has a first wiring layer, and the second chip has a second wiring layer. The first wiring layer and the second wiring layer are relatively spaced apart. By providing that the first wiring layer has a plurality of spaced-apart first conductive bumps, and the second wiring layer has a plurality of spaced-apart second conductive bumps, and making the first conductive bumps and the second conductive bumps correspond to each other and be electrically connected, in this way, there is no need to use the lead interconnection method to complete the connection of multiple chip components, simplifying the chip packaging steps, realizing shortening the interconnection length between the first chip and the second chip, reducing the interconnection resistance, and improving the signal line transmission quality in the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.
[0019] Figure 1 Shows one of the structural schematic diagrams of the chip packaging structure in some embodiments of the present application;
[0020] Figure 2Shows the second structural schematic diagram of the chip packaging structure in some embodiments of the present application.
[0021] Main component symbol description: 100 - chip packaging structure; 110 - chip group; 120 - substrate; 111 - first chip; 112 - second chip; 1111 - first conductive bump; 1121 - second conductive bump; 121 - packaging area; 1211 - placement area; 1212 - bonding area; 122 - bonding wire. Detailed implementation manners
[0022] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.
[0023] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.
[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.
[0025] In the present application, unless otherwise clearly specified and defined, the terms "mounted", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0026] In this application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply indicates that the horizontal height of the first feature is less than that of the second feature.
[0027] As Figure 1 and Figure 2 shown, an embodiment of the present application provides a chip packaging structure 100, which is mainly used to achieve wireless connection of multiple chips.
[0028] The chip packaging structure 100 includes at least one chip group 110 and a substrate 120.
[0029] Among them, multiple chip groups 110 are arranged on the substrate 120 at intervals and are respectively electrically connected to the substrate 120. By spacing the multiple chip groups 110, a certain space is reserved to prevent mutual contact interference between the wires and the chips. At the same time, it is convenient to individually package each chip group 110.
[0030] Each chip group 110 includes a first chip 111 and a second chip 112 stacked. The first chip 111 has a first wiring layer (not shown in the figure), and the second chip 112 has a second wiring layer (not shown in the figure). The first wiring layer and the second wiring layer are arranged relatively at intervals. The first wiring layer has a plurality of first conductive bumps 1111 arranged at intervals, and the second wiring layer has a plurality of second conductive bumps 1121 arranged at intervals.
[0031] It should be noted that the wiring layer is used to change the contact positions of the original designed chip circuit connection points (I / O pads) through the wafer-level metal wiring process and the bump process, so that the chips can be suitable for different packaging forms.
[0032] In addition, by setting the first conductive bumps 1111 and the second conductive bumps 1121 to be arranged in one-to-one correspondence and electrically connected, there is no need to use the way of lead interconnection to complete the connection of multiple chip components, which simplifies the chip packaging steps, realizes shortening the interconnection length between the first chip 111 and the second chip 112, reduces the interconnection resistance, and improves the signal line transmission quality in the chip packaging structure 100.
[0033] When the number of the second chips 112 is one, the second chip 112 and the first chip 111 are stacked so that the second wiring layer and the first wiring layer are disposed at a relative interval, facilitating the docking of the first conductive bumps 1111 and the second conductive bumps 1121. There is no particular limitation on the sizes of the first chip 111 and the second chip 112, and the number of the first conductive bumps 1111 of the first chip 111 and the number of the second conductive bumps 1121 of the second chip 112 can be set as required.
[0034] When the number of the second chips 112 is two or more, each second chip 112 is stacked with the first chip 111, and the second chips 112 are spaced apart and disposed on the same side of the first chip 111. The second wiring layer of each second chip 112 and the first wiring layer of the first chip 111 are disposed at a relative interval, facilitating the docking of the first conductive bumps 1111 and the second conductive bumps 1121. There is no particular limitation on the sizes of the first chip 111 and the second chip 112, and the number of the first conductive bumps 1111 of the first chip 111 and the number of the second conductive bumps 1121 of the second chip 112 can be set as required.
[0035] It should be noted that the first chip 111 refers to a single bare die, or the first chip 111 refers to a structure formed by stacking or connecting two or more bare dies. When the first chip 111 has multiple bare dies, the first wiring layer is disposed at the top or bottom of the first chip 111.
[0036] Similarly, the second chip 112 refers to a single bare die, or the second chip 112 refers to a structure formed by stacking or connecting two or more bare dies. When the second chip 112 has multiple bare dies, the second wiring layer is disposed at the top or bottom of the first chip 111.
[0037] In some embodiments, the first chip 111 is disposed on the substrate 120, the first wiring layer faces away from the substrate 120, the second wiring layer faces the substrate 120, and the second chip 112 is flip-chip disposed on the first chip 111. One side of the first chip 111 away from the first wiring layer is bonded to the substrate 120 with glue to fix the first chip 111 on the substrate 120, facilitating subsequent wire bonding of the chip set 110 and the substrate 120.
[0038] Alternatively, at least one second chip 112 is disposed on the substrate 120, the second wiring layer faces away from the substrate 120, the first wiring layer faces the substrate 120, and the first chip 111 is flip-chip disposed on the second chip 112. One side of the second chip 112 away from the second wiring layer is bonded to the substrate 120 with glue to fix the second chip 112 on the substrate 120, facilitating subsequent wire bonding of the chip set 110 and the substrate 120.
[0039] In some embodiments, the first conductive bump 1111 and the second conductive bump 1121 are soldered.
[0040] For example, the first conductive bump 1111 and the second conductive bump 1121 are solder bumps. In this way, the two solder bumps are soldered to achieve electrical connection, eliminating the need for wire interconnection to complete the connection of multiple chip components, simplifying the chip packaging steps, shortening the interconnection length between the first chip 111 and the second chip 112, reducing the interconnection resistance, improving the transmission quality of the signal lines in the chip packaging structure 100, and also reducing costs and simplifying the chip connection process.
[0041] For example, the first conductive bump 1111 and the second conductive bump 1121 are copper pillar bumps. In this way, the two solder bumps are soldered to achieve electrical connection, eliminating the need for wire interconnection to complete the connection of multiple chip components, simplifying the chip packaging steps, shortening the interconnection length between the first chip 111 and the second chip 112, reducing the interconnection resistance, improving the transmission quality of the signal lines in the chip packaging structure 100, and also reducing costs. Moreover, by utilizing the rigidity of the copper pillars, the spacer structure between the first chip 111 and the second chip 112 can be made more stable, especially when the first chip 111 or the second chip 112 has multiple bare dies.
[0042] In some embodiments, a plurality of spaced-apart packaging regions 121 are provided on the surface of the substrate 120, and each packaging region 121 corresponds to a chip group 110. In this way, during packaging, each chip group 110 can be packaged separately.
[0043] In some embodiments, as Figure 2 shown, the packaging region 121 includes a placement area 1211 and a bonding area 1212, and the placement area 1211 is received within the bonding area 1212. The position and size of the bonding area 1212 are related to the bonding points of the chip group 110.
[0044] In this embodiment, it is necessary to fan out the signals to the substrate 120 through the bonding wires 122 to solve the problem of the difficulty in fanning out the signals of the chip group 110. Therefore, preferably, the bonding points of the chip group 110 are set on the outer periphery of the chip group 110.
[0045] In some embodiments, the chip group 110 is disposed in the placement area 1211 such that the bonding area 1212 surrounds the outside of the chip group 110.
[0046] Exemplarily, the bonding area 1212 is set as an annular structure, and the placement area 1211 is received within the ring.
[0047] Exemplarily, the bonding area 1212 is two spaced-apart areas, and the placement area 1211 is disposed between the two bonding areas 1212.
[0048] Exemplarily, the bonding area 1212 has a structure such as V-shaped, U-shaped, arc-shaped, or polyline-shaped, and the bonding area 1212 is arranged on the peripheral side of the chipset 110 and corresponding to the bonding points.
[0049] In some embodiments, within the bonding area 1212, the first chip 111 and / or the second chip 112 are connected to the substrate 120 through bonding wires 122. The power supply or ground port in each chipset 110 is connected to the substrate 120 through leads, and the signals of the chipset 110 are fanned out to the substrate 120 nearby through the bonding wires 122, shortening the wire bonding distance and reducing the wire bonding cost.
[0050] In some embodiments, the chip packaging structure 100 further includes a glue part (not shown in the figure), and the glue part seals the entire packaging area 121 and seals the chipset 110 and the bonding wires 122. For example, the chipset 110 and the bonding wires 122 are wrapped by epoxy resin to form a stacked packaging structure of the chipset 110.
[0051] The present application also provides a memory, including the chip packaging structure 100 in any of the above embodiments, and the chip packaging structure 100 is arranged on the main board. Therefore, it has all the beneficial effects of the chip packaging structure 100 in any of the above embodiments, and will not be elaborated here one by one.
[0052] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0053] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.
Claims
1. A chip packaging structure, characterized in that: include: At least one chipset, each of the chipset comprising a first chip and at least one second chip, the first chip having a first wiring layer, the second chip having a second wiring layer, the first wiring layer and the second wiring layer being arranged with a relative interval, the first wiring layer having a plurality of first conductive bumps arranged with a interval, the second wiring layer having a plurality of second conductive bumps arranged with a interval, the first conductive bumps and the second conductive bumps being arranged with a one-to-one correspondence and electrically connected; A substrate, a plurality of the chip groups are arranged on the substrate at intervals and are electrically connected to the substrate respectively.
2. The chip packaging structure according to claim 1, characterized in that: The first chip is disposed on the substrate, the first wiring layer is away from the substrate, and the second chip is flip-chip disposed on the first chip; or The at least one second chip is disposed on the substrate, the second wiring layer is away from the substrate, and the first chip is flip-chip disposed on the second chip.
3. The chip packaging structure according to claim 1, characterized in that: The first conductive bump and the second conductive bump are welded.
4. The chip packaging structure according to claim 1, characterized in that: The first conductive bump and the second conductive bump are solder bumps.
5. The chip packaging structure according to claim 1, characterized in that: The first conductive bump and the second conductive bump are copper pillar bumps.
6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: A plurality of packaging areas are arranged at intervals on the surface of the substrate, and each packaging area corresponds to one of the chipsets.
7. The chip packaging structure according to claim 6, characterized in that: The packaging area includes a placement area and a bonding area. The placement area is accommodated in the bonding area. The chipset is arranged in the placement area so that the bonding area is surrounded by the outside of the chipset.
8. The chip packaging structure according to claim 7, characterized in that: In the bonding area, the first chip and / or the second chip is connected to the substrate via bonding wires.
9. The chip packaging structure according to claim 8, characterized in that: The chip packaging structure further includes a glue portion, which seals the entire packaging area and seals the chipset and the bonding wires.
10. A memory, characterized in that: The chip packaging structure comprises the chip packaging structure according to any one of claims 1 to 9, wherein the chip packaging structure is arranged on a mainboard.